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This commit is contained in:
Sascha Nesterovic
2025-08-11 14:29:00 +02:00
parent c66122e619
commit 4d134a1294
2688 changed files with 1127995 additions and 11475 deletions
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1
include/dt-bindings/arm/msm/qcom_dma_heap_dt_constants.h Symbolic link
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@@ -0,0 +1 @@
../../../linux/qcom_dma_heap_dt_constants.h

14
include/dt-bindings/arm/msm/qti-smmu-proxy-dt-ids.h Normal file
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@@ -0,0 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _QTI_SMMU_PROXY_DT_IDS_H
#define _QTI_SMMU_PROXY_DT_IDS_H
#define QTI_SMMU_PROXY_CAMERA_CB 0
#define QTI_SMMU_PROXY_DISPLAY_CB 1
#define QTI_SMMU_PROXY_EVA_CB 2
#define QTI_SMMU_PROXY_CB_IDS_LEN 3
#endif /* _QTI_SMMU_PROXY_DT_IDS_H */

20
include/dt-bindings/arm/qcom,ids.h
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@@ -231,6 +231,7 @@
#define QCOM_ID_QCS4290 470
#define QCOM_ID_SM8450_2 480
#define QCOM_ID_SM8450_3 482
#define QCOM_ID_MONACO 486
#define QCOM_ID_SC7280 487
#define QCOM_ID_SC7180P 495
#define QCOM_ID_IPQ5000 503
@@ -248,9 +249,15 @@
#define QCOM_ID_QRB4210 523
#define QCOM_ID_QRB2210 524
#define QCOM_ID_SA8775P 534
#define QCOM_ID_PARROT 537
#define QCOM_ID_QRU1000 539
#define QCOM_ID_QDU1000 545
#define QCOM_ID_X1E80100 555
#define QCOM_ID_PINEAPPLE 557
#define QCOM_ID_SM4450 568
#define QCOM_ID_RAVELIN 568
#define QCOM_ID_PINEAPPLEP 577
#define QCOM_ID_PARROTP 583
#define QCOM_ID_QDU1010 587
#define QCOM_ID_QRU1032 588
#define QCOM_ID_QRU1052 589
@@ -259,7 +266,20 @@
#define QCOM_ID_IPQ5322 593
#define QCOM_ID_IPQ5312 594
#define QCOM_ID_IPQ5302 595
#define QCOM_ID_RAVELINP 602
#define QCOM_ID_PARROT7 613
#define QCOM_ID_SUN 618
#define QCOM_ID_IPQ5300 624
#define QCOM_ID_PARROTQ 631
#define QCOM_ID_SG_PARROT 633
#define QCOM_ID_SG_PARROTP 634
#define QCOM_ID_PARROT7P 638
#define QCOM_ID_SUNP 639
#define QCOM_ID_SG_RAVELIN 653
#define QCOM_ID_SG_RAVELINP 654
#define QCOM_ID_TUNA 655
#define QCOM_ID_KERA 659
#define QCOM_ID_PARROTPRO 663
/*
* The board type and revision information, used by Qualcomm bootloaders and

398
include/dt-bindings/battery/sec-battery.h Normal file
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@@ -0,0 +1,398 @@
#ifndef _DT_BINDINGS_BATTERY_SEC_BATTERY_H
#define _DT_BINDINGS_BATTERY_SEC_BATTERY_H
#define SEC_BATTERY_CABLE_UNKNOWN 0
#define SEC_BATTERY_CABLE_NONE 1
#define SEC_BATTERY_CABLE_PREPARE_TA 2
#define SEC_BATTERY_CABLE_TA 3
#define SEC_BATTERY_CABLE_USB 4
#define SEC_BATTERY_CABLE_USB_CDP 5
#define SEC_BATTERY_CABLE_9V_TA 6
#define SEC_BATTERY_CABLE_9V_ERR 7
#define SEC_BATTERY_CABLE_9V_UNKNOWN 8
#define SEC_BATTERY_CABLE_12V_TA 9
#define SEC_BATTERY_CABLE_WIRELESS 10
#define SEC_BATTERY_CABLE_HV_WIRELESS 11
#define SEC_BATTERY_CABLE_PMA_WIRELESS 12
#define SEC_BATTERY_CABLE_WIRELESS_PACK 13
#define SEC_BATTERY_CABLE_WIRELESS_HV_PACK 14
#define SEC_BATTERY_CABLE_WIRELESS_STAND 15
#define SEC_BATTERY_CABLE_WIRELESS_HV_STAND 16
#define SEC_BATTERY_CABLE_QC20 17
#define SEC_BATTERY_CABLE_QC30 18
#define SEC_BATTERY_CABLE_PDIC 19
#define SEC_BATTERY_CABLE_UARTOFF 20
#define SEC_BATTERY_CABLE_OTG 21
#define SEC_BATTERY_CABLE_LAN_HUB 22
#define SEC_BATTERY_CABLE_POWER_SHARING 23
#define SEC_BATTERY_CABLE_HMT_CONNECTED 24
#define SEC_BATTERY_CABLE_HMT_CHARGE 25
#define SEC_BATTERY_CABLE_HV_TA_CHG_LIMIT 26
#define SEC_BATTERY_CABLE_WIRELESS_VEHICLE 27
#define SEC_BATTERY_CABLE_WIRELESS_HV_VEHICLE 28
#define SEC_BATTERY_CABLE_PREPARE_WIRELESS_HV 29
#define SEC_BATTERY_CABLE_TIMEOUT 30
#define SEC_BATTERY_CABLE_SMART_OTG 31
#define SEC_BATTERY_CABLE_SMART_NOTG 32
#define SEC_BATTERY_CABLE_WIRELESS_TX 33
#define SEC_BATTERY_CABLE_HV_WIRELESS_20 34
#define SEC_BATTERY_CABLE_HV_WIRELESS_20_LIMIT 35
#define SEC_BATTERY_CABLE_WIRELESS_FAKE 36
#define SEC_BATTERY_CABLE_PREPARE_WIRELESS_20 37
#define SEC_BATTERY_CABLE_PDIC_APDO 38
#define SEC_BATTERY_CABLE_POGO 39
#define SEC_BATTERY_CABLE_POGO_9V 40
#define SEC_BATTERY_CABLE_FPDO_DC 41
#define SEC_BATTERY_CABLE_WIRELESS_EPP 42
#define SEC_BATTERY_CABLE_LO_TA 43
#define SEC_BATTERY_CABLE_WIRELESS_EPP_NV 44
#define SEC_BATTERY_CABLE_WIRELESS_EPP_FAKE 45
#define SEC_BATTERY_CABLE_HV_WIRELESS_DC 46
#define SEC_BATTERY_CABLE_WIRELESS_MPP 47
#define SEC_BATTERY_CABLE_WIRELESS_MPP_FAKE 48
#define SEC_BATTERY_CABLE_MAX 49
/* d2d support type */
#define SB_D2D_NONE 0
#define SB_D2D_SNKONLY 1
#define SB_D2D_SRCSNK 2
/* temperature check type */
#define SEC_BATTERY_TEMP_CHECK_NONE 0 /* no temperature check */
#define SEC_BATTERY_TEMP_CHECK_ADC 1 /* by ADC value */
#define SEC_BATTERY_TEMP_CHECK_TEMP 2 /* by temperature */
#define SEC_BATTERY_TEMP_CHECK_FAKE 3 /* by a fake temperature */
/* ADC type */
/* NOT using this ADC channel */
#define SEC_BATTERY_ADC_TYPE_NONE 0
/* ADC in AP */
#define SEC_BATTERY_ADC_TYPE_AP 1
/* ADC by additional IC */
#define SEC_BATTERY_ADC_TYPE_IC 2
#define SEC_BATTERY_ADC_TYPE_NUM 3
/* ADC read type */
#define SEC_BATTERY_ADC_PROCESSED 0
#define SEC_BATTERY_ADC_RAW 1
/* thermal source */
/* none */
#define SEC_BATTERY_THERMAL_SOURCE_NONE 0
/* by external source */
#define SEC_BATTERY_THERMAL_SOURCE_CALLBACK 1
/* by ADC */
#define SEC_BATTERY_THERMAL_SOURCE_ADC 2
/* by charger */
#define SEC_BATTERY_THERMAL_SOURCE_CHG_ADC 3
/* by fuel gauge */
#define SEC_BATTERY_THERMAL_SOURCE_FG 4
/* by fuel gauge adc */
#define SEC_BATTERY_THERMAL_SOURCE_FG_ADC 5
#define SEC_BATTERY_CABLE_CHECK_NOUSBCHARGE 1
/* SEC_BATTERY_CABLE_CHECK_NOINCOMPATIBLECHARGE
* for incompatible charger
* (Not compliant to USB specification,
* cable type is SEC_BATTERY_CABLE_UNKNOWN),
* do NOT charge and show message to user
* (only for VZW)
*/
#define SEC_BATTERY_CABLE_CHECK_NOINCOMPATIBLECHARGE 2
/* SEC_BATTERY_CABLE_CHECK_PSY
* check cable by power supply set_property
*/
#define SEC_BATTERY_CABLE_CHECK_PSY 4
/* SEC_BATTERY_CABLE_CHECK_INT
* check cable by interrupt
*/
#define SEC_BATTERY_CABLE_CHECK_INT 8
/* SEC_BATTERY_CABLE_CHECK_CHGINT
* check cable by charger interrupt
*/
#define SEC_BATTERY_CABLE_CHECK_CHGINT 16
/* SEC_BATTERY_CABLE_CHECK_POLLING
* check cable by GPIO polling
*/
#define SEC_BATTERY_CABLE_CHECK_POLLING 32
/* SEC_BATTERY_CABLE_SOURCE_EXTERNAL
* already given by external argument
*/
#define SEC_BATTERY_CABLE_SOURCE_EXTERNAL 1
/* SEC_BATTERY_CABLE_SOURCE_CALLBACK
* by callback (MUIC, USB switch)
*/
#define SEC_BATTERY_CABLE_SOURCE_CALLBACK 2
/* SEC_BATTERY_CABLE_SOURCE_ADC
* by ADC
*/
#define SEC_BATTERY_CABLE_SOURCE_ADC 4
/* polling work queue */
#define SEC_BATTERY_MONITOR_WORKQUEUE 0
/* alarm polling */
#define SEC_BATTERY_MONITOR_ALARM 1
/* timer polling (NOT USE) */
#define SEC_BATTERY_MONITOR_TIMER 2
/* OVP, UVLO check : POWER_SUPPLY_PROP_HEALTH */
/* by callback function */
#define SEC_BATTERY_OVP_UVLO_CALLBACK 0
/* by PMIC polling */
#define SEC_BATTERY_OVP_UVLO_PMICPOLLING 1
/* by PMIC interrupt */
#define SEC_BATTERY_OVP_UVLO_PMICINT 2
/* by charger polling */
#define SEC_BATTERY_OVP_UVLO_CHGPOLLING 3
/* by charger interrupt */
#define SEC_BATTERY_OVP_UVLO_CHGINT 4
/* full charged check : POWER_SUPPLY_PROP_STATUS */
#define SEC_BATTERY_FULLCHARGED_NONE 0
/* current check by ADC */
#define SEC_BATTERY_FULLCHARGED_ADC 1
/* fuel gauge current check */
#define SEC_BATTERY_FULLCHARGED_FG_CURRENT 2
/* time check */
#define SEC_BATTERY_FULLCHARGED_TIME 3
/* SOC check */
#define SEC_BATTERY_FULLCHARGED_SOC 4
/* charger GPIO, NO additional full condition */
#define SEC_BATTERY_FULLCHARGED_CHGGPIO 5
/* charger interrupt, NO additional full condition */
#define SEC_BATTERY_FULLCHARGED_CHGINT 6
/* charger power supply property, NO additional full condition */
#define SEC_BATTERY_FULLCHARGED_CHGPSY 7
/* Limiter power supply property, NO additional full condition */
#define SEC_BATTERY_FULLCHARGED_LIMITER 8
#define TEMP_CONTROL_SOURCE_NONE 0
#define TEMP_CONTROL_SOURCE_BAT_THM 1
#define TEMP_CONTROL_SOURCE_CHG_THM 2
#define TEMP_CONTROL_SOURCE_WPC_THM 3
#define TEMP_CONTROL_SOURCE_USB_THM 4
/* SEC_BATTERY_FULL_CONDITION_NOTIMEFULL
* full-charged by absolute-timer only in high voltage
*/
#define SEC_BATTERY_FULL_CONDITION_NOTIMEFULL 1
/* SEC_BATTERY_FULL_CONDITION_NOSLEEPINFULL
* do not set polling time as sleep polling time in full-charged
*/
#define SEC_BATTERY_FULL_CONDITION_NOSLEEPINFULL 2
/* SEC_BATTERY_FULL_CONDITION_SOC
* use capacity for full-charged check
*/
#define SEC_BATTERY_FULL_CONDITION_SOC 4
/* SEC_BATTERY_FULL_CONDITION_VCELL
* use VCELL for full-charged check
*/
#define SEC_BATTERY_FULL_CONDITION_VCELL 8
/* SEC_BATTERY_FULL_CONDITION_AVGVCELL
* use average VCELL for full-charged check
*/
#define SEC_BATTERY_FULL_CONDITION_AVGVCELL 16
/* SEC_BATTERY_FULL_CONDITION_OCV
* use OCV for full-charged check
*/
#define SEC_BATTERY_FULL_CONDITION_OCV 32
/* recharge check condition type (can be used overlapped) */
#define sec_battery_recharge_condition_t unsigned int
/* SEC_BATTERY_RECHARGE_CONDITION_SOC
* use capacity for recharging check
*/
#define SEC_BATTERY_RECHARGE_CONDITION_SOC 1
/* SEC_BATTERY_RECHARGE_CONDITION_AVGVCELL
* use average VCELL for recharging check
*/
#define SEC_BATTERY_RECHARGE_CONDITION_AVGVCELL 2
/* SEC_BATTERY_RECHARGE_CONDITION_VCELL
* use VCELL for recharging check
*/
#define SEC_BATTERY_RECHARGE_CONDITION_VCELL 4
/* SEC_BATTERY_RECHARGE_CONDITION_LIMITER
* use VCELL of LIMITER for recharging check
*/
#define SEC_BATTERY_RECHARGE_CONDITION_LIMITER 8
/* SEC_BATTERY_RECHARGE_CONDITION_DUAL_BATTERY_INDIVIDUAL_FV
* use VCELL of LIMITER for dual battery individual fv recharging check
*/
#define SEC_BATTERY_RECHARGE_CONDITION_DUAL_BATTERY_INDIVIDUAL_FV 16
#define SIOP_DEFAULT 0xFFFF
#define SIOP_SKIP 0xFFFE
/* inbat ocv type */
#define SEC_BATTERY_OCV_NONE 0
#define SEC_BATTERY_OCV_FG_SRC_CHANGE 1
#define SEC_BATTERY_OCV_FG_NOSRC_CHANGE 2
#define SEC_BATTERY_OCV_ADC 3
#define SEC_BATTERY_OCV_VOLT_FROM_PMIC 4
/* enum sec_wireless_rx_power_list */
#define SEC_WIRELESS_RX_POWER_3W 3000000
#define SEC_WIRELESS_RX_POWER_5W 5000000
#define SEC_WIRELESS_RX_POWER_6_5W 6500000
#define SEC_WIRELESS_RX_POWER_7_5W 7500000
#define SEC_WIRELESS_RX_POWER_10W 10000000
#define SEC_WIRELESS_RX_POWER_11W 11000000
#define SEC_WIRELESS_RX_POWER_12W 12000000
#define SEC_WIRELESS_RX_POWER_15W 15000000
#define SEC_WIRELESS_RX_POWER_17_5W 17500000
#define SEC_WIRELESS_RX_POWER_20W 20000000
#define SEC_WIRELESS_RX_POWER_MAX 20000000
/* enum sec_wireless_rx_power_class_list */
#define SEC_WIRELESS_RX_POWER_CLASS_1 1 /* 4.5W ~ 7.5W */
#define SEC_WIRELESS_RX_POWER_CLASS_2 2 /* 7.6W ~ 12W */
#define SEC_WIRELESS_RX_POWER_CLASS_3 3 /* 12.1W ~ 20W */
#define SEC_WIRELESS_RX_POWER_CLASS_4 4 /* reserved */
#define SEC_WIRELESS_RX_POWER_CLASS_5 5 /* reserved */
#define SEC_WIRELESS_PHM_VOUT_CTRL_NO_DEV 0
#define SEC_WIRELESS_PHM_VOUT_CTRL_OTHER_DEV 1
#define SEC_WIRELESS_PHM_VOUT_CTRL_GEAR 2
#define SEC_WIRELESS_PHM_VOUT_CTRL_PHONE 4
#define SEC_WIRELESS_PHM_VOUT_CTRL_BUDS 8
/* enum sec_wireless_rx_control_mode */
#define WIRELESS_PAD_FAN_OFF 0
#define WIRELESS_PAD_FAN_ON 1
#define WIRELESS_PAD_LED_OFF 2
#define WIRELESS_PAD_LED_ON 3
#define WIRELESS_PAD_LED_DIMMING 4
#define WIRELESS_VRECT_ADJ_ON 5
#define WIRELESS_VRECT_ADJ_OFF 6
#define WIRELESS_VRECT_ADJ_ROOM_0 7
#define WIRELESS_VRECT_ADJ_ROOM_1 8
#define WIRELESS_VRECT_ADJ_ROOM_2 9
#define WIRELESS_VRECT_ADJ_ROOM_3 10
#define WIRELESS_VRECT_ADJ_ROOM_4 11
#define WIRELESS_VRECT_ADJ_ROOM_5 12
#define WIRELESS_CLAMP_ENABLE 13
#define WIRELESS_SLEEP_MODE_ENABLE 14
#define WIRELESS_SLEEP_MODE_DISABLE 15
/* enum sec_wireless_tx_vout */
#define WC_TX_VOUT_OFF 0
#define WC_TX_VOUT_5000MV 5000
#define WC_TX_VOUT_5500MV 5500
#define WC_TX_VOUT_6000MV 6000
#define WC_TX_VOUT_6500MV 6500
#define WC_TX_VOUT_7000MV 7000
#define WC_TX_VOUT_7500MV 7500
#define WC_TX_VOUT_8000MV 8000
#define WC_TX_VOUT_8500MV 8500
#define WC_TX_VOUT_9000MV 9000
#define WC_TX_VOUT_MIN WC_TX_VOUT_5000MV
#define WC_TX_VOUT_MAX WC_TX_VOUT_9000MV
#define WC_TX_VOUT_STEP_AOV 500
/* enum sec_wireless_vout_control_mode */
#define WIRELESS_VOUT_OFF 0
#define WIRELESS_VOUT_NORMAL_VOLTAGE 1 /* 5V , reserved by factory */
#define WIRELESS_VOUT_RESERVED 2 /* 6V */
#define WIRELESS_VOUT_HIGH_VOLTAGE 3 /* 9V , reserved by factory */
#define WIRELESS_VOUT_CC_CV_VOUT 4
#define WIRELESS_VOUT_CALL 5
#define WIRELESS_VOUT_5V 6
#define WIRELESS_VOUT_9V 7
#define WIRELESS_VOUT_10V 8
#define WIRELESS_VOUT_11V 9
#define WIRELESS_VOUT_12V 10
#define WIRELESS_VOUT_12_5V 11
#define WIRELESS_VOUT_4_5V_STEP 12
#define WIRELESS_VOUT_5V_STEP 13
#define WIRELESS_VOUT_5_5V_STEP 14
#define WIRELESS_VOUT_9V_STEP 15
#define WIRELESS_VOUT_10V_STEP 16
#define WIRELESS_VOUT_OTG 17
#define WIRELESS_VOUT_FORCE_9V 18
#define WIRELESS_VOUT_5_5V 19
#define WIRELESS_VOUT_4_5V 20
#define WIRELESS_VOUT_FORCE_4_7V 21
#define WIRELESS_VOUT_FORCE_4_8V 22
#define WIRELESS_VOUT_FORCE_4_9V 23
#define WIRELESS_VOUT_FORCE_5V 24
#define WIRELESS_VOUT_13V 25
#define WIRELESS_VOUT_FORCE_10V 26
#define WIRELESS_VOUT_FORCE_13V 27
/* enum mfc_send_command */
#define MFC_END_SIG_STRENGTH 0
#define MFC_END_POWER_TRANSFER 1
#define MFC_END_CTR_ERROR 2
#define MFC_END_RECEIVED_POWER 3
#define MFC_END_CHARGE_STATUS 4
#define MFC_POWER_CTR_HOLD_OFF 5
#define MFC_AFC_CONF_5V 6
#define MFC_AFC_CONF_10V 7
#define MFC_AFC_CONF_5V_TX 8
#define MFC_AFC_CONF_10V_TX 9
#define MFC_AFC_CONF_12V_TX 10
#define MFC_AFC_CONF_12_5V_TX 11
#define MFC_AFC_CONF_20V_TX 12
#define MFC_CONFIGURATION 13
#define MFC_IDENTIFICATION 14
#define MFC_EXTENDED_IDENT 15
#define MFC_LED_CONTROL_ON 16
#define MFC_LED_CONTROL_OFF 17
#define MFC_FAN_CONTROL_ON 18
#define MFC_FAN_CONTROL_OFF 19
#define MFC_REQUEST_AFC_TX 20
#define MFC_REQUEST_TX_ID 21
#define MFC_DISABLE_TX 22
#define MFC_PHM_ON 23
#define MFC_LED_CONTROL_DIMMING 24
#define MFC_SET_OP_FREQ 25
#define MFC_TX_UNO_OFF 26
#define MFC_REQ_TX_PWR_BUDG 27
#define MFC_VOUT_4_5V 0
#define MFC_VOUT_4_7V 1
#define MFC_VOUT_4_8V 2
#define MFC_VOUT_4_9V 3
#define MFC_VOUT_5V 4
#define MFC_VOUT_5_5V 5
#define MFC_VOUT_6V 6
#define MFC_VOUT_7V 7
#define MFC_VOUT_8V 8
#define MFC_VOUT_9V 9
#define MFC_VOUT_10V 10
#define MFC_VOUT_11V 11
#define MFC_VOUT_12V 12
#define MFC_VOUT_12_5V 13
#define MFC_VOUT_OTG 14
#define MFC_VOUT_13V 15
/* fod macro */
#define FOD_FLAG_NONE 0
#define FOD_FLAG_ADD 1
#define FOD_FLAG_USE_CC 2
#define FOD_FLAG_USE_CV 3
#define FOD_FLAG_USE_FULL 4
#define FOD_FLAG_USE_DEF_PAD 5
#define FOD_FLAG_USE_DEF_OP 6
#define SET_FOD_CC(_flag) (FOD_FLAG_ ##_flag)
#define SET_FOD_CV(_flag) (FOD_FLAG_ ##_flag << 4)
#define SET_FOD_FULL(_flag) (FOD_FLAG_ ##_flag << 8)
#define DC_MODE_NONE 0
#define DC_MODE_1TO1 1 /* Unused */
#define DC_MODE_2TO1 2
#define DC_MODE_3TO1 3
#define DC_MODE_4TO1 4
#define DC_MODE_MAX 10
#endif /* _DT_BINDINGS_BATTERY_SEC_BATTERY_H */

22
include/dt-bindings/clock/qcom,aop-qmp.h Normal file
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@@ -0,0 +1,22 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_AOP_QMP_H
#define _DT_BINDINGS_CLK_QCOM_AOP_QMP_H
#define QDSS_CLK_LEVEL_OFF 0
#define QDSS_CLK_LEVEL_DYNAMIC 1
#define QDSS_CLK_LEVEL_TURBO 2
#define QDSS_CLK_LEVEL_NOMINAL 3
#define QDSS_CLK_LEVEL_SVS_L1 4
#define QDSS_CLK_LEVEL_SVS 5
#define QDSS_CLK_LEVEL_LOW_SVS 6
#define QDSS_CLK_LEVEL_MIN_SVS 7
/* clocks id */
#define QDSS_CLK 0
#define QDSS_AO_CLK 1
#define BIMC_CLK 2
#endif

30
include/dt-bindings/clock/qcom,cambistmclkcc-sun.h Normal file
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@@ -0,0 +1,30 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_CAM_BIST_MCLK_CC_SUN_H
#define _DT_BINDINGS_CLK_QCOM_CAM_BIST_MCLK_CC_SUN_H
/* CAM_BIST_MCLK_CC clocks */
#define CAM_BIST_MCLK_CC_MCLK0_CLK 0
#define CAM_BIST_MCLK_CC_MCLK0_CLK_SRC 1
#define CAM_BIST_MCLK_CC_MCLK1_CLK 2
#define CAM_BIST_MCLK_CC_MCLK1_CLK_SRC 3
#define CAM_BIST_MCLK_CC_MCLK2_CLK 4
#define CAM_BIST_MCLK_CC_MCLK2_CLK_SRC 5
#define CAM_BIST_MCLK_CC_MCLK3_CLK 6
#define CAM_BIST_MCLK_CC_MCLK3_CLK_SRC 7
#define CAM_BIST_MCLK_CC_MCLK4_CLK 8
#define CAM_BIST_MCLK_CC_MCLK4_CLK_SRC 9
#define CAM_BIST_MCLK_CC_MCLK5_CLK 10
#define CAM_BIST_MCLK_CC_MCLK5_CLK_SRC 11
#define CAM_BIST_MCLK_CC_MCLK6_CLK 12
#define CAM_BIST_MCLK_CC_MCLK6_CLK_SRC 13
#define CAM_BIST_MCLK_CC_MCLK7_CLK 14
#define CAM_BIST_MCLK_CC_MCLK7_CLK_SRC 15
#define CAM_BIST_MCLK_CC_PLL0 16
#define CAM_BIST_MCLK_CC_SLEEP_CLK 17
#define CAM_BIST_MCLK_CC_SLEEP_CLK_SRC 18
#endif

117
include/dt-bindings/clock/qcom,camcc-parrot.h Normal file
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@@ -0,0 +1,117 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2021, 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_PARROT_H
#define _DT_BINDINGS_CLK_QCOM_CAM_CC_PARROT_H
/* CAM_CC clocks */
#define CAM_CC_PLL0 0
#define CAM_CC_PLL0_OUT_EVEN 1
#define CAM_CC_PLL0_OUT_ODD 2
#define CAM_CC_PLL1 3
#define CAM_CC_PLL1_OUT_EVEN 4
#define CAM_CC_PLL2 5
#define CAM_CC_PLL2_OUT_EVEN 6
#define CAM_CC_PLL3 7
#define CAM_CC_PLL3_OUT_EVEN 8
#define CAM_CC_PLL4 9
#define CAM_CC_PLL4_OUT_EVEN 10
#define CAM_CC_BPS_AHB_CLK 11
#define CAM_CC_BPS_AREG_CLK 12
#define CAM_CC_BPS_CLK 13
#define CAM_CC_BPS_CLK_SRC 14
#define CAM_CC_CAMNOC_ATB_CLK 15
#define CAM_CC_CAMNOC_AXI_CLK 16
#define CAM_CC_CAMNOC_AXI_CLK_SRC 17
#define CAM_CC_CAMNOC_AXI_HF_CLK 18
#define CAM_CC_CAMNOC_AXI_SF_CLK 19
#define CAM_CC_CCI_0_CLK 20
#define CAM_CC_CCI_0_CLK_SRC 21
#define CAM_CC_CCI_1_CLK 22
#define CAM_CC_CCI_1_CLK_SRC 23
#define CAM_CC_CORE_AHB_CLK 24
#define CAM_CC_CPAS_AHB_CLK 25
#define CAM_CC_CPHY_RX_CLK_SRC 26
#define CAM_CC_CRE_AHB_CLK 27
#define CAM_CC_CRE_CLK 28
#define CAM_CC_CRE_CLK_SRC 29
#define CAM_CC_CSI0PHYTIMER_CLK 30
#define CAM_CC_CSI0PHYTIMER_CLK_SRC 31
#define CAM_CC_CSI1PHYTIMER_CLK 32
#define CAM_CC_CSI1PHYTIMER_CLK_SRC 33
#define CAM_CC_CSI2PHYTIMER_CLK 34
#define CAM_CC_CSI2PHYTIMER_CLK_SRC 35
#define CAM_CC_CSI3PHYTIMER_CLK 36
#define CAM_CC_CSI3PHYTIMER_CLK_SRC 37
#define CAM_CC_CSIPHY0_CLK 38
#define CAM_CC_CSIPHY1_CLK 39
#define CAM_CC_CSIPHY2_CLK 40
#define CAM_CC_CSIPHY3_CLK 41
#define CAM_CC_FAST_AHB_CLK_SRC 42
#define CAM_CC_ICP_ATB_CLK 43
#define CAM_CC_ICP_CLK 44
#define CAM_CC_ICP_CLK_SRC 45
#define CAM_CC_ICP_CTI_CLK 46
#define CAM_CC_ICP_TS_CLK 47
#define CAM_CC_MCLK0_CLK 48
#define CAM_CC_MCLK0_CLK_SRC 49
#define CAM_CC_MCLK1_CLK 50
#define CAM_CC_MCLK1_CLK_SRC 51
#define CAM_CC_MCLK2_CLK 52
#define CAM_CC_MCLK2_CLK_SRC 53
#define CAM_CC_MCLK3_CLK 54
#define CAM_CC_MCLK3_CLK_SRC 55
#define CAM_CC_MCLK4_CLK 56
#define CAM_CC_MCLK4_CLK_SRC 57
#define CAM_CC_OPE_0_AHB_CLK 58
#define CAM_CC_OPE_0_AREG_CLK 59
#define CAM_CC_OPE_0_CLK 60
#define CAM_CC_OPE_0_CLK_SRC 61
#define CAM_CC_SLOW_AHB_CLK_SRC 62
#define CAM_CC_SOC_AHB_CLK 63
#define CAM_CC_SYS_TMR_CLK 64
#define CAM_CC_TFE_0_AHB_CLK 65
#define CAM_CC_TFE_0_CLK 66
#define CAM_CC_TFE_0_CLK_SRC 67
#define CAM_CC_TFE_0_CPHY_RX_CLK 68
#define CAM_CC_TFE_0_CSID_CLK 69
#define CAM_CC_TFE_0_CSID_CLK_SRC 70
#define CAM_CC_TFE_1_AHB_CLK 71
#define CAM_CC_TFE_1_CLK 72
#define CAM_CC_TFE_1_CLK_SRC 73
#define CAM_CC_TFE_1_CPHY_RX_CLK 74
#define CAM_CC_TFE_1_CSID_CLK 75
#define CAM_CC_TFE_1_CSID_CLK_SRC 76
#define CAM_CC_TFE_2_AHB_CLK 77
#define CAM_CC_TFE_2_CLK 78
#define CAM_CC_TFE_2_CLK_SRC 79
#define CAM_CC_TFE_2_CPHY_RX_CLK 80
#define CAM_CC_TFE_2_CSID_CLK 81
#define CAM_CC_TFE_2_CSID_CLK_SRC 82
/* CAM_CC resets */
#define CAM_CC_BPS_BCR 0
#define CAM_CC_CAMNOC_BCR 1
#define CAM_CC_CAMSS_TOP_BCR 2
#define CAM_CC_CCI_0_BCR 3
#define CAM_CC_CCI_1_BCR 4
#define CAM_CC_CPAS_BCR 5
#define CAM_CC_CRE_BCR 6
#define CAM_CC_CSI0PHY_BCR 7
#define CAM_CC_CSI1PHY_BCR 8
#define CAM_CC_CSI2PHY_BCR 9
#define CAM_CC_CSI3PHY_BCR 10
#define CAM_CC_ICP_BCR 11
#define CAM_CC_MCLK0_BCR 12
#define CAM_CC_MCLK1_BCR 13
#define CAM_CC_MCLK2_BCR 14
#define CAM_CC_MCLK3_BCR 15
#define CAM_CC_MCLK4_BCR 16
#define CAM_CC_OPE_0_BCR 17
#define CAM_CC_TFE_0_BCR 18
#define CAM_CC_TFE_1_BCR 19
#define CAM_CC_TFE_2_BCR 20
#endif

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include/dt-bindings/clock/qcom,camcc-pineapple.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_PINEAPPLE_H
#define _DT_BINDINGS_CLK_QCOM_CAM_CC_PINEAPPLE_H
/* CAM_CC clocks */
#define CAM_CC_BPS_AHB_CLK 0
#define CAM_CC_BPS_CLK 1
#define CAM_CC_BPS_CLK_SRC 2
#define CAM_CC_BPS_FAST_AHB_CLK 3
#define CAM_CC_BPS_SHIFT_CLK 4
#define CAM_CC_CAMNOC_AXI_NRT_CLK 5
#define CAM_CC_CAMNOC_AXI_RT_CLK 6
#define CAM_CC_CAMNOC_AXI_RT_CLK_SRC 7
#define CAM_CC_CAMNOC_DCD_XO_CLK 8
#define CAM_CC_CAMNOC_XO_CLK 9
#define CAM_CC_CCI_0_CLK 10
#define CAM_CC_CCI_0_CLK_SRC 11
#define CAM_CC_CCI_1_CLK 12
#define CAM_CC_CCI_1_CLK_SRC 13
#define CAM_CC_CCI_2_CLK 14
#define CAM_CC_CCI_2_CLK_SRC 15
#define CAM_CC_CORE_AHB_CLK 16
#define CAM_CC_CPAS_AHB_CLK 17
#define CAM_CC_CPAS_BPS_CLK 18
#define CAM_CC_CPAS_CRE_CLK 19
#define CAM_CC_CPAS_FAST_AHB_CLK 20
#define CAM_CC_CPAS_IFE_0_CLK 21
#define CAM_CC_CPAS_IFE_1_CLK 22
#define CAM_CC_CPAS_IFE_2_CLK 23
#define CAM_CC_CPAS_IFE_LITE_CLK 24
#define CAM_CC_CPAS_IPE_NPS_CLK 25
#define CAM_CC_CPAS_SBI_CLK 26
#define CAM_CC_CPAS_SFE_0_CLK 27
#define CAM_CC_CPAS_SFE_1_CLK 28
#define CAM_CC_CPAS_SFE_2_CLK 29
#define CAM_CC_CPHY_RX_CLK_SRC 30
#define CAM_CC_CRE_AHB_CLK 31
#define CAM_CC_CRE_CLK 32
#define CAM_CC_CRE_CLK_SRC 33
#define CAM_CC_CSI0PHYTIMER_CLK 34
#define CAM_CC_CSI0PHYTIMER_CLK_SRC 35
#define CAM_CC_CSI1PHYTIMER_CLK 36
#define CAM_CC_CSI1PHYTIMER_CLK_SRC 37
#define CAM_CC_CSI2PHYTIMER_CLK 38
#define CAM_CC_CSI2PHYTIMER_CLK_SRC 39
#define CAM_CC_CSI3PHYTIMER_CLK 40
#define CAM_CC_CSI3PHYTIMER_CLK_SRC 41
#define CAM_CC_CSI4PHYTIMER_CLK 42
#define CAM_CC_CSI4PHYTIMER_CLK_SRC 43
#define CAM_CC_CSI5PHYTIMER_CLK 44
#define CAM_CC_CSI5PHYTIMER_CLK_SRC 45
#define CAM_CC_CSI6PHYTIMER_CLK 46
#define CAM_CC_CSI6PHYTIMER_CLK_SRC 47
#define CAM_CC_CSI7PHYTIMER_CLK 48
#define CAM_CC_CSI7PHYTIMER_CLK_SRC 49
#define CAM_CC_CSID_CLK 50
#define CAM_CC_CSID_CLK_SRC 51
#define CAM_CC_CSID_CSIPHY_RX_CLK 52
#define CAM_CC_CSIPHY0_CLK 53
#define CAM_CC_CSIPHY1_CLK 54
#define CAM_CC_CSIPHY2_CLK 55
#define CAM_CC_CSIPHY3_CLK 56
#define CAM_CC_CSIPHY4_CLK 57
#define CAM_CC_CSIPHY5_CLK 58
#define CAM_CC_CSIPHY6_CLK 59
#define CAM_CC_CSIPHY7_CLK 60
#define CAM_CC_DRV_AHB_CLK 61
#define CAM_CC_DRV_XO_CLK 62
#define CAM_CC_FAST_AHB_CLK_SRC 63
#define CAM_CC_GDSC_CLK 64
#define CAM_CC_ICP_AHB_CLK 65
#define CAM_CC_ICP_CLK 66
#define CAM_CC_ICP_CLK_SRC 67
#define CAM_CC_IFE_0_CLK 68
#define CAM_CC_IFE_0_CLK_SRC 69
#define CAM_CC_IFE_0_FAST_AHB_CLK 70
#define CAM_CC_IFE_0_SHIFT_CLK 71
#define CAM_CC_IFE_1_CLK 72
#define CAM_CC_IFE_1_CLK_SRC 73
#define CAM_CC_IFE_1_FAST_AHB_CLK 74
#define CAM_CC_IFE_1_SHIFT_CLK 75
#define CAM_CC_IFE_2_CLK 76
#define CAM_CC_IFE_2_CLK_SRC 77
#define CAM_CC_IFE_2_FAST_AHB_CLK 78
#define CAM_CC_IFE_2_SHIFT_CLK 79
#define CAM_CC_IFE_LITE_AHB_CLK 80
#define CAM_CC_IFE_LITE_CLK 81
#define CAM_CC_IFE_LITE_CLK_SRC 82
#define CAM_CC_IFE_LITE_CPHY_RX_CLK 83
#define CAM_CC_IFE_LITE_CSID_CLK 84
#define CAM_CC_IFE_LITE_CSID_CLK_SRC 85
#define CAM_CC_IPE_NPS_AHB_CLK 86
#define CAM_CC_IPE_NPS_CLK 87
#define CAM_CC_IPE_NPS_CLK_SRC 88
#define CAM_CC_IPE_NPS_FAST_AHB_CLK 89
#define CAM_CC_IPE_PPS_CLK 90
#define CAM_CC_IPE_PPS_FAST_AHB_CLK 91
#define CAM_CC_IPE_SHIFT_CLK 92
#define CAM_CC_JPEG_1_CLK 93
#define CAM_CC_JPEG_CLK 94
#define CAM_CC_JPEG_CLK_SRC 95
#define CAM_CC_MCLK0_CLK 96
#define CAM_CC_MCLK0_CLK_SRC 97
#define CAM_CC_MCLK1_CLK 98
#define CAM_CC_MCLK1_CLK_SRC 99
#define CAM_CC_MCLK2_CLK 100
#define CAM_CC_MCLK2_CLK_SRC 101
#define CAM_CC_MCLK3_CLK 102
#define CAM_CC_MCLK3_CLK_SRC 103
#define CAM_CC_MCLK4_CLK 104
#define CAM_CC_MCLK4_CLK_SRC 105
#define CAM_CC_MCLK5_CLK 106
#define CAM_CC_MCLK5_CLK_SRC 107
#define CAM_CC_MCLK6_CLK 108
#define CAM_CC_MCLK6_CLK_SRC 109
#define CAM_CC_MCLK7_CLK 110
#define CAM_CC_MCLK7_CLK_SRC 111
#define CAM_CC_PLL0 112
#define CAM_CC_PLL0_OUT_EVEN 113
#define CAM_CC_PLL0_OUT_ODD 114
#define CAM_CC_PLL1 115
#define CAM_CC_PLL10 116
#define CAM_CC_PLL10_OUT_EVEN 117
#define CAM_CC_PLL1_OUT_EVEN 118
#define CAM_CC_PLL2 119
#define CAM_CC_PLL3 120
#define CAM_CC_PLL3_OUT_EVEN 121
#define CAM_CC_PLL4 122
#define CAM_CC_PLL4_OUT_EVEN 123
#define CAM_CC_PLL5 124
#define CAM_CC_PLL5_OUT_EVEN 125
#define CAM_CC_PLL6 126
#define CAM_CC_PLL6_OUT_EVEN 127
#define CAM_CC_PLL7 128
#define CAM_CC_PLL7_OUT_EVEN 129
#define CAM_CC_PLL8 130
#define CAM_CC_PLL8_OUT_EVEN 131
#define CAM_CC_PLL9 132
#define CAM_CC_PLL9_OUT_EVEN 133
#define CAM_CC_PLL9_OUT_ODD 134
#define CAM_CC_QDSS_DEBUG_CLK 135
#define CAM_CC_QDSS_DEBUG_CLK_SRC 136
#define CAM_CC_QDSS_DEBUG_XO_CLK 137
#define CAM_CC_SBI_CLK 138
#define CAM_CC_SBI_FAST_AHB_CLK 139
#define CAM_CC_SBI_SHIFT_CLK 140
#define CAM_CC_SFE_0_CLK 141
#define CAM_CC_SFE_0_CLK_SRC 142
#define CAM_CC_SFE_0_FAST_AHB_CLK 143
#define CAM_CC_SFE_0_SHIFT_CLK 144
#define CAM_CC_SFE_1_CLK 145
#define CAM_CC_SFE_1_CLK_SRC 146
#define CAM_CC_SFE_1_FAST_AHB_CLK 147
#define CAM_CC_SFE_1_SHIFT_CLK 148
#define CAM_CC_SFE_2_CLK 149
#define CAM_CC_SFE_2_CLK_SRC 150
#define CAM_CC_SFE_2_FAST_AHB_CLK 151
#define CAM_CC_SFE_2_SHIFT_CLK 152
#define CAM_CC_SLEEP_CLK 153
#define CAM_CC_SLEEP_CLK_SRC 154
#define CAM_CC_SLOW_AHB_CLK_SRC 155
#define CAM_CC_TITAN_TOP_SHIFT_CLK 156
#define CAM_CC_XO_CLK_SRC 157
/* CAM_CC resets */
#define CAM_CC_BPS_BCR 0
#define CAM_CC_DRV_BCR 1
#define CAM_CC_ICP_BCR 2
#define CAM_CC_IFE_0_BCR 3
#define CAM_CC_IFE_1_BCR 4
#define CAM_CC_IFE_2_BCR 5
#define CAM_CC_IPE_0_BCR 6
#define CAM_CC_QDSS_DEBUG_BCR 7
#define CAM_CC_SBI_BCR 8
#define CAM_CC_SFE_0_BCR 9
#define CAM_CC_SFE_1_BCR 10
#define CAM_CC_SFE_2_BCR 11
#endif

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include/dt-bindings/clock/qcom,camcc-sun.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SUN_H
#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SUN_H
/* CAM_CC clocks */
#define CAM_CC_CAM_TOP_AHB_CLK 0
#define CAM_CC_CAM_TOP_FAST_AHB_CLK 1
#define CAM_CC_CAMNOC_DCD_XO_CLK 2
#define CAM_CC_CAMNOC_NRT_AXI_CLK 3
#define CAM_CC_CAMNOC_NRT_CRE_CLK 4
#define CAM_CC_CAMNOC_NRT_IPE_NPS_CLK 5
#define CAM_CC_CAMNOC_NRT_OFE_ANCHOR_CLK 6
#define CAM_CC_CAMNOC_NRT_OFE_HDR_CLK 7
#define CAM_CC_CAMNOC_NRT_OFE_MAIN_CLK 8
#define CAM_CC_CAMNOC_RT_AXI_CLK 9
#define CAM_CC_CAMNOC_RT_AXI_CLK_SRC 10
#define CAM_CC_CAMNOC_RT_IFE_LITE_CLK 11
#define CAM_CC_CAMNOC_RT_TFE_0_BAYER_CLK 12
#define CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK 13
#define CAM_CC_CAMNOC_RT_TFE_1_BAYER_CLK 14
#define CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK 15
#define CAM_CC_CAMNOC_RT_TFE_2_BAYER_CLK 16
#define CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK 17
#define CAM_CC_CAMNOC_XO_CLK 18
#define CAM_CC_CCI_0_CLK 19
#define CAM_CC_CCI_0_CLK_SRC 20
#define CAM_CC_CCI_1_CLK 21
#define CAM_CC_CCI_1_CLK_SRC 22
#define CAM_CC_CCI_2_CLK 23
#define CAM_CC_CCI_2_CLK_SRC 24
#define CAM_CC_CORE_AHB_CLK 25
#define CAM_CC_CPHY_RX_CLK_SRC 26
#define CAM_CC_CRE_AHB_CLK 27
#define CAM_CC_CRE_CLK 28
#define CAM_CC_CRE_CLK_SRC 29
#define CAM_CC_CSI0PHYTIMER_CLK 30
#define CAM_CC_CSI0PHYTIMER_CLK_SRC 31
#define CAM_CC_CSI1PHYTIMER_CLK 32
#define CAM_CC_CSI1PHYTIMER_CLK_SRC 33
#define CAM_CC_CSI2PHYTIMER_CLK 34
#define CAM_CC_CSI2PHYTIMER_CLK_SRC 35
#define CAM_CC_CSI3PHYTIMER_CLK 36
#define CAM_CC_CSI3PHYTIMER_CLK_SRC 37
#define CAM_CC_CSI4PHYTIMER_CLK 38
#define CAM_CC_CSI4PHYTIMER_CLK_SRC 39
#define CAM_CC_CSI5PHYTIMER_CLK 40
#define CAM_CC_CSI5PHYTIMER_CLK_SRC 41
#define CAM_CC_CSID_CLK 42
#define CAM_CC_CSID_CLK_SRC 43
#define CAM_CC_CSID_CSIPHY_RX_CLK 44
#define CAM_CC_CSIPHY0_CLK 45
#define CAM_CC_CSIPHY1_CLK 46
#define CAM_CC_CSIPHY2_CLK 47
#define CAM_CC_CSIPHY3_CLK 48
#define CAM_CC_CSIPHY4_CLK 49
#define CAM_CC_CSIPHY5_CLK 50
#define CAM_CC_DRV_AHB_CLK 51
#define CAM_CC_DRV_XO_CLK 52
#define CAM_CC_FAST_AHB_CLK_SRC 53
#define CAM_CC_GDSC_CLK 54
#define CAM_CC_ICP_0_AHB_CLK 55
#define CAM_CC_ICP_0_CLK 56
#define CAM_CC_ICP_0_CLK_SRC 57
#define CAM_CC_ICP_1_AHB_CLK 58
#define CAM_CC_ICP_1_CLK 59
#define CAM_CC_ICP_1_CLK_SRC 60
#define CAM_CC_IFE_LITE_AHB_CLK 61
#define CAM_CC_IFE_LITE_CLK 62
#define CAM_CC_IFE_LITE_CLK_SRC 63
#define CAM_CC_IFE_LITE_CPHY_RX_CLK 64
#define CAM_CC_IFE_LITE_CSID_CLK 65
#define CAM_CC_IFE_LITE_CSID_CLK_SRC 66
#define CAM_CC_IPE_NPS_AHB_CLK 67
#define CAM_CC_IPE_NPS_CLK 68
#define CAM_CC_IPE_NPS_CLK_SRC 69
#define CAM_CC_IPE_NPS_FAST_AHB_CLK 70
#define CAM_CC_IPE_PPS_CLK 71
#define CAM_CC_IPE_PPS_FAST_AHB_CLK 72
#define CAM_CC_JPEG_0_CLK 73
#define CAM_CC_JPEG_1_CLK 74
#define CAM_CC_JPEG_CLK_SRC 75
#define CAM_CC_OFE_AHB_CLK 76
#define CAM_CC_OFE_ANCHOR_CLK 77
#define CAM_CC_OFE_ANCHOR_FAST_AHB_CLK 78
#define CAM_CC_OFE_CLK_SRC 79
#define CAM_CC_OFE_HDR_CLK 80
#define CAM_CC_OFE_HDR_FAST_AHB_CLK 81
#define CAM_CC_OFE_MAIN_CLK 82
#define CAM_CC_OFE_MAIN_FAST_AHB_CLK 83
#define CAM_CC_PLL0 84
#define CAM_CC_PLL0_OUT_EVEN 85
#define CAM_CC_PLL0_OUT_ODD 86
#define CAM_CC_PLL1 87
#define CAM_CC_PLL1_OUT_EVEN 88
#define CAM_CC_PLL2 89
#define CAM_CC_PLL2_OUT_EVEN 90
#define CAM_CC_PLL3 91
#define CAM_CC_PLL3_OUT_EVEN 92
#define CAM_CC_PLL4 93
#define CAM_CC_PLL4_OUT_EVEN 94
#define CAM_CC_PLL5 95
#define CAM_CC_PLL5_OUT_EVEN 96
#define CAM_CC_PLL6 97
#define CAM_CC_PLL6_OUT_EVEN 98
#define CAM_CC_PLL6_OUT_ODD 99
#define CAM_CC_QDSS_DEBUG_CLK 100
#define CAM_CC_QDSS_DEBUG_CLK_SRC 101
#define CAM_CC_QDSS_DEBUG_XO_CLK 102
#define CAM_CC_SLEEP_CLK 103
#define CAM_CC_SLEEP_CLK_SRC 104
#define CAM_CC_SLOW_AHB_CLK_SRC 105
#define CAM_CC_TFE_0_BAYER_CLK 106
#define CAM_CC_TFE_0_BAYER_FAST_AHB_CLK 107
#define CAM_CC_TFE_0_CLK_SRC 108
#define CAM_CC_TFE_0_MAIN_CLK 109
#define CAM_CC_TFE_0_MAIN_FAST_AHB_CLK 110
#define CAM_CC_TFE_1_BAYER_CLK 111
#define CAM_CC_TFE_1_BAYER_FAST_AHB_CLK 112
#define CAM_CC_TFE_1_CLK_SRC 113
#define CAM_CC_TFE_1_MAIN_CLK 114
#define CAM_CC_TFE_1_MAIN_FAST_AHB_CLK 115
#define CAM_CC_TFE_2_BAYER_CLK 116
#define CAM_CC_TFE_2_BAYER_FAST_AHB_CLK 117
#define CAM_CC_TFE_2_CLK_SRC 118
#define CAM_CC_TFE_2_MAIN_CLK 119
#define CAM_CC_TFE_2_MAIN_FAST_AHB_CLK 120
#define CAM_CC_XO_CLK_SRC 121
/* CAM_CC power domains */
#define CAM_CC_IPE_0_GDSC 0
#define CAM_CC_OFE_GDSC 1
#define CAM_CC_TFE_0_GDSC 2
#define CAM_CC_TFE_1_GDSC 3
#define CAM_CC_TFE_2_GDSC 4
#define CAM_CC_TITAN_TOP_GDSC 5
/* CAM_CC resets */
#define CAM_CC_DRV_BCR 0
#define CAM_CC_ICP_BCR 1
#define CAM_CC_IPE_0_BCR 2
#define CAM_CC_OFE_BCR 3
#define CAM_CC_QDSS_DEBUG_BCR 4
#define CAM_CC_TFE_0_BCR 5
#define CAM_CC_TFE_1_BCR 6
#define CAM_CC_TFE_2_BCR 7
#endif

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include/dt-bindings/clock/qcom,dispcc-monaco.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_MONACO_H
#define _DT_BINDINGS_CLK_QCOM_DISP_CC_MONACO_H
/* DISP_CC clocks */
#define DISP_CC_MDSS_AHB_CLK 0
#define DISP_CC_MDSS_AHB_CLK_SRC 1
#define DISP_CC_MDSS_BYTE0_CLK 2
#define DISP_CC_MDSS_BYTE0_CLK_SRC 3
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 4
#define DISP_CC_MDSS_BYTE0_INTF_CLK 5
#define DISP_CC_MDSS_ESC0_CLK 6
#define DISP_CC_MDSS_ESC0_CLK_SRC 7
#define DISP_CC_MDSS_MDP_CLK 8
#define DISP_CC_MDSS_MDP_CLK_SRC 9
#define DISP_CC_MDSS_MDP_LUT_CLK 10
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 11
#define DISP_CC_MDSS_PCLK0_CLK 12
#define DISP_CC_MDSS_PCLK0_CLK_SRC 13
#define DISP_CC_MDSS_VSYNC_CLK 14
#define DISP_CC_MDSS_VSYNC_CLK_SRC 15
#define DISP_CC_SLEEP_CLK 16
#define DISP_CC_SLEEP_CLK_SRC 17
#define DISP_CC_XO_CLK 18
#define DISP_CC_XO_CLK_SRC 19
#endif

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include/dt-bindings/clock/qcom,dispcc-parrot.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2021, 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_PARROT_H
#define _DT_BINDINGS_CLK_QCOM_DISP_CC_PARROT_H
/* DISP_CC clocks */
#define DISP_CC_PLL0 0
#define DISP_CC_PLL1 1
#define DISP_CC_MDSS_AHB1_CLK 2
#define DISP_CC_MDSS_AHB_CLK 3
#define DISP_CC_MDSS_AHB_CLK_SRC 4
#define DISP_CC_MDSS_BYTE0_CLK 5
#define DISP_CC_MDSS_BYTE0_CLK_SRC 6
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 7
#define DISP_CC_MDSS_BYTE0_INTF_CLK 8
#define DISP_CC_MDSS_DPTX0_AUX_CLK 9
#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 10
#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK 11
#define DISP_CC_MDSS_DPTX0_LINK_CLK 12
#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 13
#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 14
#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 15
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 16
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 17
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 18
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 19
#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 20
#define DISP_CC_MDSS_DPTX1_AUX_CLK 21
#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 22
#define DISP_CC_MDSS_DPTX1_CRYPTO_CLK 23
#define DISP_CC_MDSS_DPTX1_LINK_CLK 24
#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 25
#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 26
#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 27
#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 28
#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 29
#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 30
#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 31
#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 32
#define DISP_CC_MDSS_DPTX2_AUX_CLK 33
#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 34
#define DISP_CC_MDSS_DPTX2_CRYPTO_CLK 35
#define DISP_CC_MDSS_DPTX2_LINK_CLK 36
#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 37
#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 38
#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 39
#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 40
#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 41
#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 42
#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 43
#define DISP_CC_MDSS_DPTX3_AUX_CLK 44
#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 45
#define DISP_CC_MDSS_DPTX3_CRYPTO_CLK 46
#define DISP_CC_MDSS_DPTX3_LINK_CLK 47
#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 48
#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 49
#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 50
#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 51
#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 52
#define DISP_CC_MDSS_ESC0_CLK 53
#define DISP_CC_MDSS_ESC0_CLK_SRC 54
#define DISP_CC_MDSS_MDP1_CLK 55
#define DISP_CC_MDSS_MDP_CLK 56
#define DISP_CC_MDSS_MDP_CLK_SRC 57
#define DISP_CC_MDSS_MDP_LUT1_CLK 58
#define DISP_CC_MDSS_MDP_LUT_CLK 59
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 60
#define DISP_CC_MDSS_PCLK0_CLK 61
#define DISP_CC_MDSS_PCLK0_CLK_SRC 62
#define DISP_CC_MDSS_ROT1_CLK 63
#define DISP_CC_MDSS_ROT_CLK 64
#define DISP_CC_MDSS_ROT_CLK_SRC 65
#define DISP_CC_MDSS_RSCC_AHB_CLK 66
#define DISP_CC_MDSS_RSCC_VSYNC_CLK 67
#define DISP_CC_MDSS_VSYNC1_CLK 68
#define DISP_CC_MDSS_VSYNC_CLK 69
#define DISP_CC_MDSS_VSYNC_CLK_SRC 70
#define DISP_CC_SLEEP_CLK 71
#define DISP_CC_SLEEP_CLK_SRC 72
#define DISP_CC_XO_CLK 73
#define DISP_CC_XO_CLK_SRC 74
/* DISP_CC resets */
#define DISP_CC_MDSS_CORE_BCR 0
#define DISP_CC_MDSS_CORE_INT2_BCR 1
#define DISP_CC_MDSS_RSCC_BCR 2
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_PINEAPPLE_H
#define _DT_BINDINGS_CLK_QCOM_DISP_CC_PINEAPPLE_H
/* DISP_CC clocks */
#define DISP_CC_MDSS_ACCU_CLK 0
#define DISP_CC_MDSS_AHB1_CLK 1
#define DISP_CC_MDSS_AHB_CLK 2
#define DISP_CC_MDSS_AHB_CLK_SRC 3
#define DISP_CC_MDSS_BYTE0_CLK 4
#define DISP_CC_MDSS_BYTE0_CLK_SRC 5
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 6
#define DISP_CC_MDSS_BYTE0_INTF_CLK 7
#define DISP_CC_MDSS_BYTE1_CLK 8
#define DISP_CC_MDSS_BYTE1_CLK_SRC 9
#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 10
#define DISP_CC_MDSS_BYTE1_INTF_CLK 11
#define DISP_CC_MDSS_DPTX0_AUX_CLK 12
#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 13
#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK 14
#define DISP_CC_MDSS_DPTX0_LINK_CLK 15
#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 16
#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 17
#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 18
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 19
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 20
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 21
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 22
#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 23
#define DISP_CC_MDSS_DPTX1_AUX_CLK 24
#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 25
#define DISP_CC_MDSS_DPTX1_CRYPTO_CLK 26
#define DISP_CC_MDSS_DPTX1_LINK_CLK 27
#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 28
#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 29
#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 30
#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 31
#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 32
#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 33
#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 34
#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 35
#define DISP_CC_MDSS_DPTX2_AUX_CLK 36
#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 37
#define DISP_CC_MDSS_DPTX2_CRYPTO_CLK 38
#define DISP_CC_MDSS_DPTX2_LINK_CLK 39
#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 40
#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 41
#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 42
#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 43
#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 44
#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 45
#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 46
#define DISP_CC_MDSS_DPTX3_AUX_CLK 47
#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 48
#define DISP_CC_MDSS_DPTX3_CRYPTO_CLK 49
#define DISP_CC_MDSS_DPTX3_LINK_CLK 50
#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 51
#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 52
#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 53
#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 54
#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 55
#define DISP_CC_MDSS_ESC0_CLK 56
#define DISP_CC_MDSS_ESC0_CLK_SRC 57
#define DISP_CC_MDSS_ESC1_CLK 58
#define DISP_CC_MDSS_ESC1_CLK_SRC 59
#define DISP_CC_MDSS_MDP1_CLK 60
#define DISP_CC_MDSS_MDP_CLK 61
#define DISP_CC_MDSS_MDP_CLK_SRC 62
#define DISP_CC_MDSS_MDP_LUT1_CLK 63
#define DISP_CC_MDSS_MDP_LUT_CLK 64
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 65
#define DISP_CC_MDSS_PCLK0_CLK 66
#define DISP_CC_MDSS_PCLK0_CLK_SRC 67
#define DISP_CC_MDSS_PCLK1_CLK 68
#define DISP_CC_MDSS_PCLK1_CLK_SRC 69
#define DISP_CC_MDSS_RSCC_AHB_CLK 70
#define DISP_CC_MDSS_RSCC_VSYNC_CLK 71
#define DISP_CC_MDSS_VSYNC1_CLK 72
#define DISP_CC_MDSS_VSYNC_CLK 73
#define DISP_CC_MDSS_VSYNC_CLK_SRC 74
#define DISP_CC_PLL0 75
#define DISP_CC_PLL1 76
#define DISP_CC_SLEEP_CLK 77
#define DISP_CC_SLEEP_CLK_SRC 78
#define DISP_CC_XO_CLK 79
#define DISP_CC_XO_CLK_SRC 80
/* DISP_CC resets */
#define DISP_CC_MDSS_CORE_BCR 0
#define DISP_CC_MDSS_CORE_INT2_BCR 1
#define DISP_CC_MDSS_RSCC_BCR 2
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SUN_H
#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SUN_H
/* DISP_CC clocks */
#define DISP_CC_ESYNC0_CLK 0
#define DISP_CC_ESYNC0_CLK_SRC 1
#define DISP_CC_ESYNC1_CLK 2
#define DISP_CC_ESYNC1_CLK_SRC 3
#define DISP_CC_MDSS_ACCU_SHIFT_CLK 4
#define DISP_CC_MDSS_AHB1_CLK 5
#define DISP_CC_MDSS_AHB_CLK 6
#define DISP_CC_MDSS_AHB_CLK_SRC 7
#define DISP_CC_MDSS_BYTE0_CLK 8
#define DISP_CC_MDSS_BYTE0_CLK_SRC 9
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 10
#define DISP_CC_MDSS_BYTE0_INTF_CLK 11
#define DISP_CC_MDSS_BYTE1_CLK 12
#define DISP_CC_MDSS_BYTE1_CLK_SRC 13
#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 14
#define DISP_CC_MDSS_BYTE1_INTF_CLK 15
#define DISP_CC_MDSS_DPTX0_AUX_CLK 16
#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 17
#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK 18
#define DISP_CC_MDSS_DPTX0_LINK_CLK 19
#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 20
#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 21
#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 22
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 23
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 24
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 25
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 26
#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 27
#define DISP_CC_MDSS_DPTX1_AUX_CLK 28
#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 29
#define DISP_CC_MDSS_DPTX1_CRYPTO_CLK 30
#define DISP_CC_MDSS_DPTX1_LINK_CLK 31
#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 32
#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 33
#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 34
#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 35
#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 36
#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 37
#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 38
#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 39
#define DISP_CC_MDSS_DPTX2_AUX_CLK 40
#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 41
#define DISP_CC_MDSS_DPTX2_CRYPTO_CLK 42
#define DISP_CC_MDSS_DPTX2_LINK_CLK 43
#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 44
#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 45
#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 46
#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 47
#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 48
#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 49
#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 50
#define DISP_CC_MDSS_DPTX3_AUX_CLK 51
#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 52
#define DISP_CC_MDSS_DPTX3_CRYPTO_CLK 53
#define DISP_CC_MDSS_DPTX3_LINK_CLK 54
#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 55
#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 56
#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 57
#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 58
#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 59
#define DISP_CC_MDSS_ESC0_CLK 60
#define DISP_CC_MDSS_ESC0_CLK_SRC 61
#define DISP_CC_MDSS_ESC1_CLK 62
#define DISP_CC_MDSS_ESC1_CLK_SRC 63
#define DISP_CC_MDSS_MDP1_CLK 64
#define DISP_CC_MDSS_MDP_CLK 65
#define DISP_CC_MDSS_MDP_CLK_SRC 66
#define DISP_CC_MDSS_MDP_LUT1_CLK 67
#define DISP_CC_MDSS_MDP_LUT_CLK 68
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 69
#define DISP_CC_MDSS_PCLK0_CLK 70
#define DISP_CC_MDSS_PCLK0_CLK_SRC 71
#define DISP_CC_MDSS_PCLK1_CLK 72
#define DISP_CC_MDSS_PCLK1_CLK_SRC 73
#define DISP_CC_MDSS_PCLK2_CLK 74
#define DISP_CC_MDSS_PCLK2_CLK_SRC 75
#define DISP_CC_MDSS_RSCC_AHB_CLK 76
#define DISP_CC_MDSS_RSCC_VSYNC_CLK 77
#define DISP_CC_MDSS_VSYNC1_CLK 78
#define DISP_CC_MDSS_VSYNC_CLK 79
#define DISP_CC_MDSS_VSYNC_CLK_SRC 80
#define DISP_CC_PLL0 83
#define DISP_CC_PLL1 84
#define DISP_CC_SLEEP_CLK 86
#define DISP_CC_SLEEP_CLK_SRC 87
#define DISP_CC_XO_CLK 88
#define DISP_CC_XO_CLK_SRC 89
/* DISP_CC MX clocks */
#define DISP_CC_OSC_CLK 0
#define DISP_CC_OSC_CLK_SRC 1
#define DISP_CC_PLL2 2
/* DISP_CC power domains */
#define DISP_CC_MDSS_CORE_GDSC 0
#define DISP_CC_MDSS_CORE_INT2_GDSC 1
/* DISP_CC resets */
#define DISP_CC_MDSS_CORE_BCR 0
#define DISP_CC_MDSS_CORE_INT2_BCR 1
#define DISP_CC_MDSS_RSCC_BCR 2
#endif

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_TUNA_H
#define _DT_BINDINGS_CLK_QCOM_DISP_CC_TUNA_H
/* DISP_CC clocks */
#define DISP_CC_PLL0 0
#define DISP_CC_PLL1 1
#define DISP_CC_PLL2 2
#define DISP_CC_ESYNC0_CLK 3
#define DISP_CC_ESYNC0_CLK_SRC 4
#define DISP_CC_ESYNC1_CLK 5
#define DISP_CC_ESYNC1_CLK_SRC 6
#define DISP_CC_MDSS_ACCU_SHIFT_CLK 7
#define DISP_CC_MDSS_AHB1_CLK 8
#define DISP_CC_MDSS_AHB_CLK 9
#define DISP_CC_MDSS_AHB_CLK_SRC 10
#define DISP_CC_MDSS_BYTE0_CLK 11
#define DISP_CC_MDSS_BYTE0_CLK_SRC 12
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 13
#define DISP_CC_MDSS_BYTE0_INTF_CLK 14
#define DISP_CC_MDSS_BYTE1_CLK 15
#define DISP_CC_MDSS_BYTE1_CLK_SRC 16
#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 17
#define DISP_CC_MDSS_BYTE1_INTF_CLK 18
#define DISP_CC_MDSS_DPTX0_AUX_CLK 19
#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 20
#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK 21
#define DISP_CC_MDSS_DPTX0_LINK_CLK 22
#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 23
#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 24
#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 25
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 26
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 27
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 28
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 29
#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 30
#define DISP_CC_MDSS_DPTX1_AUX_CLK 31
#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 32
#define DISP_CC_MDSS_DPTX1_CRYPTO_CLK 33
#define DISP_CC_MDSS_DPTX1_LINK_CLK 34
#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 35
#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 36
#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 37
#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 38
#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 39
#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 40
#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 41
#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 42
#define DISP_CC_MDSS_DPTX2_AUX_CLK 43
#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 44
#define DISP_CC_MDSS_DPTX2_CRYPTO_CLK 45
#define DISP_CC_MDSS_DPTX2_LINK_CLK 46
#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 47
#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 48
#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 49
#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 50
#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 51
#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 52
#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 53
#define DISP_CC_MDSS_DPTX3_AUX_CLK 54
#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 55
#define DISP_CC_MDSS_DPTX3_CRYPTO_CLK 56
#define DISP_CC_MDSS_DPTX3_LINK_CLK 57
#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 58
#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 59
#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 60
#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 61
#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 62
#define DISP_CC_MDSS_ESC0_CLK 63
#define DISP_CC_MDSS_ESC0_CLK_SRC 64
#define DISP_CC_MDSS_ESC1_CLK 65
#define DISP_CC_MDSS_ESC1_CLK_SRC 66
#define DISP_CC_MDSS_HDMI_AHBM_CLK 67
#define DISP_CC_MDSS_HDMI_APP_CLK 68
#define DISP_CC_MDSS_HDMI_APP_CLK_SRC 69
#define DISP_CC_MDSS_HDMI_CRYPTO_CLK 70
#define DISP_CC_MDSS_HDMI_INTF_CLK 71
#define DISP_CC_MDSS_HDMI_PCLK_CLK 72
#define DISP_CC_MDSS_HDMI_PCLK_CLK_SRC 73
#define DISP_CC_MDSS_HDMI_PCLK_DIV_CLK_SRC 74
#define DISP_CC_MDSS_MDP1_CLK 75
#define DISP_CC_MDSS_MDP_CLK 76
#define DISP_CC_MDSS_MDP_CLK_SRC 77
#define DISP_CC_MDSS_MDP_LUT1_CLK 78
#define DISP_CC_MDSS_MDP_LUT_CLK 79
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 80
#define DISP_CC_MDSS_PCLK0_CLK 81
#define DISP_CC_MDSS_PCLK0_CLK_SRC 82
#define DISP_CC_MDSS_PCLK1_CLK 83
#define DISP_CC_MDSS_PCLK1_CLK_SRC 84
#define DISP_CC_MDSS_PCLK2_CLK 85
#define DISP_CC_MDSS_PCLK2_CLK_SRC 86
#define DISP_CC_MDSS_RSCC_AHB_CLK 87
#define DISP_CC_MDSS_RSCC_VSYNC_CLK 88
#define DISP_CC_MDSS_VSYNC1_CLK 89
#define DISP_CC_MDSS_VSYNC_CLK 90
#define DISP_CC_MDSS_VSYNC_CLK_SRC 91
#define DISP_CC_OSC_CLK 92
#define DISP_CC_OSC_CLK_SRC 93
#define DISP_CC_SLEEP_CLK 94
#define DISP_CC_SLEEP_CLK_SRC 95
#define DISP_CC_XO_CLK 96
#define DISP_CC_XO_CLK_SRC 97
/* DISP_CC power domains */
#define DISP_CC_MDSS_CORE_GDSC 0
#define DISP_CC_MDSS_CORE_INT2_GDSC 1
/* DISP_CC resets */
#define DISP_CC_MDSS_CORE_BCR 0
#define DISP_CC_MDSS_CORE_INT2_BCR 1
#define DISP_CC_MDSS_RSCC_BCR 2
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_EVA_CC_SUN_H
#define _DT_BINDINGS_CLK_QCOM_EVA_CC_SUN_H
/* EVA_CC clocks */
#define EVA_CC_AHB_CLK 0
#define EVA_CC_AHB_CLK_SRC 1
#define EVA_CC_MVS0_CLK 2
#define EVA_CC_MVS0_CLK_SRC 3
#define EVA_CC_MVS0_DIV_CLK_SRC 4
#define EVA_CC_MVS0_FREERUN_CLK 5
#define EVA_CC_MVS0_SHIFT_CLK 6
#define EVA_CC_MVS0C_CLK 7
#define EVA_CC_MVS0C_DIV2_DIV_CLK_SRC 8
#define EVA_CC_MVS0C_FREERUN_CLK 9
#define EVA_CC_MVS0C_SHIFT_CLK 10
#define EVA_CC_PLL0 11
#define EVA_CC_SLEEP_CLK 12
#define EVA_CC_SLEEP_CLK_SRC 13
#define EVA_CC_XO_CLK 14
#define EVA_CC_XO_CLK_SRC 15
/* EVA_CC power domains */
#define EVA_CC_MVS0_GDSC 0
#define EVA_CC_MVS0C_GDSC 1
/* EVA_CC resets */
#define EVA_CC_INTERFACE_BCR 0
#define EVA_CC_MVS0_BCR 1
#define EVA_CC_MVS0_FREERUN_CLK_ARES 2
#define EVA_CC_MVS0C_CLK_ARES 3
#define EVA_CC_MVS0C_BCR 4
#define EVA_CC_MVS0C_FREERUN_CLK_ARES 5
#define EVA_CVP_EVA_CC_INTERFACE_BCR EVA_CC_INTERFACE_BCR
#define EVA_CVP_EVA_CC_MVS0_BCR EVA_CC_MVS0_BCR
#define EVA_CVP_EVA_CC_MVS0C_BCR EVA_CC_MVS0C_BCR
#endif

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include/dt-bindings/clock/qcom,evacc-tuna.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_EVA_CC_TUNA_H
#define _DT_BINDINGS_CLK_QCOM_EVA_CC_TUNA_H
/* EVA_CC clocks */
#define EVA_CC_PLL0 0
#define EVA_CC_AHB_CLK 1
#define EVA_CC_AHB_CLK_SRC 2
#define EVA_CC_MVS0_CLK 3
#define EVA_CC_MVS0_CLK_SRC 4
#define EVA_CC_MVS0_DIV_CLK_SRC 5
#define EVA_CC_MVS0_FREERUN_CLK 6
#define EVA_CC_MVS0_SHIFT_CLK 7
#define EVA_CC_MVS0C_CLK 8
#define EVA_CC_MVS0C_DIV2_DIV_CLK_SRC 9
#define EVA_CC_MVS0C_FREERUN_CLK 10
#define EVA_CC_MVS0C_SHIFT_CLK 11
#define EVA_CC_SLEEP_CLK 12
#define EVA_CC_SLEEP_CLK_SRC 13
#define EVA_CC_XO_CLK 14
#define EVA_CC_XO_CLK_SRC 15
/* EVA_CC resets */
#define EVA_CC_INTERFACE_BCR 0
#define EVA_CC_MVS0_BCR 1
#define EVA_CC_MVS0C_BCR 2
#define EVA_CC_MVS0_FREERUN_CLK_ARES 3
#define EVA_CC_MVS0C_CLK_ARES 4
#define EVA_CC_MVS0C_FREERUN_CLK_ARES 5
#endif

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include/dt-bindings/clock/qcom,gcc-kera.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_KERA_H
#define _DT_BINDINGS_CLK_QCOM_GCC_KERA_H
/* GCC clocks */
#define GCC_GPLL0 0
#define GCC_GPLL0_OUT_EVEN 1
#define GCC_GPLL1 2
#define GCC_GPLL4 3
#define GCC_GPLL7 4
#define GCC_GPLL8 5
#define GCC_GPLL9 6
#define GCC_AGGRE_NOC_PCIE_AXI_CLK 7
#define GCC_AGGRE_UFS_PHY_AXI_CLK 8
#define GCC_AGGRE_USB3_PRIM_AXI_CLK 9
#define GCC_AHB2PHY_2_CLK 10
#define GCC_BOOT_ROM_AHB_CLK 11
#define GCC_CAM_BIST_MCLK_AHB_CLK 12
#define GCC_CAMERA_AHB_CLK 13
#define GCC_CAMERA_HF_AXI_CLK 14
#define GCC_CAMERA_SF_AXI_CLK 15
#define GCC_CAMERA_XO_CLK 16
#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 17
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 18
#define GCC_CM_PHY_REFGEN3_CLK 19
#define GCC_CNOC_PCIE_SF_AXI_CLK 20
#define GCC_DDRSS_GPU_AXI_CLK 21
#define GCC_DDRSS_PCIE_SF_QTB_CLK 22
#define GCC_DISP_AHB_CLK 23
#define GCC_DISP_HF_AXI_CLK 24
#define GCC_GP1_CLK 25
#define GCC_GP1_CLK_SRC 26
#define GCC_GP2_CLK 27
#define GCC_GP2_CLK_SRC 28
#define GCC_GP3_CLK 29
#define GCC_GP3_CLK_SRC 30
#define GCC_GPU_CFG_AHB_CLK 31
#define GCC_GPU_GEMNOC_GFX_CLK 32
#define GCC_GPU_GPLL0_CPH_CLK_SRC 33
#define GCC_GPU_GPLL0_DIV_CPH_CLK_SRC 34
#define GCC_PCIE_0_AUX_CLK 35
#define GCC_PCIE_0_AUX_CLK_SRC 36
#define GCC_PCIE_0_CFG_AHB_CLK 37
#define GCC_PCIE_0_MSTR_AXI_CLK 38
#define GCC_PCIE_0_PHY_RCHNG_CLK 39
#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 40
#define GCC_PCIE_0_PIPE_CLK 41
#define GCC_PCIE_0_PIPE_CLK_SRC 42
#define GCC_PCIE_0_PIPE_DIV2_CLK 43
#define GCC_PCIE_0_PIPE_DIV2_CLK_SRC 44
#define GCC_PCIE_0_SLV_AXI_CLK 45
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 46
#define GCC_PCIE_1_AUX_CLK 47
#define GCC_PCIE_1_AUX_CLK_SRC 48
#define GCC_PCIE_1_CFG_AHB_CLK 49
#define GCC_PCIE_1_MSTR_AXI_CLK 50
#define GCC_PCIE_1_PHY_RCHNG_CLK 51
#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 52
#define GCC_PCIE_1_PIPE_CLK 53
#define GCC_PCIE_1_PIPE_CLK_SRC 54
#define GCC_PCIE_1_PIPE_DIV2_CLK 55
#define GCC_PCIE_1_PIPE_DIV2_CLK_SRC 56
#define GCC_PCIE_1_SLV_AXI_CLK 57
#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 58
#define GCC_PCIE_RSCC_CFG_AHB_CLK 59
#define GCC_PCIE_RSCC_XO_CLK 60
#define GCC_PDM2_CLK 61
#define GCC_PDM2_CLK_SRC 62
#define GCC_PDM_AHB_CLK 63
#define GCC_PDM_XO4_CLK 64
#define GCC_QMIP_CAMERA_CMD_AHB_CLK 65
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 66
#define GCC_QMIP_CAMERA_RT_AHB_CLK 67
#define GCC_QMIP_GPU_AHB_CLK 68
#define GCC_QMIP_PCIE_AHB_CLK 69
#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 70
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 71
#define GCC_QUPV3_WRAP1_CORE_2X_CLK 72
#define GCC_QUPV3_WRAP1_CORE_CLK 73
#define GCC_QUPV3_WRAP1_QSPI_REF_CLK 74
#define GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC 75
#define GCC_QUPV3_WRAP1_S0_CLK 76
#define GCC_QUPV3_WRAP1_S0_CLK_SRC 77
#define GCC_QUPV3_WRAP1_S1_CLK 78
#define GCC_QUPV3_WRAP1_S1_CLK_SRC 79
#define GCC_QUPV3_WRAP1_S2_CLK 80
#define GCC_QUPV3_WRAP1_S2_CLK_SRC 81
#define GCC_QUPV3_WRAP1_S3_CLK 82
#define GCC_QUPV3_WRAP1_S3_CLK_SRC 83
#define GCC_QUPV3_WRAP1_S4_CLK 84
#define GCC_QUPV3_WRAP1_S4_CLK_SRC 85
#define GCC_QUPV3_WRAP1_S5_CLK 86
#define GCC_QUPV3_WRAP1_S5_CLK_SRC 87
#define GCC_QUPV3_WRAP1_S6_CLK 88
#define GCC_QUPV3_WRAP1_S6_CLK_SRC 89
#define GCC_QUPV3_WRAP1_S7_CLK 90
#define GCC_QUPV3_WRAP1_S7_CLK_SRC 91
#define GCC_QUPV3_WRAP2_CORE_2X_CLK 92
#define GCC_QUPV3_WRAP2_CORE_CLK 93
#define GCC_QUPV3_WRAP2_IBI_CTRL_0_CLK_SRC 94
#define GCC_QUPV3_WRAP2_IBI_CTRL_2_CLK 95
#define GCC_QUPV3_WRAP2_IBI_CTRL_3_CLK 96
#define GCC_QUPV3_WRAP2_S0_CLK 97
#define GCC_QUPV3_WRAP2_S0_CLK_SRC 98
#define GCC_QUPV3_WRAP2_S1_CLK 99
#define GCC_QUPV3_WRAP2_S1_CLK_SRC 100
#define GCC_QUPV3_WRAP2_S2_CLK 101
#define GCC_QUPV3_WRAP2_S2_CLK_SRC 102
#define GCC_QUPV3_WRAP2_S3_CLK 103
#define GCC_QUPV3_WRAP2_S3_CLK_SRC 104
#define GCC_QUPV3_WRAP2_S4_CLK 105
#define GCC_QUPV3_WRAP2_S4_CLK_SRC 106
#define GCC_QUPV3_WRAP2_S5_CLK 107
#define GCC_QUPV3_WRAP2_S5_CLK_SRC 108
#define GCC_QUPV3_WRAP2_S6_CLK 109
#define GCC_QUPV3_WRAP2_S6_CLK_SRC 110
#define GCC_QUPV3_WRAP2_S7_CLK 111
#define GCC_QUPV3_WRAP2_S7_CLK_SRC 112
#define GCC_QUPV3_WRAP_1_M_AHB_CLK 113
#define GCC_QUPV3_WRAP_1_S_AHB_CLK 114
#define GCC_QUPV3_WRAP_2_IBI_2_AHB_CLK 115
#define GCC_QUPV3_WRAP_2_IBI_3_AHB_CLK 116
#define GCC_QUPV3_WRAP_2_M_AHB_CLK 117
#define GCC_QUPV3_WRAP_2_S_AHB_CLK 118
#define GCC_SDCC1_AHB_CLK 119
#define GCC_SDCC1_APPS_CLK 120
#define GCC_SDCC1_APPS_CLK_SRC 121
#define GCC_SDCC1_ICE_CORE_CLK 122
#define GCC_SDCC1_ICE_CORE_CLK_SRC 123
#define GCC_SDCC2_AHB_CLK 124
#define GCC_SDCC2_APPS_CLK 125
#define GCC_SDCC2_APPS_CLK_SRC 126
#define GCC_UFS_PHY_AHB_CLK 127
#define GCC_UFS_PHY_AXI_CLK 128
#define GCC_UFS_PHY_AXI_CLK_SRC 129
#define GCC_UFS_PHY_ICE_CORE_CLK 130
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 131
#define GCC_UFS_PHY_PHY_AUX_CLK 132
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 133
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 134
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 135
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 136
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 137
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 138
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 139
#define GCC_UFS_PHY_UNIPRO_CORE_CLK 140
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 141
#define GCC_USB30_PRIM_ATB_CLK 142
#define GCC_USB30_PRIM_MASTER_CLK 143
#define GCC_USB30_PRIM_MASTER_CLK_SRC 144
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 145
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 146
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 147
#define GCC_USB30_PRIM_SLEEP_CLK 148
#define GCC_USB3_PRIM_PHY_AUX_CLK 149
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 150
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 151
#define GCC_USB3_PRIM_PHY_PIPE_CLK 152
#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 153
#define GCC_VIDEO_AHB_CLK 154
#define GCC_VIDEO_AXI0_CLK 155
#define GCC_VIDEO_AXI1_CLK 156
#define GCC_VIDEO_XO_CLK 157
#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 158
#define GCC_UFS_PHY_AXI_HW_CTL_CLK 159
#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 160
#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 161
#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 162
/* GCC power domains */
#define GCC_PCIE_0_GDSC 0
#define GCC_PCIE_0_PHY_GDSC 1
#define GCC_UFS_MEM_PHY_GDSC 2
#define GCC_UFS_PHY_GDSC 3
#define GCC_USB30_PRIM_GDSC 4
#define GCC_USB3_PHY_GDSC 5
/* GCC resets */
#define GCC_AHB2PHY_CENTER_BCR 0
#define GCC_CAMERA_BCR 1
#define GCC_CM_PHY_REFGEN3_BCR 2
#define GCC_DISPLAY_BCR 3
#define GCC_GPU_BCR 4
#define GCC_PCIE_0_BCR 5
#define GCC_PCIE_0_LINK_DOWN_BCR 6
#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 7
#define GCC_PCIE_0_PHY_BCR 8
#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 9
#define GCC_PCIE_1_BCR 10
#define GCC_PCIE_1_LINK_DOWN_BCR 11
#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 12
#define GCC_PCIE_1_PHY_BCR 13
#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 14
#define GCC_PCIE_PHY_BCR 15
#define GCC_PCIE_PHY_CFG_AHB_BCR 16
#define GCC_PCIE_PHY_COM_BCR 17
#define GCC_PCIE_RSCC_BCR 18
#define GCC_PDM_BCR 19
#define GCC_QUPV3_WRAPPER_1_BCR 20
#define GCC_QUPV3_WRAPPER_2_BCR 21
#define GCC_QUSB2PHY_PRIM_BCR 22
#define GCC_QUSB2PHY_SEC_BCR 23
#define GCC_SDCC1_BCR 24
#define GCC_SDCC2_BCR 25
#define GCC_UFS_PHY_BCR 26
#define GCC_USB30_PRIM_BCR 27
#define GCC_USB3_DP_PHY_PRIM_BCR 28
#define GCC_USB3_DP_PHY_SEC_BCR 29
#define GCC_USB3_PHY_PRIM_BCR 30
#define GCC_USB3_PHY_SEC_BCR 31
#define GCC_USB3PHY_PHY_PRIM_BCR 32
#define GCC_USB3PHY_PHY_SEC_BCR 33
#define GCC_VIDEO_BCR 34
#define GCC_VIDEO_AXI0_CLK_ARES 35
#define GCC_VIDEO_AXI1_CLK_ARES 36
#endif

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include/dt-bindings/clock/qcom,gcc-monaco.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_MONACO_H
#define _DT_BINDINGS_CLK_QCOM_GCC_MONACO_H
/* GCC clocks */
#define GPLL0 0
#define GPLL0_OUT_EVEN 1
#define GPLL1 2
#define GPLL10 3
#define GPLL3 4
#define GPLL3_OUT_EVEN 5
#define GPLL4 6
#define GPLL6 7
#define GPLL6_OUT_EVEN 8
#define GPLL7 9
#define GPLL8 10
#define GPLL8_OUT_EVEN 11
#define GPLL9 12
#define GPLL9_OUT_EVEN 13
#define GCC_AHB2PHY_CSI_CLK 14
#define GCC_AHB2PHY_USB_CLK 15
#define GCC_BIMC_GPU_AXI_CLK 16
#define GCC_BOOT_ROM_AHB_CLK 17
#define GCC_CAM_THROTTLE_NRT_CLK 18
#define GCC_CAM_THROTTLE_RT_CLK 19
#define GCC_CAMERA_AHB_CLK 20
#define GCC_CAMERA_XO_CLK 21
#define GCC_CAMSS_AXI_CLK 22
#define GCC_CAMSS_AXI_CLK_SRC 23
#define GCC_CAMSS_CAMNOC_ATB_CLK 24
#define GCC_CAMSS_CAMNOC_NTS_XO_CLK 25
#define GCC_CAMSS_CCI_0_CLK 26
#define GCC_CAMSS_CCI_CLK_SRC 27
#define GCC_CAMSS_CPHY_0_CLK 28
#define GCC_CAMSS_CPHY_1_CLK 29
#define GCC_CAMSS_CSI0PHYTIMER_CLK 30
#define GCC_CAMSS_CSI0PHYTIMER_CLK_SRC 31
#define GCC_CAMSS_CSI1PHYTIMER_CLK 32
#define GCC_CAMSS_CSI1PHYTIMER_CLK_SRC 33
#define GCC_CAMSS_MCLK0_CLK 34
#define GCC_CAMSS_MCLK0_CLK_SRC 35
#define GCC_CAMSS_MCLK1_CLK 36
#define GCC_CAMSS_MCLK1_CLK_SRC 37
#define GCC_CAMSS_MCLK2_CLK 38
#define GCC_CAMSS_MCLK2_CLK_SRC 39
#define GCC_CAMSS_MCLK3_CLK 40
#define GCC_CAMSS_MCLK3_CLK_SRC 41
#define GCC_CAMSS_NRT_AXI_CLK 42
#define GCC_CAMSS_OPE_AHB_CLK 43
#define GCC_CAMSS_OPE_AHB_CLK_SRC 44
#define GCC_CAMSS_OPE_CLK 45
#define GCC_CAMSS_OPE_CLK_SRC 46
#define GCC_CAMSS_RT_AXI_CLK 47
#define GCC_CAMSS_TFE_0_CLK 48
#define GCC_CAMSS_TFE_0_CLK_SRC 49
#define GCC_CAMSS_TFE_0_CPHY_RX_CLK 50
#define GCC_CAMSS_TFE_0_CSID_CLK 51
#define GCC_CAMSS_TFE_0_CSID_CLK_SRC 52
#define GCC_CAMSS_TFE_1_CLK 53
#define GCC_CAMSS_TFE_1_CLK_SRC 54
#define GCC_CAMSS_TFE_1_CPHY_RX_CLK 55
#define GCC_CAMSS_TFE_1_CSID_CLK 56
#define GCC_CAMSS_TFE_1_CSID_CLK_SRC 57
#define GCC_CAMSS_TFE_CPHY_RX_CLK_SRC 58
#define GCC_CAMSS_TOP_AHB_CLK 59
#define GCC_CAMSS_TOP_AHB_CLK_SRC 60
#define GCC_CFG_NOC_USB2_PRIM_AXI_CLK 61
#define GCC_CPUSS_AHB_CLK_SRC 62
#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 63
#define GCC_CPUSS_GNOC_CLK 64
#define GCC_DISP_AHB_CLK 65
#define GCC_DISP_GPLL0_CLK_SRC 66
#define GCC_DISP_HF_AXI_CLK 67
#define GCC_DISP_THROTTLE_CORE_CLK 68
#define GCC_DISP_XO_CLK 69
#define GCC_GP1_CLK 70
#define GCC_GP1_CLK_SRC 71
#define GCC_GP2_CLK 72
#define GCC_GP2_CLK_SRC 73
#define GCC_GP3_CLK 74
#define GCC_GP3_CLK_SRC 75
#define GCC_GPU_CFG_AHB_CLK 76
#define GCC_GPU_GPLL0_CLK_SRC 77
#define GCC_GPU_GPLL0_DIV_CLK_SRC 78
#define GCC_GPU_IREF_CLK 79
#define GCC_GPU_MEMNOC_GFX_CLK 80
#define GCC_GPU_SNOC_DVM_GFX_CLK 81
#define GCC_GPU_THROTTLE_CORE_CLK 82
#define GCC_PDM2_CLK 83
#define GCC_PDM2_CLK_SRC 84
#define GCC_PDM_AHB_CLK 85
#define GCC_PDM_XO4_CLK 86
#define GCC_PWM0_XO512_CLK 87
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 88
#define GCC_QMIP_CAMERA_RT_AHB_CLK 89
#define GCC_QMIP_DISP_AHB_CLK 90
#define GCC_QMIP_GPU_CFG_AHB_CLK 91
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 92
#define GCC_QUPV3_WRAP0_CORE_2X_CLK 93
#define GCC_QUPV3_WRAP0_CORE_CLK 94
#define GCC_QUPV3_WRAP0_S0_CLK 95
#define GCC_QUPV3_WRAP0_S0_CLK_SRC 96
#define GCC_QUPV3_WRAP0_S1_CLK 97
#define GCC_QUPV3_WRAP0_S1_CLK_SRC 98
#define GCC_QUPV3_WRAP0_S2_CLK 99
#define GCC_QUPV3_WRAP0_S2_CLK_SRC 100
#define GCC_QUPV3_WRAP0_S3_CLK 101
#define GCC_QUPV3_WRAP0_S3_CLK_SRC 102
#define GCC_QUPV3_WRAP0_S4_CLK 103
#define GCC_QUPV3_WRAP0_S4_CLK_SRC 104
#define GCC_QUPV3_WRAP0_S5_CLK 105
#define GCC_QUPV3_WRAP0_S5_CLK_SRC 106
#define GCC_QUPV3_WRAP0_S6_CLK 107
#define GCC_QUPV3_WRAP0_S6_CLK_SRC 108
#define GCC_QUPV3_WRAP0_S7_CLK 109
#define GCC_QUPV3_WRAP0_S7_CLK_SRC 110
#define GCC_QUPV3_WRAP_0_M_AHB_CLK 111
#define GCC_QUPV3_WRAP_0_S_AHB_CLK 112
#define GCC_SDCC1_AHB_CLK 113
#define GCC_SDCC1_APPS_CLK 114
#define GCC_SDCC1_APPS_CLK_SRC 115
#define GCC_SDCC1_ICE_CORE_CLK 116
#define GCC_SDCC1_ICE_CORE_CLK_SRC 117
#define GCC_SDCC2_AHB_CLK 118
#define GCC_SDCC2_APPS_CLK 119
#define GCC_SDCC2_APPS_CLK_SRC 120
#define GCC_SYS_NOC_CPUSS_AHB_CLK 121
#define GCC_SYS_NOC_USB2_PRIM_AXI_CLK 122
#define GCC_USB20_MASTER_CLK 123
#define GCC_USB20_MASTER_CLK_SRC 124
#define GCC_USB20_MOCK_UTMI_CLK 125
#define GCC_USB20_MOCK_UTMI_CLK_SRC 126
#define GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 127
#define GCC_USB20_SLEEP_CLK 128
#define GCC_USB2_PRIM_CLKREF_CLK 129
#define GCC_VCODEC0_AXI_CLK 130
#define GCC_VENUS_AHB_CLK 131
#define GCC_VENUS_CTL_AXI_CLK 132
#define GCC_VIDEO_AHB_CLK 133
#define GCC_VIDEO_THROTTLE_CORE_CLK 134
#define GCC_VIDEO_VCODEC0_SYS_CLK 135
#define GCC_VIDEO_VENUS_CLK_SRC 136
#define GCC_VIDEO_VENUS_CTL_CLK 137
#define GCC_VIDEO_XO_CLK 138
/* GCC resets */
#define GCC_CAMSS_OPE_BCR 0
#define GCC_CAMSS_TFE_BCR 1
#define GCC_CAMSS_TOP_BCR 2
#define GCC_GPU_BCR 3
#define GCC_MMSS_BCR 4
#define GCC_PDM_BCR 5
#define GCC_QUPV3_WRAPPER_0_BCR 6
#define GCC_QUSB2PHY_PRIM_BCR 7
#define GCC_QUSB2PHY_SEC_BCR 8
#define GCC_SDCC1_BCR 9
#define GCC_SDCC2_BCR 10
#define GCC_USB20_PRIM_BCR 11
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 12
#define GCC_VCODEC0_BCR 13
#define GCC_VENUS_BCR 14
#define GCC_VIDEO_INTERFACE_BCR 15
#endif

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2021, 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_PARROT_H
#define _DT_BINDINGS_CLK_QCOM_GCC_PARROT_H
/* GCC clocks */
#define GCC_GPLL0 0
#define GCC_GPLL0_OUT_EVEN 1
#define GCC_GPLL0_OUT_ODD 2
#define GCC_GPLL1 3
#define GCC_GPLL10 4
#define GCC_GPLL4 5
#define GCC_GPLL9 6
#define GCC_AGGRE_NOC_PCIE_0_AXI_CLK 7
#define GCC_AGGRE_UFS_PHY_AXI_CLK 8
#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 9
#define GCC_AGGRE_USB3_PRIM_AXI_CLK 10
#define GCC_BOOT_ROM_AHB_CLK 11
#define GCC_CAMERA_AHB_CLK 12
#define GCC_CAMERA_HF_AXI_CLK 13
#define GCC_CAMERA_SF_AXI_CLK 14
#define GCC_CAMERA_SLEEP_CLK 15
#define GCC_CAMERA_XO_CLK 16
#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 17
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 18
#define GCC_DDRSS_GPU_AXI_CLK 19
#define GCC_DDRSS_PCIE_SF_TBU_CLK 20
#define GCC_DISP_AHB_CLK 21
#define GCC_DISP_HF_AXI_CLK 22
#define GCC_DISP_XO_CLK 23
#define GCC_EUSB3_0_CLKREF_EN 24
#define GCC_GP1_CLK 25
#define GCC_GP1_CLK_SRC 26
#define GCC_GP2_CLK 27
#define GCC_GP2_CLK_SRC 28
#define GCC_GP3_CLK 29
#define GCC_GP3_CLK_SRC 30
#define GCC_GPU_CFG_AHB_CLK 31
#define GCC_GPU_GPLL0_CLK_SRC 32
#define GCC_GPU_GPLL0_DIV_CLK_SRC 33
#define GCC_GPU_MEMNOC_GFX_CLK 34
#define GCC_GPU_SNOC_DVM_GFX_CLK 35
#define GCC_PCIE_0_AUX_CLK 36
#define GCC_PCIE_0_AUX_CLK_SRC 37
#define GCC_PCIE_0_CFG_AHB_CLK 38
#define GCC_PCIE_0_CLKREF_EN 39
#define GCC_PCIE_0_MSTR_AXI_CLK 40
#define GCC_PCIE_0_PHY_RCHNG_CLK 41
#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 42
#define GCC_PCIE_0_PIPE_CLK 43
#define GCC_PCIE_0_PIPE_CLK_SRC 44
#define GCC_PCIE_0_PIPE_DIV2_CLK 45
#define GCC_PCIE_0_PIPE_DIV2_CLK_SRC 46
#define GCC_PCIE_0_SLV_AXI_CLK 47
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 48
#define GCC_PDM2_CLK 49
#define GCC_PDM2_CLK_SRC 50
#define GCC_PDM_AHB_CLK 51
#define GCC_PDM_XO4_CLK 52
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 53
#define GCC_QMIP_CAMERA_RT_AHB_CLK 54
#define GCC_QMIP_DISP_AHB_CLK 55
#define GCC_QMIP_GPU_AHB_CLK 56
#define GCC_QMIP_PCIE_AHB_CLK 57
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 58
#define GCC_QUPV3_WRAP0_CORE_2X_CLK 59
#define GCC_QUPV3_WRAP0_CORE_CLK 60
#define GCC_QUPV3_WRAP0_QSPI0_CLK 61
#define GCC_QUPV3_WRAP0_S0_CLK 62
#define GCC_QUPV3_WRAP0_S0_CLK_SRC 63
#define GCC_QUPV3_WRAP0_S1_CLK 64
#define GCC_QUPV3_WRAP0_S1_CLK_SRC 65
#define GCC_QUPV3_WRAP0_S2_CLK 66
#define GCC_QUPV3_WRAP0_S2_CLK_SRC 67
#define GCC_QUPV3_WRAP0_S3_CLK 68
#define GCC_QUPV3_WRAP0_S3_CLK_SRC 69
#define GCC_QUPV3_WRAP0_S4_CLK 70
#define GCC_QUPV3_WRAP0_S4_CLK_SRC 71
#define GCC_QUPV3_WRAP0_S5_CLK 72
#define GCC_QUPV3_WRAP0_S5_CLK_SRC 73
#define GCC_QUPV3_WRAP0_S5_DIV_CLK_SRC 74
#define GCC_QUPV3_WRAP1_CORE_2X_CLK 75
#define GCC_QUPV3_WRAP1_CORE_CLK 76
#define GCC_QUPV3_WRAP1_QSPI0_CLK 77
#define GCC_QUPV3_WRAP1_S0_CLK 78
#define GCC_QUPV3_WRAP1_S0_CLK_SRC 79
#define GCC_QUPV3_WRAP1_S1_CLK 80
#define GCC_QUPV3_WRAP1_S1_CLK_SRC 81
#define GCC_QUPV3_WRAP1_S2_CLK 82
#define GCC_QUPV3_WRAP1_S2_CLK_SRC 83
#define GCC_QUPV3_WRAP1_S3_CLK 84
#define GCC_QUPV3_WRAP1_S3_CLK_SRC 85
#define GCC_QUPV3_WRAP1_S4_CLK 86
#define GCC_QUPV3_WRAP1_S4_CLK_SRC 87
#define GCC_QUPV3_WRAP1_S5_CLK 88
#define GCC_QUPV3_WRAP1_S5_CLK_SRC 89
#define GCC_QUPV3_WRAP1_S5_DIV_CLK_SRC 90
#define GCC_QUPV3_WRAP_0_M_AHB_CLK 91
#define GCC_QUPV3_WRAP_0_S_AHB_CLK 92
#define GCC_QUPV3_WRAP_1_M_AHB_CLK 93
#define GCC_QUPV3_WRAP_1_S_AHB_CLK 94
#define GCC_SDCC1_AHB_CLK 95
#define GCC_SDCC1_APPS_CLK 96
#define GCC_SDCC1_APPS_CLK_SRC 97
#define GCC_SDCC1_ICE_CORE_CLK 98
#define GCC_SDCC1_ICE_CORE_CLK_SRC 99
#define GCC_SDCC2_AHB_CLK 100
#define GCC_SDCC2_APPS_CLK 101
#define GCC_SDCC2_APPS_CLK_SRC 102
#define GCC_UFS_0_CLKREF_EN 103
#define GCC_UFS_PAD_CLKREF_EN 104
#define GCC_UFS_PHY_AHB_CLK 105
#define GCC_UFS_PHY_AXI_CLK 106
#define GCC_UFS_PHY_AXI_CLK_SRC 107
#define GCC_UFS_PHY_ICE_CORE_CLK 108
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 109
#define GCC_UFS_PHY_PHY_AUX_CLK 110
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 111
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 112
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 113
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 114
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 115
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 116
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 117
#define GCC_UFS_PHY_UNIPRO_CORE_CLK 118
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 119
#define GCC_USB30_PRIM_MASTER_CLK 120
#define GCC_USB30_PRIM_MASTER_CLK_SRC 121
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 122
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 123
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 124
#define GCC_USB30_PRIM_SLEEP_CLK 125
#define GCC_USB3_0_CLKREF_EN 126
#define GCC_USB3_PRIM_PHY_AUX_CLK 127
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 128
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 129
#define GCC_USB3_PRIM_PHY_PIPE_CLK 130
#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 131
#define GCC_UFS_PHY_AXI_HW_CTL_CLK 132
#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 133
#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 134
#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 135
#define GCC_VIDEO_AHB_CLK 136
#define GCC_VIDEO_AXI0_CLK 137
#define GCC_VIDEO_THROTTLE_CORE_CLK 138
#define GCC_VIDEO_XO_CLK 139
/* GCC resets */
#define GCC_CAMERA_BCR 0
#define GCC_DISPLAY_BCR 1
#define GCC_EMMC_BCR 2
#define GCC_GPU_BCR 3
#define GCC_PCIE_0_BCR 4
#define GCC_PCIE_0_LINK_DOWN_BCR 5
#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 6
#define GCC_PCIE_0_PHY_BCR 7
#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 8
#define GCC_PCIE_PHY_CFG_AHB_BCR 9
#define GCC_PCIE_PHY_COM_BCR 10
#define GCC_PDM_BCR 11
#define GCC_QUPV3_WRAPPER_0_BCR 12
#define GCC_QUPV3_WRAPPER_1_BCR 13
#define GCC_QUSB2PHY_PRIM_BCR 14
#define GCC_QUSB2PHY_SEC_BCR 15
#define GCC_SDCC2_BCR 16
#define GCC_UFS_PHY_BCR 17
#define GCC_USB30_PRIM_BCR 18
#define GCC_USB3_DP_PHY_PRIM_BCR 19
#define GCC_USB3_DP_PHY_SEC_BCR 20
#define GCC_USB3_PHY_PRIM_BCR 21
#define GCC_USB3_PHY_SEC_BCR 22
#define GCC_USB3PHY_PHY_PRIM_BCR 23
#define GCC_USB3PHY_PHY_SEC_BCR 24
#define GCC_VIDEO_AXI0_CLK_ARES 25
#define GCC_VIDEO_BCR 26
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_PINEAPPLE_H
#define _DT_BINDINGS_CLK_QCOM_GCC_PINEAPPLE_H
/* GCC clocks */
#define GCC_AGGRE_NOC_PCIE_AXI_CLK 0
#define GCC_AGGRE_UFS_PHY_AXI_CLK 1
#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 2
#define GCC_AGGRE_USB3_PRIM_AXI_CLK 3
#define GCC_BOOT_ROM_AHB_CLK 4
#define GCC_CAMERA_AHB_CLK 5
#define GCC_CAMERA_HF_AXI_CLK 6
#define GCC_CAMERA_SF_AXI_CLK 7
#define GCC_CAMERA_XO_CLK 8
#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 9
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 10
#define GCC_CNOC_PCIE_SF_AXI_CLK 11
#define GCC_CPUSS_UBWCP_CLK 12
#define GCC_CPUSS_UBWCP_CLK_SRC 13
#define GCC_DDRSS_GPU_AXI_CLK 14
#define GCC_DDRSS_PCIE_SF_QTB_CLK 15
#define GCC_DDRSS_UBWCP_CLK 16
#define GCC_DISP_AHB_CLK 17
#define GCC_DISP_HF_AXI_CLK 18
#define GCC_DISP_XO_CLK 19
#define GCC_GP1_CLK 20
#define GCC_GP1_CLK_SRC 21
#define GCC_GP2_CLK 22
#define GCC_GP2_CLK_SRC 23
#define GCC_GP3_CLK 24
#define GCC_GP3_CLK_SRC 25
#define GCC_GPLL0 26
#define GCC_GPLL0_OUT_EVEN 27
#define GCC_GPLL1 28
#define GCC_GPLL3 29
#define GCC_GPLL4 30
#define GCC_GPLL6 31
#define GCC_GPLL7 32
#define GCC_GPLL9 33
#define GCC_GPU_CFG_AHB_CLK 34
#define GCC_GPU_GPLL0_CLK_SRC 35
#define GCC_GPU_GPLL0_DIV_CLK_SRC 36
#define GCC_GPU_MEMNOC_GFX_CLK 37
#define GCC_GPU_SNOC_DVM_GFX_CLK 38
#define GCC_PCIE_0_AUX_CLK 39
#define GCC_PCIE_0_AUX_CLK_SRC 40
#define GCC_PCIE_0_CFG_AHB_CLK 41
#define GCC_PCIE_0_MSTR_AXI_CLK 42
#define GCC_PCIE_0_PHY_RCHNG_CLK 43
#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 44
#define GCC_PCIE_0_PIPE_CLK 45
#define GCC_PCIE_0_PIPE_CLK_SRC 46
#define GCC_PCIE_0_SLV_AXI_CLK 47
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 48
#define GCC_PCIE_1_AUX_CLK 49
#define GCC_PCIE_1_AUX_CLK_SRC 50
#define GCC_PCIE_1_CFG_AHB_CLK 51
#define GCC_PCIE_1_MSTR_AXI_CLK 52
#define GCC_PCIE_1_PHY_AUX_CLK 53
#define GCC_PCIE_1_PHY_AUX_CLK_SRC 54
#define GCC_PCIE_1_PHY_RCHNG_CLK 55
#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 56
#define GCC_PCIE_1_PIPE_CLK 57
#define GCC_PCIE_1_PIPE_CLK_SRC 58
#define GCC_PCIE_1_SLV_AXI_CLK 59
#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 60
#define GCC_PDM2_CLK 61
#define GCC_PDM2_CLK_SRC 62
#define GCC_PDM_AHB_CLK 63
#define GCC_PDM_XO4_CLK 64
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 65
#define GCC_QMIP_CAMERA_RT_AHB_CLK 66
#define GCC_QMIP_DISP_AHB_CLK 67
#define GCC_QMIP_GPU_AHB_CLK 68
#define GCC_QMIP_PCIE_AHB_CLK 69
#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 70
#define GCC_QMIP_VIDEO_CVP_AHB_CLK 71
#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 72
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 73
#define GCC_QUPV3_I2C_CORE_CLK 74
#define GCC_QUPV3_I2C_S0_CLK 75
#define GCC_QUPV3_I2C_S0_CLK_SRC 76
#define GCC_QUPV3_I2C_S1_CLK 77
#define GCC_QUPV3_I2C_S1_CLK_SRC 78
#define GCC_QUPV3_I2C_S2_CLK 79
#define GCC_QUPV3_I2C_S2_CLK_SRC 80
#define GCC_QUPV3_I2C_S3_CLK 81
#define GCC_QUPV3_I2C_S3_CLK_SRC 82
#define GCC_QUPV3_I2C_S4_CLK 83
#define GCC_QUPV3_I2C_S4_CLK_SRC 84
#define GCC_QUPV3_I2C_S5_CLK 85
#define GCC_QUPV3_I2C_S5_CLK_SRC 86
#define GCC_QUPV3_I2C_S6_CLK 87
#define GCC_QUPV3_I2C_S6_CLK_SRC 88
#define GCC_QUPV3_I2C_S7_CLK 89
#define GCC_QUPV3_I2C_S7_CLK_SRC 90
#define GCC_QUPV3_I2C_S8_CLK 91
#define GCC_QUPV3_I2C_S8_CLK_SRC 92
#define GCC_QUPV3_I2C_S9_CLK 93
#define GCC_QUPV3_I2C_S9_CLK_SRC 94
#define GCC_QUPV3_I2C_S_AHB_CLK 95
#define GCC_QUPV3_WRAP1_CORE_2X_CLK 96
#define GCC_QUPV3_WRAP1_CORE_CLK 97
#define GCC_QUPV3_WRAP1_QSPI_REF_CLK 98
#define GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC 99
#define GCC_QUPV3_WRAP1_S0_CLK 100
#define GCC_QUPV3_WRAP1_S0_CLK_SRC 101
#define GCC_QUPV3_WRAP1_S1_CLK 102
#define GCC_QUPV3_WRAP1_S1_CLK_SRC 103
#define GCC_QUPV3_WRAP1_S2_CLK 104
#define GCC_QUPV3_WRAP1_S2_CLK_SRC 105
#define GCC_QUPV3_WRAP1_S3_CLK 106
#define GCC_QUPV3_WRAP1_S3_CLK_SRC 107
#define GCC_QUPV3_WRAP1_S4_CLK 108
#define GCC_QUPV3_WRAP1_S4_CLK_SRC 109
#define GCC_QUPV3_WRAP1_S5_CLK 110
#define GCC_QUPV3_WRAP1_S5_CLK_SRC 111
#define GCC_QUPV3_WRAP1_S6_CLK 112
#define GCC_QUPV3_WRAP1_S6_CLK_SRC 113
#define GCC_QUPV3_WRAP1_S7_CLK 114
#define GCC_QUPV3_WRAP1_S7_CLK_SRC 115
#define GCC_QUPV3_WRAP2_CORE_2X_CLK 116
#define GCC_QUPV3_WRAP2_CORE_CLK 117
#define GCC_QUPV3_WRAP2_IBI_CTRL_0_CLK_SRC 118
#define GCC_QUPV3_WRAP2_IBI_CTRL_2_CLK 119
#define GCC_QUPV3_WRAP2_IBI_CTRL_3_CLK 120
#define GCC_QUPV3_WRAP2_S0_CLK 121
#define GCC_QUPV3_WRAP2_S0_CLK_SRC 122
#define GCC_QUPV3_WRAP2_S1_CLK 123
#define GCC_QUPV3_WRAP2_S1_CLK_SRC 124
#define GCC_QUPV3_WRAP2_S2_CLK 125
#define GCC_QUPV3_WRAP2_S2_CLK_SRC 126
#define GCC_QUPV3_WRAP2_S3_CLK 127
#define GCC_QUPV3_WRAP2_S3_CLK_SRC 128
#define GCC_QUPV3_WRAP2_S4_CLK 129
#define GCC_QUPV3_WRAP2_S4_CLK_SRC 130
#define GCC_QUPV3_WRAP2_S5_CLK 131
#define GCC_QUPV3_WRAP2_S5_CLK_SRC 132
#define GCC_QUPV3_WRAP2_S6_CLK 133
#define GCC_QUPV3_WRAP2_S6_CLK_SRC 134
#define GCC_QUPV3_WRAP2_S7_CLK 135
#define GCC_QUPV3_WRAP2_S7_CLK_SRC 136
#define GCC_QUPV3_WRAP3_CORE_2X_CLK 137
#define GCC_QUPV3_WRAP3_CORE_CLK 138
#define GCC_QUPV3_WRAP3_QSPI_REF_CLK 139
#define GCC_QUPV3_WRAP3_QSPI_REF_CLK_SRC 140
#define GCC_QUPV3_WRAP3_S0_CLK 141
#define GCC_QUPV3_WRAP3_S0_CLK_SRC 142
#define GCC_QUPV3_WRAP_1_M_AHB_CLK 143
#define GCC_QUPV3_WRAP_1_S_AHB_CLK 144
#define GCC_QUPV3_WRAP_2_IBI_2_AHB_CLK 145
#define GCC_QUPV3_WRAP_2_IBI_3_AHB_CLK 146
#define GCC_QUPV3_WRAP_2_M_AHB_CLK 147
#define GCC_QUPV3_WRAP_2_S_AHB_CLK 148
#define GCC_QUPV3_WRAP_3_M_AHB_CLK 149
#define GCC_QUPV3_WRAP_3_S_AHB_CLK 150
#define GCC_SDCC2_AHB_CLK 151
#define GCC_SDCC2_APPS_CLK 152
#define GCC_SDCC2_APPS_CLK_SRC 153
#define GCC_SDCC4_AHB_CLK 154
#define GCC_SDCC4_APPS_CLK 155
#define GCC_SDCC4_APPS_CLK_SRC 156
#define GCC_UFS_PHY_AHB_CLK 157
#define GCC_UFS_PHY_AXI_CLK 158
#define GCC_UFS_PHY_AXI_CLK_SRC 159
#define GCC_UFS_PHY_AXI_HW_CTL_CLK 160
#define GCC_UFS_PHY_ICE_CORE_CLK 161
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 162
#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 163
#define GCC_UFS_PHY_PHY_AUX_CLK 164
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 165
#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 166
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 167
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 168
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 169
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 170
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 171
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 172
#define GCC_UFS_PHY_UNIPRO_CORE_CLK 173
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 174
#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 175
#define GCC_USB30_PRIM_MASTER_CLK 176
#define GCC_USB30_PRIM_MASTER_CLK_SRC 177
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 178
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 179
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 180
#define GCC_USB30_PRIM_SLEEP_CLK 181
#define GCC_USB3_PRIM_PHY_AUX_CLK 182
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 183
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 184
#define GCC_USB3_PRIM_PHY_PIPE_CLK 185
#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 186
#define GCC_VIDEO_AHB_CLK 187
#define GCC_VIDEO_AXI0_CLK 188
#define GCC_VIDEO_AXI1_CLK 189
#define GCC_VIDEO_XO_CLK 190
#define GCC_GPLL0_AO 191
#define GCC_GPLL0_OUT_EVEN_AO 192
#define GCC_GPLL1_AO 193
#define GCC_GPLL3_AO 194
#define GCC_GPLL4_AO 195
#define GCC_GPLL6_AO 196
/* GCC resets */
#define GCC_CAMERA_BCR 0
#define GCC_DISPLAY_BCR 1
#define GCC_GPU_BCR 2
#define GCC_PCIE_0_BCR 3
#define GCC_PCIE_0_LINK_DOWN_BCR 4
#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5
#define GCC_PCIE_0_PHY_BCR 6
#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7
#define GCC_PCIE_1_BCR 8
#define GCC_PCIE_1_LINK_DOWN_BCR 9
#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 10
#define GCC_PCIE_1_PHY_BCR 11
#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 12
#define GCC_PCIE_PHY_BCR 13
#define GCC_PCIE_PHY_CFG_AHB_BCR 14
#define GCC_PCIE_PHY_COM_BCR 15
#define GCC_PDM_BCR 16
#define GCC_QUPV3_WRAPPER_1_BCR 17
#define GCC_QUPV3_WRAPPER_2_BCR 18
#define GCC_QUPV3_WRAPPER_3_BCR 19
#define GCC_QUPV3_WRAPPER_I2C_BCR 20
#define GCC_QUSB2PHY_PRIM_BCR 21
#define GCC_QUSB2PHY_SEC_BCR 22
#define GCC_SDCC2_BCR 23
#define GCC_SDCC4_BCR 24
#define GCC_UFS_PHY_BCR 25
#define GCC_USB30_PRIM_BCR 26
#define GCC_USB3_DP_PHY_PRIM_BCR 27
#define GCC_USB3_DP_PHY_SEC_BCR 28
#define GCC_USB3_PHY_PRIM_BCR 29
#define GCC_USB3_PHY_SEC_BCR 30
#define GCC_USB3PHY_PHY_PRIM_BCR 31
#define GCC_USB3PHY_PHY_SEC_BCR 32
#define GCC_VIDEO_AXI0_CLK_ARES 33
#define GCC_VIDEO_AXI1_CLK_ARES 34
#define GCC_VIDEO_BCR 35
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SUN_H
#define _DT_BINDINGS_CLK_QCOM_GCC_SUN_H
/* GCC clocks */
#define GCC_AGGRE_NOC_PCIE_AXI_CLK 0
#define GCC_AGGRE_UFS_PHY_AXI_CLK 1
#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 2
#define GCC_AGGRE_USB3_PRIM_AXI_CLK 3
#define GCC_BOOT_ROM_AHB_CLK 4
#define GCC_CAM_BIST_MCLK_AHB_CLK 5
#define GCC_CAMERA_AHB_CLK 6
#define GCC_CAMERA_HF_AXI_CLK 7
#define GCC_CAMERA_SF_AXI_CLK 8
#define GCC_CAMERA_XO_CLK 9
#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 10
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 11
#define GCC_CNOC_PCIE_SF_AXI_CLK 12
#define GCC_DDRSS_GPU_AXI_CLK 13
#define GCC_DDRSS_PCIE_SF_QTB_CLK 14
#define GCC_DISP_AHB_CLK 15
#define GCC_DISP_HF_AXI_CLK 16
#define GCC_EVA_AHB_CLK 17
#define GCC_EVA_AXI0_CLK 18
#define GCC_EVA_AXI0C_CLK 19
#define GCC_EVA_XO_CLK 20
#define GCC_GP1_CLK 21
#define GCC_GP1_CLK_SRC 22
#define GCC_GP2_CLK 23
#define GCC_GP2_CLK_SRC 24
#define GCC_GP3_CLK 25
#define GCC_GP3_CLK_SRC 26
#define GCC_GPLL0 27
#define GCC_GPLL0_OUT_EVEN 28
#define GCC_GPLL1 29
#define GCC_GPLL4 30
#define GCC_GPLL7 31
#define GCC_GPLL9 32
#define GCC_GPU_CFG_AHB_CLK 33
#define GCC_GPU_GEMNOC_GFX_CLK 34
#define GCC_GPU_GPLL0_CLK_SRC 35
#define GCC_GPU_GPLL0_DIV_CLK_SRC 36
#define GCC_PCIE_0_AUX_CLK 37
#define GCC_PCIE_0_AUX_CLK_SRC 38
#define GCC_PCIE_0_CFG_AHB_CLK 39
#define GCC_PCIE_0_MSTR_AXI_CLK 40
#define GCC_PCIE_0_PHY_RCHNG_CLK 41
#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 42
#define GCC_PCIE_0_PIPE_CLK 43
#define GCC_PCIE_0_PIPE_CLK_SRC 44
#define GCC_PCIE_0_SLV_AXI_CLK 45
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 46
#define GCC_PCIE_RSCC_CFG_AHB_CLK 47
#define GCC_PCIE_RSCC_XO_CLK 48
#define GCC_PDM2_CLK 49
#define GCC_PDM2_CLK_SRC 50
#define GCC_PDM_AHB_CLK 51
#define GCC_PDM_XO4_CLK 52
#define GCC_QMIP_CAMERA_CMD_AHB_CLK 53
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 54
#define GCC_QMIP_CAMERA_RT_AHB_CLK 55
#define GCC_QMIP_GPU_AHB_CLK 56
#define GCC_QMIP_PCIE_AHB_CLK 57
#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 58
#define GCC_QMIP_VIDEO_CVP_AHB_CLK 59
#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 60
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 61
#define GCC_QUPV3_I2C_CORE_CLK 62
#define GCC_QUPV3_I2C_S0_CLK 63
#define GCC_QUPV3_I2C_S0_CLK_SRC 64
#define GCC_QUPV3_I2C_S1_CLK 65
#define GCC_QUPV3_I2C_S1_CLK_SRC 66
#define GCC_QUPV3_I2C_S2_CLK 67
#define GCC_QUPV3_I2C_S2_CLK_SRC 68
#define GCC_QUPV3_I2C_S3_CLK 69
#define GCC_QUPV3_I2C_S3_CLK_SRC 70
#define GCC_QUPV3_I2C_S4_CLK 71
#define GCC_QUPV3_I2C_S4_CLK_SRC 72
#define GCC_QUPV3_I2C_S5_CLK 73
#define GCC_QUPV3_I2C_S5_CLK_SRC 74
#define GCC_QUPV3_I2C_S6_CLK 75
#define GCC_QUPV3_I2C_S6_CLK_SRC 76
#define GCC_QUPV3_I2C_S7_CLK 77
#define GCC_QUPV3_I2C_S7_CLK_SRC 78
#define GCC_QUPV3_I2C_S8_CLK 79
#define GCC_QUPV3_I2C_S8_CLK_SRC 80
#define GCC_QUPV3_I2C_S9_CLK 81
#define GCC_QUPV3_I2C_S9_CLK_SRC 82
#define GCC_QUPV3_I2C_S_AHB_CLK 83
#define GCC_QUPV3_WRAP1_CORE_2X_CLK 84
#define GCC_QUPV3_WRAP1_CORE_CLK 85
#define GCC_QUPV3_WRAP1_QSPI_REF_CLK 86
#define GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC 87
#define GCC_QUPV3_WRAP1_S0_CLK 88
#define GCC_QUPV3_WRAP1_S0_CLK_SRC 89
#define GCC_QUPV3_WRAP1_S1_CLK 90
#define GCC_QUPV3_WRAP1_S1_CLK_SRC 91
#define GCC_QUPV3_WRAP1_S2_CLK 92
#define GCC_QUPV3_WRAP1_S2_CLK_SRC 93
#define GCC_QUPV3_WRAP1_S3_CLK 94
#define GCC_QUPV3_WRAP1_S3_CLK_SRC 95
#define GCC_QUPV3_WRAP1_S4_CLK 96
#define GCC_QUPV3_WRAP1_S4_CLK_SRC 97
#define GCC_QUPV3_WRAP1_S5_CLK 98
#define GCC_QUPV3_WRAP1_S5_CLK_SRC 99
#define GCC_QUPV3_WRAP1_S6_CLK 100
#define GCC_QUPV3_WRAP1_S6_CLK_SRC 101
#define GCC_QUPV3_WRAP1_S7_CLK 102
#define GCC_QUPV3_WRAP1_S7_CLK_SRC 103
#define GCC_QUPV3_WRAP2_CORE_2X_CLK 104
#define GCC_QUPV3_WRAP2_CORE_CLK 105
#define GCC_QUPV3_WRAP2_IBI_CTRL_0_CLK_SRC 106
#define GCC_QUPV3_WRAP2_IBI_CTRL_2_CLK 107
#define GCC_QUPV3_WRAP2_IBI_CTRL_3_CLK 108
#define GCC_QUPV3_WRAP2_S0_CLK 109
#define GCC_QUPV3_WRAP2_S0_CLK_SRC 110
#define GCC_QUPV3_WRAP2_S1_CLK 111
#define GCC_QUPV3_WRAP2_S1_CLK_SRC 112
#define GCC_QUPV3_WRAP2_S2_CLK 113
#define GCC_QUPV3_WRAP2_S2_CLK_SRC 114
#define GCC_QUPV3_WRAP2_S3_CLK 115
#define GCC_QUPV3_WRAP2_S3_CLK_SRC 116
#define GCC_QUPV3_WRAP2_S4_CLK 117
#define GCC_QUPV3_WRAP2_S4_CLK_SRC 118
#define GCC_QUPV3_WRAP2_S5_CLK 119
#define GCC_QUPV3_WRAP2_S5_CLK_SRC 120
#define GCC_QUPV3_WRAP2_S6_CLK 121
#define GCC_QUPV3_WRAP2_S6_CLK_SRC 122
#define GCC_QUPV3_WRAP2_S7_CLK 123
#define GCC_QUPV3_WRAP2_S7_CLK_SRC 124
#define GCC_QUPV3_WRAP_1_M_AHB_CLK 125
#define GCC_QUPV3_WRAP_1_S_AHB_CLK 126
#define GCC_QUPV3_WRAP_2_IBI_2_AHB_CLK 127
#define GCC_QUPV3_WRAP_2_IBI_3_AHB_CLK 128
#define GCC_QUPV3_WRAP_2_M_AHB_CLK 129
#define GCC_QUPV3_WRAP_2_S_AHB_CLK 130
#define GCC_SDCC2_AHB_CLK 131
#define GCC_SDCC2_APPS_CLK 132
#define GCC_SDCC2_APPS_CLK_SRC 133
#define GCC_SDCC4_AHB_CLK 134
#define GCC_SDCC4_APPS_CLK 135
#define GCC_SDCC4_APPS_CLK_SRC 136
#define GCC_UFS_PHY_AHB_CLK 137
#define GCC_UFS_PHY_AXI_CLK 138
#define GCC_UFS_PHY_AXI_CLK_SRC 139
#define GCC_UFS_PHY_AXI_HW_CTL_CLK 140
#define GCC_UFS_PHY_ICE_CORE_CLK 141
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 142
#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 143
#define GCC_UFS_PHY_PHY_AUX_CLK 144
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 145
#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 146
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 147
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 148
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 149
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 150
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 151
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 152
#define GCC_UFS_PHY_UNIPRO_CORE_CLK 153
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 154
#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 155
#define GCC_USB30_PRIM_MASTER_CLK 156
#define GCC_USB30_PRIM_MASTER_CLK_SRC 157
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 158
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 159
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 160
#define GCC_USB30_PRIM_SLEEP_CLK 161
#define GCC_USB3_PRIM_PHY_AUX_CLK 162
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 163
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 164
#define GCC_USB3_PRIM_PHY_PIPE_CLK 165
#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 166
#define GCC_VIDEO_AHB_CLK 167
#define GCC_VIDEO_AXI0_CLK 168
#define GCC_VIDEO_AXI1_CLK 169
#define GCC_VIDEO_XO_CLK 170
/* GCC power domains */
#define GCC_PCIE_0_GDSC 0
#define GCC_PCIE_0_PHY_GDSC 1
#define GCC_UFS_MEM_PHY_GDSC 2
#define GCC_UFS_PHY_GDSC 3
#define GCC_USB30_PRIM_GDSC 4
#define GCC_USB3_PHY_GDSC 5
/* GCC resets */
#define GCC_CAMERA_BCR 0
#define GCC_DISPLAY_BCR 1
#define GCC_EVA_AXI0_CLK_ARES 2
#define GCC_EVA_AXI0C_CLK_ARES 3
#define GCC_EVA_BCR 4
#define GCC_GPU_BCR 5
#define GCC_PCIE_0_BCR 6
#define GCC_PCIE_0_LINK_DOWN_BCR 7
#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 8
#define GCC_PCIE_0_PHY_BCR 9
#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 10
#define GCC_PCIE_PHY_BCR 11
#define GCC_PCIE_PHY_CFG_AHB_BCR 12
#define GCC_PCIE_PHY_COM_BCR 13
#define GCC_PCIE_RSCC_BCR 14
#define GCC_PDM_BCR 15
#define GCC_QUPV3_WRAPPER_1_BCR 16
#define GCC_QUPV3_WRAPPER_2_BCR 17
#define GCC_QUPV3_WRAPPER_I2C_BCR 18
#define GCC_QUSB2PHY_PRIM_BCR 19
#define GCC_QUSB2PHY_SEC_BCR 20
#define GCC_SDCC2_BCR 21
#define GCC_SDCC4_BCR 22
#define GCC_UFS_PHY_BCR 23
#define GCC_USB30_PRIM_BCR 24
#define GCC_USB3_DP_PHY_PRIM_BCR 25
#define GCC_USB3_DP_PHY_SEC_BCR 26
#define GCC_USB3_PHY_PRIM_BCR 27
#define GCC_USB3_PHY_SEC_BCR 28
#define GCC_USB3PHY_PHY_PRIM_BCR 29
#define GCC_USB3PHY_PHY_SEC_BCR 30
#define GCC_VIDEO_AXI0_CLK_ARES 31
#define GCC_VIDEO_AXI1_CLK_ARES 32
#define GCC_VIDEO_BCR 33
#endif

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_TUNA_H
#define _DT_BINDINGS_CLK_QCOM_GCC_TUNA_H
/* GCC clocks */
#define GCC_GPLL0 0
#define GCC_GPLL0_OUT_EVEN 1
#define GCC_GPLL1 2
#define GCC_GPLL4 3
#define GCC_GPLL7 4
#define GCC_GPLL9 5
#define GCC_AGGRE_NOC_PCIE_AXI_CLK 6
#define GCC_AGGRE_UFS_PHY_AXI_CLK 7
#define GCC_AGGRE_USB3_PRIM_AXI_CLK 8
#define GCC_BOOT_ROM_AHB_CLK 9
#define GCC_CAM_BIST_MCLK_AHB_CLK 10
#define GCC_CAMERA_AHB_CLK 11
#define GCC_CAMERA_HF_AXI_CLK 12
#define GCC_CAMERA_SF_AXI_CLK 13
#define GCC_CAMERA_XO_CLK 14
#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 15
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 16
#define GCC_CNOC_PCIE_SF_AXI_CLK 17
#define GCC_DDRSS_GPU_AXI_CLK 18
#define GCC_DDRSS_PCIE_SF_QTB_CLK 19
#define GCC_DISP_AHB_CLK 20
#define GCC_DISP_HF_AXI_CLK 21
#define GCC_EVA_AHB_CLK 22
#define GCC_EVA_AXI0_CLK 23
#define GCC_EVA_AXI0C_CLK 24
#define GCC_EVA_VIDEO_AXI_DCHT_PIPE_CLK 25
#define GCC_EVA_XO_CLK 26
#define GCC_GP1_CLK 27
#define GCC_GP1_CLK_SRC 28
#define GCC_GP2_CLK 29
#define GCC_GP2_CLK_SRC 30
#define GCC_GP3_CLK 31
#define GCC_GP3_CLK_SRC 32
#define GCC_GPU_CFG_AHB_CLK 33
#define GCC_GPU_GEMNOC_GFX_CLK 34
#define GCC_GPU_GPLL0_CPH_CLK_SRC 35
#define GCC_GPU_GPLL0_DIV_CPH_CLK_SRC 36
#define GCC_PCIE_0_AUX_CLK 37
#define GCC_PCIE_0_AUX_CLK_SRC 38
#define GCC_PCIE_0_CFG_AHB_CLK 39
#define GCC_PCIE_0_MSTR_AXI_CLK 40
#define GCC_PCIE_0_PHY_RCHNG_CLK 41
#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 42
#define GCC_PCIE_0_PIPE_CLK 43
#define GCC_PCIE_0_PIPE_CLK_SRC 44
#define GCC_PCIE_0_PIPE_DIV2_CLK 45
#define GCC_PCIE_0_PIPE_DIV2_CLK_SRC 46
#define GCC_PCIE_0_SLV_AXI_CLK 47
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 48
#define GCC_PCIE_RSCC_CFG_AHB_CLK 49
#define GCC_PCIE_RSCC_XO_CLK 50
#define GCC_PDM2_CLK 51
#define GCC_PDM2_CLK_SRC 52
#define GCC_PDM_AHB_CLK 53
#define GCC_PDM_XO4_CLK 54
#define GCC_QMIP_CAMERA_CMD_AHB_CLK 55
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 56
#define GCC_QMIP_CAMERA_RT_AHB_CLK 57
#define GCC_QMIP_GPU_AHB_CLK 58
#define GCC_QMIP_PCIE_AHB_CLK 59
#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 60
#define GCC_QMIP_VIDEO_CVP_AHB_CLK 61
#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 62
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 63
#define GCC_QUPV3_WRAP1_CORE_2X_CLK 64
#define GCC_QUPV3_WRAP1_CORE_CLK 65
#define GCC_QUPV3_WRAP1_QSPI_REF_CLK 66
#define GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC 67
#define GCC_QUPV3_WRAP1_S0_CLK 68
#define GCC_QUPV3_WRAP1_S0_CLK_SRC 69
#define GCC_QUPV3_WRAP1_S1_CLK 70
#define GCC_QUPV3_WRAP1_S1_CLK_SRC 71
#define GCC_QUPV3_WRAP1_S2_CLK 72
#define GCC_QUPV3_WRAP1_S2_CLK_SRC 73
#define GCC_QUPV3_WRAP1_S3_CLK 74
#define GCC_QUPV3_WRAP1_S3_CLK_SRC 75
#define GCC_QUPV3_WRAP1_S4_CLK 76
#define GCC_QUPV3_WRAP1_S4_CLK_SRC 77
#define GCC_QUPV3_WRAP1_S5_CLK 78
#define GCC_QUPV3_WRAP1_S5_CLK_SRC 79
#define GCC_QUPV3_WRAP1_S6_CLK 80
#define GCC_QUPV3_WRAP1_S6_CLK_SRC 81
#define GCC_QUPV3_WRAP1_S7_CLK 82
#define GCC_QUPV3_WRAP1_S7_CLK_SRC 83
#define GCC_QUPV3_WRAP2_CORE_2X_CLK 84
#define GCC_QUPV3_WRAP2_CORE_CLK 85
#define GCC_QUPV3_WRAP2_IBI_CTRL_0_CLK_SRC 86
#define GCC_QUPV3_WRAP2_IBI_CTRL_2_CLK 87
#define GCC_QUPV3_WRAP2_IBI_CTRL_3_CLK 88
#define GCC_QUPV3_WRAP2_S0_CLK 89
#define GCC_QUPV3_WRAP2_S0_CLK_SRC 90
#define GCC_QUPV3_WRAP2_S1_CLK 91
#define GCC_QUPV3_WRAP2_S1_CLK_SRC 92
#define GCC_QUPV3_WRAP2_S2_CLK 93
#define GCC_QUPV3_WRAP2_S2_CLK_SRC 94
#define GCC_QUPV3_WRAP2_S3_CLK 95
#define GCC_QUPV3_WRAP2_S3_CLK_SRC 96
#define GCC_QUPV3_WRAP2_S4_CLK 97
#define GCC_QUPV3_WRAP2_S4_CLK_SRC 98
#define GCC_QUPV3_WRAP2_S5_CLK 99
#define GCC_QUPV3_WRAP2_S5_CLK_SRC 100
#define GCC_QUPV3_WRAP2_S6_CLK 101
#define GCC_QUPV3_WRAP2_S6_CLK_SRC 102
#define GCC_QUPV3_WRAP2_S7_CLK 103
#define GCC_QUPV3_WRAP2_S7_CLK_SRC 104
#define GCC_QUPV3_WRAP_1_M_AHB_CLK 105
#define GCC_QUPV3_WRAP_1_S_AHB_CLK 106
#define GCC_QUPV3_WRAP_2_IBI_2_AHB_CLK 107
#define GCC_QUPV3_WRAP_2_IBI_3_AHB_CLK 108
#define GCC_QUPV3_WRAP_2_M_AHB_CLK 109
#define GCC_QUPV3_WRAP_2_S_AHB_CLK 110
#define GCC_SDCC2_AHB_CLK 111
#define GCC_SDCC2_APPS_CLK 112
#define GCC_SDCC2_APPS_CLK_SRC 113
#define GCC_UFS_PHY_AHB_CLK 114
#define GCC_UFS_PHY_AXI_CLK 115
#define GCC_UFS_PHY_AXI_CLK_SRC 116
#define GCC_UFS_PHY_ICE_CORE_CLK 117
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 118
#define GCC_UFS_PHY_PHY_AUX_CLK 119
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 120
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 121
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 122
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 123
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 124
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 125
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 126
#define GCC_UFS_PHY_UNIPRO_CORE_CLK 127
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 128
#define GCC_USB30_PRIM_ATB_CLK 129
#define GCC_USB30_PRIM_MASTER_CLK 130
#define GCC_USB30_PRIM_MASTER_CLK_SRC 131
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 132
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 133
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 134
#define GCC_USB30_PRIM_SLEEP_CLK 135
#define GCC_USB3_PRIM_PHY_AUX_CLK 136
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 137
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 138
#define GCC_USB3_PRIM_PHY_PIPE_CLK 139
#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 140
#define GCC_VIDEO_AHB_CLK 141
#define GCC_VIDEO_AXI0_CLK 142
#define GCC_VIDEO_AXI1_CLK 143
#define GCC_VIDEO_XO_CLK 144
#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 145
#define GCC_UFS_PHY_AXI_HW_CTL_CLK 146
#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 147
#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 148
#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 149
/* GCC power domains */
#define GCC_PCIE_0_GDSC 0
#define GCC_PCIE_0_PHY_GDSC 1
#define GCC_UFS_MEM_PHY_GDSC 2
#define GCC_UFS_PHY_GDSC 3
#define GCC_USB30_PRIM_GDSC 4
#define GCC_USB3_PHY_GDSC 5
/* GCC resets */
#define GCC_CAMERA_BCR 0
#define GCC_DISPLAY_BCR 1
#define GCC_EVA_BCR 2
#define GCC_GPU_BCR 3
#define GCC_PCIE_0_BCR 4
#define GCC_PCIE_0_LINK_DOWN_BCR 5
#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 6
#define GCC_PCIE_0_PHY_BCR 7
#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 8
#define GCC_PCIE_PHY_BCR 9
#define GCC_PCIE_PHY_CFG_AHB_BCR 10
#define GCC_PCIE_PHY_COM_BCR 11
#define GCC_PCIE_RSCC_BCR 12
#define GCC_PDM_BCR 13
#define GCC_QUPV3_WRAPPER_1_BCR 14
#define GCC_QUPV3_WRAPPER_2_BCR 15
#define GCC_QUSB2PHY_PRIM_BCR 16
#define GCC_QUSB2PHY_SEC_BCR 17
#define GCC_SDCC2_BCR 18
#define GCC_UFS_PHY_BCR 19
#define GCC_USB30_PRIM_BCR 20
#define GCC_USB3_DP_PHY_PRIM_BCR 21
#define GCC_USB3_DP_PHY_SEC_BCR 22
#define GCC_USB3_PHY_PRIM_BCR 23
#define GCC_USB3_PHY_SEC_BCR 24
#define GCC_USB3PHY_PHY_PRIM_BCR 25
#define GCC_USB3PHY_PHY_SEC_BCR 26
#define GCC_VIDEO_BCR 27
#define GCC_VIDEO_AXI0_CLK_ARES 28
#define GCC_VIDEO_AXI1_CLK_ARES 29
#endif

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include/dt-bindings/clock/qcom,gpucc-kera.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_KERA_H
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_KERA_H
/* GPU_CC clocks */
#define GPU_CC_PLL0 0
#define GPU_CC_PLL1 1
#define GPU_CC_AHB_CLK 2
#define GPU_CC_CRC_AHB_CLK 3
#define GPU_CC_CX_ACCU_SHIFT_CLK 4
#define GPU_CC_CX_FF_CLK 5
#define GPU_CC_CX_GMU_CLK 6
#define GPU_CC_CXO_AON_CLK 7
#define GPU_CC_CXO_CLK 8
#define GPU_CC_DEMET_CLK 9
#define GPU_CC_DEMET_DIV_CLK_SRC 10
#define GPU_CC_FF_CLK_SRC 11
#define GPU_CC_FREQ_MEASURE_CLK 12
#define GPU_CC_GMU_CLK_SRC 13
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 14
#define GPU_CC_HUB_AON_CLK 15
#define GPU_CC_HUB_CLK_SRC 16
#define GPU_CC_HUB_CX_INT_CLK 17
#define GPU_CC_MEMNOC_GFX_CLK 18
#define GPU_CC_MND1X_0_GFX3D_CLK 19
#define GPU_CC_MND1X_1_GFX3D_CLK 20
#define GPU_CC_SLEEP_CLK 21
#define GPU_CC_XO_CLK_SRC 22
#define GPU_CC_XO_DIV_CLK_SRC 23
/* GPU_CC power domains */
#define GPU_CC_CX_GDSC 0
#define GPU_CC_GX_GDSC 1
/* GPU_CC resets */
#define GPU_CC_ACD_BCR 0
#define GPU_CC_CB_BCR 1
#define GPU_CC_CX_BCR 2
#define GPU_CC_FAST_HUB_BCR 3
#define GPU_CC_FF_BCR 4
#define GPU_CC_GFX3D_AON_BCR 5
#define GPU_CC_GMU_BCR 6
#define GPU_CC_GX_BCR 7
#define GPU_CC_RBCPR_BCR 8
#define GPU_CC_XO_BCR 9
#define GPU_CC_FREQUENCY_LIMITER_IRQ_CLEAR 10
#endif

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include/dt-bindings/clock/qcom,gpucc-monaco.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_MONACO_H
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_MONACO_H
/* GPU_CC clocks */
#define GPU_CC_PLL0 0
#define GPU_CC_AHB_CLK 1
#define GPU_CC_CRC_AHB_CLK 2
#define GPU_CC_CX_APB_CLK 3
#define GPU_CC_CX_GFX3D_CLK 4
#define GPU_CC_CX_GFX3D_SLV_CLK 5
#define GPU_CC_CX_GMU_CLK 6
#define GPU_CC_CX_SNOC_DVM_CLK 7
#define GPU_CC_CXO_AON_CLK 8
#define GPU_CC_CXO_AON_CLK_SRC 9
#define GPU_CC_CXO_CLK 10
#define GPU_CC_GMU_CLK_SRC 11
#define GPU_CC_GX_CXO_CLK 12
#define GPU_CC_GX_GFX3D_CLK 13
#define GPU_CC_GX_GFX3D_CLK_SRC 14
#define GPU_CC_SLEEP_CLK 15
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 16
#endif

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include/dt-bindings/clock/qcom,gpucc-parrot.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2021, 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_PARROT_H
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_PARROT_H
/* GPU_CC clocks */
#define GPU_CC_PLL0 0
#define GPU_CC_PLL1 1
#define GPU_CC_AHB_CLK 2
#define GPU_CC_CB_CLK 3
#define GPU_CC_CRC_AHB_CLK 4
#define GPU_CC_CX_FF_CLK 5
#define GPU_CC_CX_GMU_CLK 6
#define GPU_CC_CX_SNOC_DVM_CLK 7
#define GPU_CC_CXO_AON_CLK 8
#define GPU_CC_CXO_CLK 9
#define GPU_CC_DEMET_CLK 10
#define GPU_CC_DEMET_DIV_CLK_SRC 11
#define GPU_CC_FF_CLK_SRC 12
#define GPU_CC_FREQ_MEASURE_CLK 13
#define GPU_CC_GMU_CLK_SRC 14
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 15
#define GPU_CC_HUB_AHB_DIV_CLK_SRC 16
#define GPU_CC_HUB_AON_CLK 17
#define GPU_CC_HUB_CLK_SRC 18
#define GPU_CC_HUB_CX_INT_CLK 19
#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 20
#define GPU_CC_MEMNOC_GFX_CLK 21
#define GPU_CC_MND1X_0_GFX3D_CLK 22
#define GPU_CC_MND1X_1_GFX3D_CLK 23
#define GPU_CC_SLEEP_CLK 24
#define GPU_CC_XO_CLK_SRC 25
#define GPU_CC_XO_DIV_CLK_SRC 26
/* GPU_CC resets */
#define GPUCC_GPU_CC_ACD_BCR 0
#define GPUCC_GPU_CC_CB_BCR 1
#define GPUCC_GPU_CC_CX_BCR 2
#define GPUCC_GPU_CC_FAST_HUB_BCR 3
#define GPUCC_GPU_CC_FF_BCR 4
#define GPUCC_GPU_CC_GFX3D_AON_BCR 5
#define GPUCC_GPU_CC_GMU_BCR 6
#define GPUCC_GPU_CC_GX_BCR 7
#define GPUCC_GPU_CC_RBCPR_BCR 8
#define GPUCC_GPU_CC_XO_BCR 9
#define GPUCC_GPU_CC_FREQUENCY_LIMITER_IRQ_CLEAR 10
#endif

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include/dt-bindings/clock/qcom,gpucc-pineapple.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_PINEAPPLE_H
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_PINEAPPLE_H
/* GPU_CC clocks */
#define GPU_CC_AHB_CLK 0
#define GPU_CC_CRC_AHB_CLK 1
#define GPU_CC_CX_ACCU_SHIFT_CLK 2
#define GPU_CC_CX_FF_CLK 3
#define GPU_CC_CX_GMU_CLK 4
#define GPU_CC_CXO_AON_CLK 5
#define GPU_CC_CXO_CLK 6
#define GPU_CC_DEMET_CLK 7
#define GPU_CC_DPM_CLK 8
#define GPU_CC_FF_CLK_SRC 9
#define GPU_CC_FREQ_MEASURE_CLK 10
#define GPU_CC_GMU_CLK_SRC 11
#define GPU_CC_GX_ACCU_SHIFT_CLK 12
#define GPU_CC_GX_FF_CLK 13
#define GPU_CC_GX_GFX3D_CLK 14
#define GPU_CC_GX_GFX3D_RDVM_CLK 15
#define GPU_CC_GX_GMU_CLK 16
#define GPU_CC_GX_VSENSE_CLK 17
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 18
#define GPU_CC_HUB_AON_CLK 19
#define GPU_CC_HUB_CLK_SRC 20
#define GPU_CC_HUB_CX_INT_CLK 21
#define GPU_CC_HUB_DIV_CLK_SRC 22
#define GPU_CC_MEMNOC_GFX_CLK 23
#define GPU_CC_PLL0 24
#define GPU_CC_PLL1 25
#define GPU_CC_SLEEP_CLK 26
/* GPU_CC resets */
#define GPUCC_GPU_CC_ACD_BCR 0
#define GPUCC_GPU_CC_CX_BCR 1
#define GPUCC_GPU_CC_FAST_HUB_BCR 2
#define GPUCC_GPU_CC_FF_BCR 3
#define GPUCC_GPU_CC_GFX3D_AON_BCR 4
#define GPUCC_GPU_CC_GMU_BCR 5
#define GPUCC_GPU_CC_GX_BCR 6
#define GPUCC_GPU_CC_XO_BCR 7
#define GPUCC_GPU_CC_FREQUENCY_LIMITER_IRQ_CLEAR 8
#endif

53
include/dt-bindings/clock/qcom,gpucc-sun.h Normal file
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@@ -0,0 +1,53 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SUN_H
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SUN_H
/* GPU_CC clocks */
#define GPU_CC_AHB_CLK 0
#define GPU_CC_CB_CLK 1
#define GPU_CC_CX_ACCU_SHIFT_CLK 2
#define GPU_CC_CX_FF_CLK 3
#define GPU_CC_CX_GMU_CLK 4
#define GPU_CC_CXO_AON_CLK 5
#define GPU_CC_CXO_CLK 6
#define GPU_CC_DEMET_CLK 7
#define GPU_CC_DPM_CLK 8
#define GPU_CC_FF_CLK_SRC 9
#define GPU_CC_FREQ_MEASURE_CLK 10
#define GPU_CC_GMU_CLK_SRC 11
#define GPU_CC_GX_ACCU_SHIFT_CLK 12
#define GPU_CC_GX_ACD_AHB_FF_CLK 13
#define GPU_CC_GX_AHB_FF_CLK 14
#define GPU_CC_GX_GMU_CLK 15
#define GPU_CC_GX_RCG_AHB_FF_CLK 16
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 17
#define GPU_CC_HUB_AON_CLK 18
#define GPU_CC_HUB_CLK_SRC 19
#define GPU_CC_HUB_CX_INT_CLK 20
#define GPU_CC_HUB_DIV_CLK_SRC 21
#define GPU_CC_MEMNOC_GFX_CLK 22
#define GPU_CC_PLL0 23
#define GPU_CC_PLL0_OUT_EVEN 24
#define GPU_CC_RSCC_HUB_AON_CLK 25
#define GPU_CC_RSCC_XO_AON_CLK 26
#define GPU_CC_SLEEP_CLK 27
/* GPU_CC power domains */
#define GPU_CC_CX_GDSC 0
#define GPU_CC_CX_SMMU_GDSC 1
#define GPU_CC_CX_GMU_GDSC 2
/* GPU_CC resets */
#define GPUCC_GPU_CC_CB_BCR 0
#define GPUCC_GPU_CC_CX_BCR 1
#define GPUCC_GPU_CC_FAST_HUB_BCR 2
#define GPUCC_GPU_CC_FF_BCR 3
#define GPUCC_GPU_CC_GMU_BCR 4
#define GPUCC_GPU_CC_GX_BCR 5
#define GPUCC_GPU_CC_XO_BCR 6
#endif

49
include/dt-bindings/clock/qcom,gpucc-tuna.h Normal file
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@@ -0,0 +1,49 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_TUNA_H
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_TUNA_H
/* GPU_CC clocks */
#define GPU_CC_PLL0 0
#define GPU_CC_PLL0_OUT_EVEN 1
#define GPU_CC_AHB_CLK 2
#define GPU_CC_CB_CLK 3
#define GPU_CC_CX_ACCU_SHIFT_CLK 4
#define GPU_CC_CX_GMU_CLK 5
#define GPU_CC_CXO_AON_CLK 6
#define GPU_CC_CXO_CLK 7
#define GPU_CC_DEMET_CLK 8
#define GPU_CC_DPM_CLK 9
#define GPU_CC_FF_CLK_SRC 10
#define GPU_CC_FREQ_MEASURE_CLK 11
#define GPU_CC_GMU_CLK_SRC 12
#define GPU_CC_GX_ACCU_SHIFT_CLK 13
#define GPU_CC_GX_GMU_CLK 14
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 15
#define GPU_CC_HUB_AON_CLK 16
#define GPU_CC_HUB_CLK_SRC 17
#define GPU_CC_HUB_CX_INT_CLK 18
#define GPU_CC_HUB_DIV_CLK_SRC 19
#define GPU_CC_MEMNOC_GFX_CLK 20
#define GPU_CC_RSCC_HUB_AON_CLK 21
#define GPU_CC_RSCC_XO_AON_CLK 22
#define GPU_CC_SLEEP_CLK 23
/* GPU_CC power domains */
#define GPU_CC_CX_GDSC 0
#define GX_CLKCTL_GX_GDSC 1
/* GPU_CC resets */
#define GPU_CC_CB_BCR 0
#define GPU_CC_CX_BCR 1
#define GPU_CC_FAST_HUB_BCR 2
#define GPU_CC_FF_BCR 3
#define GPU_CC_GMU_BCR 4
#define GPU_CC_GX_BCR 5
#define GPU_CC_RBCPR_BCR 6
#define GPU_CC_XO_BCR 7
#endif

12
include/dt-bindings/clock/qcom,gxclkctl-sun.h Normal file
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@@ -0,0 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GX_CLKCTL_SUN_H
#define _DT_BINDINGS_CLK_QCOM_GX_CLKCTL_SUN_H
/* GX_CLKCTL power domains */
#define GX_CLKCTL_GX_GDSC 0
#endif

2
include/dt-bindings/clock/qcom,rpmcc.h
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@@ -170,5 +170,7 @@
#define RPM_SMD_BIMC_FREQ_LOG 124
#define RPM_SMD_LN_BB_CLK_PIN 125
#define RPM_SMD_LN_BB_A_CLK_PIN 126
#define RPM_SMD_RF_CLK5 127
#define RPM_SMD_RF_CLK5_A 128
#endif

4
include/dt-bindings/clock/qcom,rpmh.h
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@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved. */
/* Copyright (c) 2018, 2020 The Linux Foundation. All rights reserved. */
#ifndef _DT_BINDINGS_CLK_MSM_RPMH_H
@@ -33,5 +33,7 @@
#define RPMH_HWKM_CLK 24
#define RPMH_QLINK_CLK 25
#define RPMH_QLINK_CLK_A 26
#define RPMH_CXO_PAD_CLK 27
#define RPMH_CXO_PAD_CLK_A 28
#endif

12
include/dt-bindings/clock/qcom,sdx75-gcc.h
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@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SDX75_H
@@ -150,6 +150,12 @@
#define GCC_USB3_PRIM_CLKREF_EN 140
#define GCC_USB_PHY_CFG_AHB2PHY_CLK 141
#define GCC_XO_PCIE_LINK_CLK 142
#define GCC_MVM_AHB_CLK 143
#define GCC_MVM_MASTER_AXI_CLK 144
#define GCC_MVMSS_NTS_CLK 145
#define GCC_SYS_NOC_MVMSS_CLK 146
#define GCC_TLMM_125_CLK_SRC 147
#define GCC_TLMM_125_CLK 148
/* GCC power domains */
#define GCC_EMAC0_GDSC 0
@@ -189,5 +195,9 @@
#define GCC_USB3PHY_PHY_BCR 22
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 23
#define GCC_EMAC0_RGMII_CLK_ARES 24
#define GCC_MVMSS_BCR 25
#define GCC_PDM_BCR 26
#define GCC_QUPV3_WRAPPER_0_BCR 27
#define GCC_SDCC2_BCR 28
#endif

106
include/dt-bindings/clock/qcom,sm4450-camcc.h Normal file
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@@ -0,0 +1,106 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM4450_H
#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM4450_H
/* CAM_CC clocks */
#define CAM_CC_BPS_AHB_CLK 0
#define CAM_CC_BPS_AREG_CLK 1
#define CAM_CC_BPS_CLK 2
#define CAM_CC_BPS_CLK_SRC 3
#define CAM_CC_CAMNOC_ATB_CLK 4
#define CAM_CC_CAMNOC_AXI_CLK 5
#define CAM_CC_CAMNOC_AXI_CLK_SRC 6
#define CAM_CC_CAMNOC_AXI_HF_CLK 7
#define CAM_CC_CAMNOC_AXI_SF_CLK 8
#define CAM_CC_CCI_0_CLK 9
#define CAM_CC_CCI_0_CLK_SRC 10
#define CAM_CC_CCI_1_CLK 11
#define CAM_CC_CCI_1_CLK_SRC 12
#define CAM_CC_CORE_AHB_CLK 13
#define CAM_CC_CPAS_AHB_CLK 14
#define CAM_CC_CPHY_RX_CLK_SRC 15
#define CAM_CC_CRE_AHB_CLK 16
#define CAM_CC_CRE_CLK 17
#define CAM_CC_CRE_CLK_SRC 18
#define CAM_CC_CSI0PHYTIMER_CLK 19
#define CAM_CC_CSI0PHYTIMER_CLK_SRC 20
#define CAM_CC_CSI1PHYTIMER_CLK 21
#define CAM_CC_CSI1PHYTIMER_CLK_SRC 22
#define CAM_CC_CSI2PHYTIMER_CLK 23
#define CAM_CC_CSI2PHYTIMER_CLK_SRC 24
#define CAM_CC_CSIPHY0_CLK 25
#define CAM_CC_CSIPHY1_CLK 26
#define CAM_CC_CSIPHY2_CLK 27
#define CAM_CC_FAST_AHB_CLK_SRC 28
#define CAM_CC_ICP_ATB_CLK 29
#define CAM_CC_ICP_CLK 30
#define CAM_CC_ICP_CLK_SRC 31
#define CAM_CC_ICP_CTI_CLK 32
#define CAM_CC_ICP_TS_CLK 33
#define CAM_CC_MCLK0_CLK 34
#define CAM_CC_MCLK0_CLK_SRC 35
#define CAM_CC_MCLK1_CLK 36
#define CAM_CC_MCLK1_CLK_SRC 37
#define CAM_CC_MCLK2_CLK 38
#define CAM_CC_MCLK2_CLK_SRC 39
#define CAM_CC_MCLK3_CLK 40
#define CAM_CC_MCLK3_CLK_SRC 41
#define CAM_CC_OPE_0_AHB_CLK 42
#define CAM_CC_OPE_0_AREG_CLK 43
#define CAM_CC_OPE_0_CLK 44
#define CAM_CC_OPE_0_CLK_SRC 45
#define CAM_CC_PLL0 46
#define CAM_CC_PLL0_OUT_EVEN 47
#define CAM_CC_PLL0_OUT_ODD 48
#define CAM_CC_PLL1 49
#define CAM_CC_PLL1_OUT_EVEN 50
#define CAM_CC_PLL2 51
#define CAM_CC_PLL2_OUT_EVEN 52
#define CAM_CC_PLL3 53
#define CAM_CC_PLL3_OUT_EVEN 54
#define CAM_CC_PLL4 55
#define CAM_CC_PLL4_OUT_EVEN 56
#define CAM_CC_SLOW_AHB_CLK_SRC 57
#define CAM_CC_SOC_AHB_CLK 58
#define CAM_CC_SYS_TMR_CLK 59
#define CAM_CC_TFE_0_AHB_CLK 60
#define CAM_CC_TFE_0_CLK 61
#define CAM_CC_TFE_0_CLK_SRC 62
#define CAM_CC_TFE_0_CPHY_RX_CLK 63
#define CAM_CC_TFE_0_CSID_CLK 64
#define CAM_CC_TFE_0_CSID_CLK_SRC 65
#define CAM_CC_TFE_1_AHB_CLK 66
#define CAM_CC_TFE_1_CLK 67
#define CAM_CC_TFE_1_CLK_SRC 68
#define CAM_CC_TFE_1_CPHY_RX_CLK 69
#define CAM_CC_TFE_1_CSID_CLK 70
#define CAM_CC_TFE_1_CSID_CLK_SRC 71
/* CAM_CC power domains */
#define CAM_CC_CAMSS_TOP_GDSC 0
/* CAM_CC resets */
#define CAM_CC_BPS_BCR 0
#define CAM_CC_CAMNOC_BCR 1
#define CAM_CC_CAMSS_TOP_BCR 2
#define CAM_CC_CCI_0_BCR 3
#define CAM_CC_CCI_1_BCR 4
#define CAM_CC_CPAS_BCR 5
#define CAM_CC_CRE_BCR 6
#define CAM_CC_CSI0PHY_BCR 7
#define CAM_CC_CSI1PHY_BCR 8
#define CAM_CC_CSI2PHY_BCR 9
#define CAM_CC_ICP_BCR 10
#define CAM_CC_MCLK0_BCR 11
#define CAM_CC_MCLK1_BCR 12
#define CAM_CC_MCLK2_BCR 13
#define CAM_CC_MCLK3_BCR 14
#define CAM_CC_OPE_0_BCR 15
#define CAM_CC_TFE_0_BCR 16
#define CAM_CC_TFE_1_BCR 17
#endif

51
include/dt-bindings/clock/qcom,sm4450-dispcc.h Normal file
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@@ -0,0 +1,51 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM4450_H
#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM4450_H
/* DISP_CC clocks */
#define DISP_CC_MDSS_AHB1_CLK 0
#define DISP_CC_MDSS_AHB_CLK 1
#define DISP_CC_MDSS_AHB_CLK_SRC 2
#define DISP_CC_MDSS_BYTE0_CLK 3
#define DISP_CC_MDSS_BYTE0_CLK_SRC 4
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5
#define DISP_CC_MDSS_BYTE0_INTF_CLK 6
#define DISP_CC_MDSS_ESC0_CLK 7
#define DISP_CC_MDSS_ESC0_CLK_SRC 8
#define DISP_CC_MDSS_MDP1_CLK 9
#define DISP_CC_MDSS_MDP_CLK 10
#define DISP_CC_MDSS_MDP_CLK_SRC 11
#define DISP_CC_MDSS_MDP_LUT1_CLK 12
#define DISP_CC_MDSS_MDP_LUT_CLK 13
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 14
#define DISP_CC_MDSS_PCLK0_CLK 15
#define DISP_CC_MDSS_PCLK0_CLK_SRC 16
#define DISP_CC_MDSS_ROT1_CLK 17
#define DISP_CC_MDSS_ROT_CLK 18
#define DISP_CC_MDSS_ROT_CLK_SRC 19
#define DISP_CC_MDSS_RSCC_AHB_CLK 20
#define DISP_CC_MDSS_RSCC_VSYNC_CLK 21
#define DISP_CC_MDSS_VSYNC1_CLK 22
#define DISP_CC_MDSS_VSYNC_CLK 23
#define DISP_CC_MDSS_VSYNC_CLK_SRC 24
#define DISP_CC_PLL0 25
#define DISP_CC_PLL1 26
#define DISP_CC_SLEEP_CLK 27
#define DISP_CC_SLEEP_CLK_SRC 28
#define DISP_CC_XO_CLK 29
#define DISP_CC_XO_CLK_SRC 30
/* DISP_CC power domains */
#define DISP_CC_MDSS_CORE_GDSC 0
#define DISP_CC_MDSS_CORE_INT2_GDSC 1
/* DISP_CC resets */
#define DISP_CC_MDSS_CORE_BCR 0
#define DISP_CC_MDSS_CORE_INT2_BCR 1
#define DISP_CC_MDSS_RSCC_BCR 2
#endif

197
include/dt-bindings/clock/qcom,sm4450-gcc.h Normal file
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@@ -0,0 +1,197 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM4450_H
#define _DT_BINDINGS_CLK_QCOM_GCC_SM4450_H
/* GCC clocks */
#define GCC_AGGRE_NOC_PCIE_0_AXI_CLK 0
#define GCC_AGGRE_UFS_PHY_AXI_CLK 1
#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 2
#define GCC_AGGRE_USB3_PRIM_AXI_CLK 3
#define GCC_BOOT_ROM_AHB_CLK 4
#define GCC_CAMERA_AHB_CLK 5
#define GCC_CAMERA_HF_AXI_CLK 6
#define GCC_CAMERA_SF_AXI_CLK 7
#define GCC_CAMERA_SLEEP_CLK 8
#define GCC_CAMERA_XO_CLK 9
#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 10
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 11
#define GCC_DDRSS_GPU_AXI_CLK 12
#define GCC_DDRSS_PCIE_SF_TBU_CLK 13
#define GCC_DISP_AHB_CLK 14
#define GCC_DISP_HF_AXI_CLK 15
#define GCC_DISP_XO_CLK 16
#define GCC_EUSB3_0_CLKREF_EN 17
#define GCC_GP1_CLK 18
#define GCC_GP1_CLK_SRC 19
#define GCC_GP2_CLK 20
#define GCC_GP2_CLK_SRC 21
#define GCC_GP3_CLK 22
#define GCC_GP3_CLK_SRC 23
#define GCC_GPLL0 24
#define GCC_GPLL0_OUT_EVEN 25
#define GCC_GPLL0_OUT_ODD 26
#define GCC_GPLL1 27
#define GCC_GPLL3 28
#define GCC_GPLL4 29
#define GCC_GPLL9 30
#define GCC_GPLL10 31
#define GCC_GPU_CFG_AHB_CLK 32
#define GCC_GPU_GPLL0_CLK_SRC 33
#define GCC_GPU_GPLL0_DIV_CLK_SRC 34
#define GCC_GPU_MEMNOC_GFX_CLK 35
#define GCC_GPU_SNOC_DVM_GFX_CLK 36
#define GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK 37
#define GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK 38
#define GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK 39
#define GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK 40
#define GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_CLK 41
#define GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_CLK 42
#define GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_CLK 43
#define GCC_HLOS1_VOTE_MMU_TCU_CLK 44
#define GCC_PCIE_0_AUX_CLK 45
#define GCC_PCIE_0_AUX_CLK_SRC 46
#define GCC_PCIE_0_CFG_AHB_CLK 47
#define GCC_PCIE_0_CLKREF_EN 48
#define GCC_PCIE_0_MSTR_AXI_CLK 49
#define GCC_PCIE_0_PHY_RCHNG_CLK 50
#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 51
#define GCC_PCIE_0_PIPE_CLK 52
#define GCC_PCIE_0_PIPE_CLK_SRC 53
#define GCC_PCIE_0_PIPE_DIV2_CLK 54
#define GCC_PCIE_0_PIPE_DIV2_CLK_SRC 55
#define GCC_PCIE_0_SLV_AXI_CLK 56
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 57
#define GCC_PDM2_CLK 58
#define GCC_PDM2_CLK_SRC 59
#define GCC_PDM_AHB_CLK 60
#define GCC_PDM_XO4_CLK 61
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 62
#define GCC_QMIP_CAMERA_RT_AHB_CLK 63
#define GCC_QMIP_DISP_AHB_CLK 64
#define GCC_QMIP_GPU_AHB_CLK 65
#define GCC_QMIP_PCIE_AHB_CLK 66
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 67
#define GCC_QUPV3_WRAP0_CORE_2X_CLK 68
#define GCC_QUPV3_WRAP0_CORE_CLK 69
#define GCC_QUPV3_WRAP0_S0_CLK 70
#define GCC_QUPV3_WRAP0_S0_CLK_SRC 71
#define GCC_QUPV3_WRAP0_S1_CLK 72
#define GCC_QUPV3_WRAP0_S1_CLK_SRC 73
#define GCC_QUPV3_WRAP0_S2_CLK 74
#define GCC_QUPV3_WRAP0_S2_CLK_SRC 75
#define GCC_QUPV3_WRAP0_S3_CLK 76
#define GCC_QUPV3_WRAP0_S3_CLK_SRC 77
#define GCC_QUPV3_WRAP0_S4_CLK 78
#define GCC_QUPV3_WRAP0_S4_CLK_SRC 79
#define GCC_QUPV3_WRAP1_CORE_2X_CLK 80
#define GCC_QUPV3_WRAP1_CORE_CLK 81
#define GCC_QUPV3_WRAP1_S0_CLK 82
#define GCC_QUPV3_WRAP1_S0_CLK_SRC 83
#define GCC_QUPV3_WRAP1_S1_CLK 84
#define GCC_QUPV3_WRAP1_S1_CLK_SRC 85
#define GCC_QUPV3_WRAP1_S2_CLK 86
#define GCC_QUPV3_WRAP1_S2_CLK_SRC 87
#define GCC_QUPV3_WRAP1_S3_CLK 88
#define GCC_QUPV3_WRAP1_S3_CLK_SRC 89
#define GCC_QUPV3_WRAP1_S4_CLK 90
#define GCC_QUPV3_WRAP1_S4_CLK_SRC 91
#define GCC_QUPV3_WRAP_0_M_AHB_CLK 92
#define GCC_QUPV3_WRAP_0_S_AHB_CLK 93
#define GCC_QUPV3_WRAP_1_M_AHB_CLK 94
#define GCC_QUPV3_WRAP_1_S_AHB_CLK 95
#define GCC_SDCC1_AHB_CLK 96
#define GCC_SDCC1_APPS_CLK 97
#define GCC_SDCC1_APPS_CLK_SRC 98
#define GCC_SDCC1_ICE_CORE_CLK 99
#define GCC_SDCC1_ICE_CORE_CLK_SRC 100
#define GCC_SDCC2_AHB_CLK 101
#define GCC_SDCC2_APPS_CLK 102
#define GCC_SDCC2_APPS_CLK_SRC 103
#define GCC_UFS_0_CLKREF_EN 104
#define GCC_UFS_PAD_CLKREF_EN 105
#define GCC_UFS_PHY_AHB_CLK 106
#define GCC_UFS_PHY_AXI_CLK 107
#define GCC_UFS_PHY_AXI_CLK_SRC 108
#define GCC_UFS_PHY_AXI_HW_CTL_CLK 109
#define GCC_UFS_PHY_ICE_CORE_CLK 110
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 111
#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 112
#define GCC_UFS_PHY_PHY_AUX_CLK 113
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 114
#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 115
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 116
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 117
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 118
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 119
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 120
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 121
#define GCC_UFS_PHY_UNIPRO_CORE_CLK 122
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 123
#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 124
#define GCC_USB30_PRIM_MASTER_CLK 125
#define GCC_USB30_PRIM_MASTER_CLK_SRC 126
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 127
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 128
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 129
#define GCC_USB30_PRIM_SLEEP_CLK 130
#define GCC_USB3_0_CLKREF_EN 131
#define GCC_USB3_PRIM_PHY_AUX_CLK 132
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 133
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 134
#define GCC_USB3_PRIM_PHY_PIPE_CLK 135
#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 136
#define GCC_VCODEC0_AXI_CLK 137
#define GCC_VENUS_CTL_AXI_CLK 138
#define GCC_VIDEO_AHB_CLK 139
#define GCC_VIDEO_THROTTLE_CORE_CLK 140
#define GCC_VIDEO_VCODEC0_SYS_CLK 141
#define GCC_VIDEO_VENUS_CLK_SRC 142
#define GCC_VIDEO_VENUS_CTL_CLK 143
#define GCC_VIDEO_XO_CLK 144
/* GCC power domains */
#define GCC_PCIE_0_GDSC 0
#define GCC_UFS_PHY_GDSC 1
#define GCC_USB30_PRIM_GDSC 2
#define GCC_VCODEC0_GDSC 3
#define GCC_VENUS_GDSC 4
/* GCC resets */
#define GCC_CAMERA_BCR 0
#define GCC_DISPLAY_BCR 1
#define GCC_GPU_BCR 2
#define GCC_PCIE_0_BCR 3
#define GCC_PCIE_0_LINK_DOWN_BCR 4
#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5
#define GCC_PCIE_0_PHY_BCR 6
#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7
#define GCC_PCIE_PHY_BCR 8
#define GCC_PCIE_PHY_CFG_AHB_BCR 9
#define GCC_PCIE_PHY_COM_BCR 10
#define GCC_PDM_BCR 11
#define GCC_QUPV3_WRAPPER_0_BCR 12
#define GCC_QUPV3_WRAPPER_1_BCR 13
#define GCC_QUSB2PHY_PRIM_BCR 14
#define GCC_QUSB2PHY_SEC_BCR 15
#define GCC_SDCC1_BCR 16
#define GCC_SDCC2_BCR 17
#define GCC_UFS_PHY_BCR 18
#define GCC_USB30_PRIM_BCR 19
#define GCC_USB3_DP_PHY_PRIM_BCR 20
#define GCC_USB3_DP_PHY_SEC_BCR 21
#define GCC_USB3_PHY_PRIM_BCR 22
#define GCC_USB3_PHY_SEC_BCR 23
#define GCC_USB3PHY_PHY_PRIM_BCR 24
#define GCC_USB3PHY_PHY_SEC_BCR 25
#define GCC_VCODEC0_BCR 26
#define GCC_VENUS_BCR 27
#define GCC_VIDEO_BCR 28
#define GCC_VIDEO_VENUS_BCR 29
#define GCC_VENUS_CTL_AXI_CLK_ARES 30
#define GCC_VIDEO_VENUS_CTL_CLK_ARES 31
#endif

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include/dt-bindings/clock/qcom,sm4450-gpucc.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM4450_H
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM4450_H
/* GPU_CC clocks */
#define GPU_CC_AHB_CLK 0
#define GPU_CC_CB_CLK 1
#define GPU_CC_CRC_AHB_CLK 2
#define GPU_CC_CX_FF_CLK 3
#define GPU_CC_CX_GFX3D_CLK 4
#define GPU_CC_CX_GFX3D_SLV_CLK 5
#define GPU_CC_CX_GMU_CLK 6
#define GPU_CC_CX_SNOC_DVM_CLK 7
#define GPU_CC_CXO_AON_CLK 8
#define GPU_CC_CXO_CLK 9
#define GPU_CC_DEMET_CLK 10
#define GPU_CC_DEMET_DIV_CLK_SRC 11
#define GPU_CC_FF_CLK_SRC 12
#define GPU_CC_FREQ_MEASURE_CLK 13
#define GPU_CC_GMU_CLK_SRC 14
#define GPU_CC_GX_CXO_CLK 15
#define GPU_CC_GX_FF_CLK 16
#define GPU_CC_GX_GFX3D_CLK 17
#define GPU_CC_GX_GFX3D_CLK_SRC 18
#define GPU_CC_GX_GFX3D_RDVM_CLK 19
#define GPU_CC_GX_GMU_CLK 20
#define GPU_CC_GX_VSENSE_CLK 21
#define GPU_CC_HUB_AHB_DIV_CLK_SRC 22
#define GPU_CC_HUB_AON_CLK 23
#define GPU_CC_HUB_CLK_SRC 24
#define GPU_CC_HUB_CX_INT_CLK 25
#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 26
#define GPU_CC_MEMNOC_GFX_CLK 27
#define GPU_CC_MND1X_0_GFX3D_CLK 28
#define GPU_CC_PLL0 29
#define GPU_CC_PLL1 30
#define GPU_CC_SLEEP_CLK 31
#define GPU_CC_XO_CLK_SRC 32
#define GPU_CC_XO_DIV_CLK_SRC 33
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 34
/* GPU_CC power domains */
#define GPU_CC_CX_GDSC 0
#define GPU_CC_GX_GDSC 1
/* GPU_CC resets */
#define GPU_CC_ACD_BCR 0
#define GPU_CC_CB_BCR 1
#define GPU_CC_CX_BCR 2
#define GPU_CC_FAST_HUB_BCR 3
#define GPU_CC_FF_BCR 4
#define GPU_CC_GFX3D_AON_BCR 5
#define GPU_CC_GMU_BCR 6
#define GPU_CC_GX_BCR 7
#define GPU_CC_XO_BCR 8
#define GPU_CC_GX_ACD_IROOT_BCR 9
#define GPU_CC_RBCPR_BCR 10
#define GPUCC_GPU_CC_FREQUENCY_LIMITER_IRQ_CLEAR 11
#endif

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include/dt-bindings/clock/qcom,tcsrcc-pineapple.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_PINEAPPLE_H
#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_PINEAPPLE_H
/* TCSR_CC clocks */
#define TCSR_PCIE_0_CLKREF_EN 0
#define TCSR_PCIE_1_CLKREF_EN 1
#define TCSR_UFS_CLKREF_EN 2
#define TCSR_UFS_PAD_CLKREF_EN 3
#define TCSR_USB2_CLKREF_EN 4
#define TCSR_USB3_CLKREF_EN 5
#define TCSR_PCIE_2L_CLKREF_EN 0
#endif

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include/dt-bindings/clock/qcom,tcsrcc-sun.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2023, 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_SUN_H
#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_SUN_H
/* TCSR_CC clocks */
#define TCSR_PCIE_0_CLKREF_EN 0
#define TCSR_UFS_CLKREF_EN 1
#define TCSR_USB2_CLKREF_EN 2
#define TCSR_USB3_CLKREF_EN 3
#define TCSR_PCIE_1_CLKREF_EN 4
#endif

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include/dt-bindings/clock/qcom,videocc-parrot.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2021, 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_PARROT_H
#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_PARROT_H
/* VIDEO_CC clocks */
#define VIDEO_PLL0 0
#define VIDEO_CC_IRIS_AHB_CLK 1
#define VIDEO_CC_IRIS_CLK_SRC 2
#define VIDEO_CC_MVS0_AXI_CLK 3
#define VIDEO_CC_MVS0_CORE_CLK 4
#define VIDEO_CC_MVSC_CORE_CLK 5
#define VIDEO_CC_MVSC_CTL_AXI_CLK 6
#define VIDEO_CC_SLEEP_CLK 7
#define VIDEO_CC_SLEEP_CLK_SRC 8
#define VIDEO_CC_TRIG_CLK 9
#define VIDEO_CC_VENUS_AHB_CLK 10
#define VIDEO_CC_XO_CLK 11
#define VIDEO_CC_XO_CLK_SRC 12
/* VIDEO_CC resets */
#define VCODEC_VIDEO_CC_INTERFACE_AHB_BCR 0
#define VCODEC_VIDEO_CC_INTERFACE_BCR 1
#define VCODEC_VIDEO_CC_MVS0_BCR 2
#define VCODEC_VIDEO_CC_MVSC_BCR 3
#endif

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include/dt-bindings/clock/qcom,videocc-pineapple.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_PINEAPPLE_H
#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_PINEAPPLE_H
/* VIDEO_CC clocks */
#define VIDEO_CC_AHB_CLK 0
#define VIDEO_CC_AHB_CLK_SRC 1
#define VIDEO_CC_MVS0_CLK 2
#define VIDEO_CC_MVS0_CLK_SRC 3
#define VIDEO_CC_MVS0_DIV_CLK_SRC 4
#define VIDEO_CC_MVS0_SHIFT_CLK 5
#define VIDEO_CC_MVS0C_CLK 6
#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 7
#define VIDEO_CC_MVS0C_SHIFT_CLK 8
#define VIDEO_CC_MVS1_CLK 9
#define VIDEO_CC_MVS1_CLK_SRC 10
#define VIDEO_CC_MVS1_DIV_CLK_SRC 11
#define VIDEO_CC_MVS1_SHIFT_CLK 12
#define VIDEO_CC_MVS1C_CLK 13
#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 14
#define VIDEO_CC_MVS1C_SHIFT_CLK 15
#define VIDEO_CC_PLL0 16
#define VIDEO_CC_PLL1 17
#define VIDEO_CC_SLEEP_CLK 18
#define VIDEO_CC_SLEEP_CLK_SRC 19
#define VIDEO_CC_XO_CLK 20
#define VIDEO_CC_XO_CLK_SRC 21
/* VIDEO_CC resets */
#define VCODEC_VIDEO_CC_INTERFACE_BCR 0
#define VCODEC_VIDEO_CC_MVS0_BCR 1
#define VIDEO_CC_MVS0C_CLK_ARES 2
#define VCODEC_VIDEO_CC_MVS0C_BCR 3
#define VCODEC_VIDEO_CC_MVS1_BCR 4
#define VIDEO_CC_MVS1C_CLK_ARES 5
#define VCODEC_VIDEO_CC_MVS1C_BCR 6
#define VIDEO_CC_XO_CLK_ARES 7
#endif

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include/dt-bindings/clock/qcom,videocc-sun.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SUN_H
#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SUN_H
/* VIDEO_CC clocks */
#define VIDEO_CC_AHB_CLK 0
#define VIDEO_CC_AHB_CLK_SRC 1
#define VIDEO_CC_MVS0_CLK 2
#define VIDEO_CC_MVS0_CLK_SRC 3
#define VIDEO_CC_MVS0_DIV_CLK_SRC 4
#define VIDEO_CC_MVS0_FREERUN_CLK 5
#define VIDEO_CC_MVS0_SHIFT_CLK 6
#define VIDEO_CC_MVS0C_CLK 7
#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 8
#define VIDEO_CC_MVS0C_FREERUN_CLK 9
#define VIDEO_CC_MVS0C_SHIFT_CLK 10
#define VIDEO_CC_PLL0 11
#define VIDEO_CC_SLEEP_CLK 12
#define VIDEO_CC_SLEEP_CLK_SRC 13
#define VIDEO_CC_XO_CLK 14
#define VIDEO_CC_XO_CLK_SRC 15
/* VIDEO_CC power domains */
#define VIDEO_CC_MVS0_GDSC 0
#define VIDEO_CC_MVS0C_GDSC 1
/* VIDEO_CC resets */
#define VIDEO_CC_INTERFACE_BCR 0
#define VIDEO_CC_MVS0_BCR 1
#define VIDEO_CC_MVS0_FREERUN_CLK_ARES 2
#define VIDEO_CC_MVS0C_CLK_ARES 3
#define VIDEO_CC_MVS0C_BCR 4
#define VIDEO_CC_MVS0C_FREERUN_CLK_ARES 5
#define VIDEO_CC_XO_CLK_ARES 6
#define IRIS_VCODEC_VIDEO_CC_INTERFACE_BCR VIDEO_CC_INTERFACE_BCR
#define IRIS_VCODEC_VIDEO_CC_MVS0_BCR VIDEO_CC_MVS0_BCR
#define IRIS_VCODEC_VIDEO_CC_MVS0C_BCR VIDEO_CC_MVS0C_BCR
#endif

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include/dt-bindings/clock/qcom,videocc-tuna.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_TUNA_H
#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_TUNA_H
/* VIDEO_CC clocks */
#define VIDEO_CC_PLL0 0
#define VIDEO_CC_AHB_CLK 1
#define VIDEO_CC_AHB_CLK_SRC 2
#define VIDEO_CC_MVS0_CLK 3
#define VIDEO_CC_MVS0_CLK_SRC 4
#define VIDEO_CC_MVS0_DIV_CLK_SRC 5
#define VIDEO_CC_MVS0_SHIFT_CLK 6
#define VIDEO_CC_MVS0C_CLK 7
#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 8
#define VIDEO_CC_MVS0C_SHIFT_CLK 9
#define VIDEO_CC_SLEEP_CLK 10
#define VIDEO_CC_SLEEP_CLK_SRC 11
#define VIDEO_CC_XO_CLK 12
#define VIDEO_CC_XO_CLK_SRC 13
/* VIDEO_CC power domains */
#define VIDEO_CC_MVS0_GDSC 0
#define VIDEO_CC_MVS0C_GDSC 1
/* VIDEO_CC resets */
#define VIDEO_CC_INTERFACE_BCR 0
#define VIDEO_CC_MVS0_BCR 1
#define VIDEO_CC_MVS0C_BCR 2
#define VIDEO_CC_MVS0_CLK_ARES 3
#define VIDEO_CC_MVS0C_CLK_ARES 4
#define VIDEO_CC_XO_CLK_ARES 5
#endif

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include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm5100.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2021 The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM5100_H
#define _DT_BINDINGS_QCOM_SPMI_VADC_PM5100_H
#ifndef PM5100_SID
#define PM5100_SID 0
#endif
/* ADC channels for PM5100_ADC for PMIC5 Gen3 */
#define PM5100_ADC5_GEN3_OFFSET_REF (PM5100_SID << 8 | 0x0)
#define PM5100_ADC5_GEN3_1P25VREF (PM5100_SID << 8 | 0x01)
#define PM5100_ADC5_GEN3_VREF_VADC (PM5100_SID << 8 | 0x02)
#define PM5100_ADC5_GEN3_DIE_TEMP (PM5100_SID << 8 | 0x03)
#define PM5100_ADC5_GEN3_AMUX1_THM (PM5100_SID << 8 | 0x04)
#define PM5100_ADC5_GEN3_BAT_ID (PM5100_SID << 8 | 0x05)
#define PM5100_ADC5_GEN3_BATT_THM (PM5100_SID << 8 | 0x06)
#define PM5100_ADC5_GEN3_AMUX4_THM (PM5100_SID << 8 | 0x07)
#define PM5100_ADC5_GEN3_AMUX5_THM (PM5100_SID << 8 | 0x08)
#define PM5100_ADC5_GEN3_AMUX6_THM (PM5100_SID << 8 | 0x09)
#define PM5100_ADC5_GEN3_AMUX1_GPIO10 (PM5100_SID << 8 | 0x0a)
#define PM5100_ADC5_GEN3_AMUX2_GPIO11 (PM5100_SID << 8 | 0x0b)
#define PM5100_ADC5_GEN3_AMUX3_GPIO (PM5100_SID << 8 | 0x0c)
#define PM5100_ADC5_GEN3_AMUX4_GPIO (PM5100_SID << 8 | 0x0d)
#define PM5100_ADC5_GEN3_CHG_TEMP (PM5100_SID << 8 | 0x10)
#define PM5100_ADC5_GEN3_USB_SNS_V_16 (PM5100_SID << 8 | 0x11)
#define PM5100_ADC5_GEN3_VIN_DIV16_MUX (PM5100_SID << 8 | 0x12)
#define PM5100_ADC5_GEN3_USB_IN_I (PM5100_SID << 8 | 0x17)
#define PM5100_ADC5_GEN3_ICHG_FB (PM5100_SID << 8 | 0xa1)
/* 30k pull-up1 */
#define PM5100_ADC5_GEN3_AMUX1_THM_30K_PU (PM5100_SID << 8 | 0x24)
#define PM5100_ADC5_GEN3_BAT_ID_30K_PU (PM5100_SID << 8 | 0x25)
#define PM5100_ADC5_GEN3_BATT_THM_30K_PU (PM5100_SID << 8 | 0x26)
#define PM5100_ADC5_GEN3_AMUX4_THM_30K_PU (PM5100_SID << 8 | 0x27)
#define PM5100_ADC5_GEN3_AMUX5_THM_30K_PU (PM5100_SID << 8 | 0x28)
#define PM5100_ADC5_GEN3_AMUX6_THM_30K_PU (PM5100_SID << 8 | 0x29)
#define PM5100_ADC5_GEN3_AMUX1_GPIO10_30K_PU (PM5100_SID << 8 | 0x2a)
#define PM5100_ADC5_GEN3_AMUX2_GPIO11_30K_PU (PM5100_SID << 8 | 0x2b)
#define PM5100_ADC5_GEN3_AMUX3_GPIO_30K_PU (PM5100_SID << 8 | 0x2c)
#define PM5100_ADC5_GEN3_AMUX4_GPIO_30K_PU (PM5100_SID << 8 | 0x2d)
/* 100k pull-up2 */
#define PM5100_ADC5_GEN3_AMUX1_THM_100K_PU (PM5100_SID << 8 | 0x44)
#define PM5100_ADC5_GEN3_BAT_ID_100K_PU (PM5100_SID << 8 | 0x45)
#define PM5100_ADC5_GEN3_BATT_THM_100K_PU (PM5100_SID << 8 | 0x46)
#define PM5100_ADC5_GEN3_AMUX4_THM_100K_PU (PM5100_SID << 8 | 0x47)
#define PM5100_ADC5_GEN3_AMUX5_THM_100K_PU (PM5100_SID << 8 | 0x48)
#define PM5100_ADC5_GEN3_AMUX6_THM_100K_PU (PM5100_SID << 8 | 0x49)
#define PM5100_ADC5_GEN3_AMUX1_GPIO10_100K_PU (PM5100_SID << 8 | 0x4a)
#define PM5100_ADC5_GEN3_AMUX2_GPIO11_100K_PU (PM5100_SID << 8 | 0x4b)
#define PM5100_ADC5_GEN3_AMUX3_GPIO_100K_PU (PM5100_SID << 8 | 0x4c)
#define PM5100_ADC5_GEN3_AMUX4_GPIO_100K_PU (PM5100_SID << 8 | 0x4d)
/* 400k pull-up3 */
#define PM5100_ADC5_GEN3_AMUX1_THM_400K_PU (PM5100_SID << 8 | 0x64)
#define PM5100_ADC5_GEN3_BAT_ID_400K_PU (PM5100_SID << 8 | 0x65)
#define PM5100_ADC5_GEN3_BATT_THM_400K_PU (PM5100_SID << 8 | 0x66)
#define PM5100_ADC5_GEN3_AMUX4_THM_400K_PU (PM5100_SID << 8 | 0x67)
#define PM5100_ADC5_GEN3_AMUX5_THM_400K_PU (PM5100_SID << 8 | 0x68)
#define PM5100_ADC5_GEN3_AMUX6_THM_400K_PU (PM5100_SID << 8 | 0x69)
#define PM5100_ADC5_GEN3_AMUX1_GPIO10_400K_PU (PM5100_SID << 8 | 0x6a)
#define PM5100_ADC5_GEN3_AMUX2_GPIO11_400K_PU (PM5100_SID << 8 | 0x6b)
#define PM5100_ADC5_GEN3_AMUX3_GPIO_400K_PU (PM5100_SID << 8 | 0x6c)
#define PM5100_ADC5_GEN3_AMUX4_GPIO_400K_PU (PM5100_SID << 8 | 0x6d)
/* 1/3 Divider */
#define PM5100_ADC5_GEN3_GPIO10_DIV3 (PM5100_SID << 8 | 0x8a)
#define PM5100_ADC5_GEN3_GPIO11_DIV3 (PM5100_SID << 8 | 0x8b)
#define PM5100_ADC5_GEN3_VPH_PWR (PM5100_SID << 8 | 0x8e)
#define PM5100_ADC5_GEN3_VBAT_SNS_QBG (PM5100_SID << 8 | 0x8f)
#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM5100_H */

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include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm7550ba.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __DT_BINDINGS_QCOM_SPMI_VADC_PM7550BA_H
#define __DT_BINDINGS_QCOM_SPMI_VADC_PM7550BA_H
#ifndef PM7550BA_SID
#define PM7550BA_SID 7
#endif
#define PM7550BA_ADC5_GEN3_OFFSET_REF (PM7550BA_SID << 8 | 0x00)
#define PM7550BA_ADC5_GEN3_1P25VREF (PM7550BA_SID << 8 | 0x01)
#define PM7550BA_ADC5_GEN3_VREF_VADC (PM7550BA_SID << 8 | 0x02)
#define PM7550BA_ADC5_GEN3_DIE_TEMP (PM7550BA_SID << 8 | 0x03)
#define PM7550BA_ADC5_GEN3_AMUX_THM1_BATT_THERM (PM7550BA_SID << 8 | 0x04)
#define PM7550BA_ADC5_GEN3_AMUX_THM2_BATT_ID (PM7550BA_SID << 8 | 0x05)
#define PM7550BA_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V (PM7550BA_SID << 8 | 0x06)
#define PM7550BA_ADC5_GEN3_AMUX_THM4_USB_THERM (PM7550BA_SID << 8 | 0x07)
#define PM7550BA_ADC5_GEN3_AMUX_THM5_OPTION (PM7550BA_SID << 8 | 0x08)
#define PM7550BA_ADC5_GEN3_AMUX_THM6_GPIO6 (PM7550BA_SID << 8 | 0x09)
#define PM7550BA_ADC5_GEN3_AMUX1_GPIO1 (PM7550BA_SID << 8 | 0x0a)
#define PM7550BA_ADC5_GEN3_AMUX2_GPIO2 (PM7550BA_SID << 8 | 0x0b)
#define PM7550BA_ADC5_GEN3_AMUX3_GPIO3 (PM7550BA_SID << 8 | 0x0c)
#define PM7550BA_ADC5_GEN3_AMUX4_GPIO4 (PM7550BA_SID << 8 | 0x0d)
#define PM7550BA_ADC5_GEN3_CHG_TEMP_V (PM7550BA_SID << 8 | 0x10)
#define PM7550BA_ADC5_GEN3_USB_SNS_V_16 (PM7550BA_SID << 8 | 0x11)
#define PM7550BA_ADC5_GEN3_VIN_DIV16_MUX (PM7550BA_SID << 8 | 0x12)
#define PM7550BA_ADC5_GEN3_USBC_MUX (PM7550BA_SID << 8 | 0x13)
#define PM7550BA_ADC5_GEN3_VREF_BAT_THERM (PM7550BA_SID << 8 | 0x15)
#define PM7550BA_ADC5_GEN3_IIN_FB (PM7550BA_SID << 8 | 0x17)
#define PM7550BA_ADC5_GEN3_SMB_IIN (PM7550BA_SID << 8 | 0x19)
#define PM7550BA_ADC5_GEN3_SMB_ICHG (PM7550BA_SID << 8 | 0x1b)
#define PM7550BA_ADC5_GEN3_SMB_TEMP_I (PM7550BA_SID << 8 | 0x1e)
#define PM7550BA_ADC5_GEN3_CHG_TEMP_I (PM7550BA_SID << 8 | 0x1f)
#define PM7550BA_ADC5_GEN3_ICHG_FB (PM7550BA_SID << 8 | 0xa1)
/* 30k pull-up */
#define PM7550BA_ADC5_GEN3_AMUX_THM1_BATT_THERM_30K_PU (PM7550BA_SID << 8 | 0x24)
#define PM7550BA_ADC5_GEN3_AMUX_THM2_BATT_ID_30K_PU (PM7550BA_SID << 8 | 0x25)
#define PM7550BA_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_30K_PU (PM7550BA_SID << 8 | 0x26)
#define PM7550BA_ADC5_GEN3_AMUX_THM4_USB_THERM_30K_PU (PM7550BA_SID << 8 | 0x27)
#define PM7550BA_ADC5_GEN3_AMUX_THM5_OPTION_30K_PU (PM7550BA_SID << 8 | 0x28)
#define PM7550BA_ADC5_GEN3_AMUX_THM6_GPIO6_30K_PU (PM7550BA_SID << 8 | 0x29)
#define PM7550BA_ADC5_GEN3_AMUX1_GPIO1_30K_PU (PM7550BA_SID << 8 | 0x2a)
#define PM7550BA_ADC5_GEN3_AMUX2_GPIO2_30K_PU (PM7550BA_SID << 8 | 0x2b)
#define PM7550BA_ADC5_GEN3_AMUX3_GPIO3_30K_PU (PM7550BA_SID << 8 | 0x2c)
#define PM7550BA_ADC5_GEN3_AMUX4_GPIO4_30K_PU (PM7550BA_SID << 8 | 0x2d)
#define PM7550BA_ADC5_GEN3_USBC_MUX_30K_PU (PM7550BA_SID << 8 | 0x33)
/* 100k pull-up */
#define PM7550BA_ADC5_GEN3_AMUX_THM1_BATT_THERM_100K_PU (PM7550BA_SID << 8 | 0x44)
#define PM7550BA_ADC5_GEN3_AMUX_THM2_BATT_ID_100K_PU (PM7550BA_SID << 8 | 0x45)
#define PM7550BA_ADC5_GEN3_AMUX_THM3_SMB_THEMP_100K_PU (PM7550BA_SID << 8 | 0x46)
#define PM7550BA_ADC5_GEN3_AMUX_THM4_USB_THERM_100K_PU (PM7550BA_SID << 8 | 0x47)
#define PM7550BA_ADC5_GEN3_AMUX_THM5_OPTION_100K_PU (PM7550BA_SID << 8 | 0x48)
#define PM7550BA_ADC5_GEN3_AMUX_THM6_GPIO6_100K_PU (PM7550BA_SID << 8 | 0x49)
#define PM7550BA_ADC5_GEN3_AMUX1_GPIO1_100K_PU (PM7550BA_SID << 8 | 0x4a)
#define PM7550BA_ADC5_GEN3_AMUX2_GPIO2_100K_PU (PM7550BA_SID << 8 | 0x4b)
#define PM7550BA_ADC5_GEN3_AMUX3_GPIO3_100K_PU (PM7550BA_SID << 8 | 0x4c)
#define PM7550BA_ADC5_GEN3_AMUX4_GPIO4_100K_PU (PM7550BA_SID << 8 | 0x4d)
#define PM7550_ADC5_GEN3_USBC_MUX_100K_PU (PM7550BA_SID << 8 | 0x53)
/* 400k pull-up */
#define PM7550BA_ADC5_GEN3_AMUX_THM1_BATT_THERM_400K_PU (PM7550BA_SID << 8 | 0x64)
#define PM7550BA_ADC5_GEN3_AMUX_THM2_BATT_ID_400K_PU (PM7550BA_SID << 8 | 0x65)
#define PM7550BA_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_400K_PU (PM7550BA_SID << 8 | 0x66)
#define PM7550BA_ADC5_GEN3_AMUX_THM4_USB_THERM_400K_PU (PM7550BA_SID << 8 | 0x67)
#define PM7550BA_ADC5_GEN3_AMUX_THM5_OPTION_400K_PU (PM7550BA_SID << 8 | 0x68)
#define PM7550BA_ADC5_GEN3_AMUX_THM6_GPIO6_400K_PU (PM7550BA_SID << 8 | 0x69)
#define PM7550BA_ADC5_GEN3_AMUX1_GPIO1_400K_PU (PM7550BA_SID << 8 | 0x6a)
#define PM7550BA_ADC5_GEN3_AMUX2_GPIO2_400K_PU (PM7550BA_SID << 8 | 0x6b)
#define PM7550BA_ADC5_GEN3_AMUX3_GPIO3_400K_PU (PM7550BA_SID << 8 | 0x6c)
#define PM7550BA_ADC5_GEN3_AMUX4_GPIO4_400K_PU (PM7550BA_SID << 8 | 0x6d)
#define PM7550BA_ADC5_GEN3_USBC_MUX_400K_PU (PM7550BA_SID << 8 | 0x73)
/* 1/3 Divider*/
#define PM7550BA_ADC5_GEN3_AMUX1_GPIO1_DIV3 (PM7550BA_SID << 8 | 0x8a)
#define PM7550BA_ADC5_GEN3_AMUX2_GPIO2_DIV3 (PM7550BA_SID << 8 | 0x8b)
#define PM7550BA_ADC5_GEN3_AMUX3_GPIO3_DIV3 (PM7550BA_SID << 8 | 0x8c)
#define PM7550BA_ADC5_GEN3_AMUX4_GPIO4_DIV3 (PM7550BA_SID << 8 | 0x8d)
#define PM7550BA_ADC5_GEN3_VPH_PWR (PM7550BA_SID << 8 | 0x8e)
#define PM7550BA_ADC5_GEN3_VBAT_SNS_QBG (PM7550BA_SID << 8 | 0x8f)
#define PM7550BA_ADC5_GEN3_VBAT_SNS_CHGR (PM7550BA_SID << 8 | 0x94)
#endif /* __DT_BINDINGS_QCOM_SPMI_VADC_PM7550_H */

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include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H
#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H
#ifndef PM8550_SID
#define PM8550_SID 1
#endif
/* ADC channels for PM8550_ADC for PMIC5 Gen3 */
#define PM8550_ADC5_GEN3_OFFSET_REF (PM8550_SID << 8 | 0x00)
#define PM8550_ADC5_GEN3_1P25VREF (PM8550_SID << 8 | 0x01)
#define PM8550_ADC5_GEN3_VREF_VADC (PM8550_SID << 8 | 0x02)
#define PM8550_ADC5_GEN3_DIE_TEMP (PM8550_SID << 8 | 0x03)
#define PM8550_ADC5_GEN3_AMUX_THM1 (PM8550_SID << 8 | 0x04)
#define PM8550_ADC5_GEN3_AMUX_THM2 (PM8550_SID << 8 | 0x05)
#define PM8550_ADC5_GEN3_AMUX_THM3 (PM8550_SID << 8 | 0x06)
#define PM8550_ADC5_GEN3_AMUX_THM4 (PM8550_SID << 8 | 0x07)
#define PM8550_ADC5_GEN3_AMUX_THM5 (PM8550_SID << 8 | 0x08)
#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2 (PM8550_SID << 8 | 0x09)
#define PM8550_ADC5_GEN3_AMUX1_GPIO3 (PM8550_SID << 8 | 0x0a)
#define PM8550_ADC5_GEN3_AMUX2_GPIO4 (PM8550_SID << 8 | 0x0b)
#define PM8550_ADC5_GEN3_AMUX3_GPIO7 (PM8550_SID << 8 | 0x0c)
#define PM8550_ADC5_GEN3_AMUX4_GPIO12 (PM8550_SID << 8 | 0x0d)
/* 100k pull-up */
#define PM8550_ADC5_GEN3_AMUX_THM1_100K_PU (PM8550_SID << 8 | 0x44)
#define PM8550_ADC5_GEN3_AMUX_THM2_100K_PU (PM8550_SID << 8 | 0x45)
#define PM8550_ADC5_GEN3_AMUX_THM3_100K_PU (PM8550_SID << 8 | 0x46)
#define PM8550_ADC5_GEN3_AMUX_THM4_100K_PU (PM8550_SID << 8 | 0x47)
#define PM8550_ADC5_GEN3_AMUX_THM5_100K_PU (PM8550_SID << 8 | 0x48)
#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2_100K_PU (PM8550_SID << 8 | 0x49)
#define PM8550_ADC5_GEN3_AMUX1_GPIO3_100K_PU (PM8550_SID << 8 | 0x4a)
#define PM8550_ADC5_GEN3_AMUX2_GPIO4_100K_PU (PM8550_SID << 8 | 0x4b)
#define PM8550_ADC5_GEN3_AMUX3_GPIO7_100K_PU (PM8550_SID << 8 | 0x4c)
#define PM8550_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8550_SID << 8 | 0x4d)
/* 1/3 Divider */
#define PM8550_ADC5_GEN3_AMUX3_GPIO7_DIV3 (PM8550_SID << 8 | 0x8c)
#define PM8550_ADC5_GEN3_AMUX4_GPIO12_DIV3 (PM8550_SID << 8 | 0x8d)
#define PM8550_ADC5_GEN3_VPH_PWR (PM8550_SID << 8 | 0x8e)
#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H */

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include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H
#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H
#ifndef PM8550B_SID
#define PM8550B_SID 7
#endif
/* ADC channels for PM8550B_ADC for PMIC5 Gen3 */
#define PM8550B_ADC5_GEN3_OFFSET_REF (PM8550B_SID << 8 | 0x00)
#define PM8550B_ADC5_GEN3_1P25VREF (PM8550B_SID << 8 | 0x01)
#define PM8550B_ADC5_GEN3_VREF_VADC (PM8550B_SID << 8 | 0x02)
#define PM8550B_ADC5_GEN3_DIE_TEMP (PM8550B_SID << 8 | 0x03)
#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM (PM8550B_SID << 8 | 0x04)
#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID (PM8550B_SID << 8 | 0x05)
#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V (PM8550B_SID << 8 | 0x06)
#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM (PM8550B_SID << 8 | 0x07)
#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION (PM8550B_SID << 8 | 0x08)
#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10 (PM8550B_SID << 8 | 0x09)
#define PM8550B_ADC5_GEN3_AMUX1_GPIO1 (PM8550B_SID << 8 | 0x0a)
#define PM8550B_ADC5_GEN3_AMUX2_GPIO5 (PM8550B_SID << 8 | 0x0b)
#define PM8550B_ADC5_GEN3_AMUX3_GPIO6 (PM8550B_SID << 8 | 0x0c)
#define PM8550B_ADC5_GEN3_AMUX4_GPIO12 (PM8550B_SID << 8 | 0x0d)
#define PM8550B_ADC5_GEN3_CHG_TEMP (PM8550B_SID << 8 | 0x10)
#define PM8550B_ADC5_GEN3_USB_SNS_V_16 (PM8550B_SID << 8 | 0x11)
#define PM8550B_ADC5_GEN3_VIN_DIV16_MUX (PM8550B_SID << 8 | 0x12)
#define PM8550B_ADC5_GEN3_USBC_MUX (PM8550B_SID << 8 | 0x13)
#define PM8550B_ADC5_GEN3_VREF_BAT_THERM (PM8550B_SID << 8 | 0x15)
#define PM8550B_ADC5_GEN3_IIN_FB (PM8550B_SID << 8 | 0x17)
#define PM8550B_ADC5_GEN3_TEMP_ALARM_LITE (PM8550B_SID << 8 | 0x18)
#define PM8550B_ADC5_GEN3_SMB_IIN (PM8550B_SID << 8 | 0x19)
#define PM8550B_ADC5_GEN3_VREF_BAT2_THERM (PM8550B_SID << 8 | 0x1a)
#define PM8550B_ADC5_GEN3_SMB_ICHG (PM8550B_SID << 8 | 0x1b)
#define PM8550B_ADC5_GEN3_SMB_TEMP_I (PM8550B_SID << 8 | 0x1e)
#define PM8550B_ADC5_GEN3_CHG_TEMP_I (PM8550B_SID << 8 | 0x1f)
#define PM8550B_ADC5_GEN3_ICHG_FB (PM8550B_SID << 8 | 0xa1)
/* 30k pull-up */
#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_30K_PU (PM8550B_SID << 8 | 0x24)
#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_30K_PU (PM8550B_SID << 8 | 0x25)
#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_30K_PU (PM8550B_SID << 8 | 0x26)
#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_30K_PU (PM8550B_SID << 8 | 0x27)
#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_30K_PU (PM8550B_SID << 8 | 0x28)
#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_30K_PU (PM8550B_SID << 8 | 0x29)
#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_30K_PU (PM8550B_SID << 8 | 0x2a)
#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_30K_PU (PM8550B_SID << 8 | 0x2b)
#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_30K_PU (PM8550B_SID << 8 | 0x2c)
#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_30K_PU (PM8550B_SID << 8 | 0x2d)
#define PM8550B_ADC5_GEN3_USBC_MUX_30K_PU (PM8550B_SID << 8 | 0x33)
/* 100k pull-up */
#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_100K_PU (PM8550B_SID << 8 | 0x44)
#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_100K_PU (PM8550B_SID << 8 | 0x45)
#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_100K_PU (PM8550B_SID << 8 | 0x46)
#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_100K_PU (PM8550B_SID << 8 | 0x47)
#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_100K_PU (PM8550B_SID << 8 | 0x48)
#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_100K_PU (PM8550B_SID << 8 | 0x49)
#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_100K_PU (PM8550B_SID << 8 | 0x4a)
#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_100K_PU (PM8550B_SID << 8 | 0x4b)
#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_100K_PU (PM8550B_SID << 8 | 0x4c)
#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8550B_SID << 8 | 0x4d)
#define PM8550B_ADC5_GEN3_USBC_MUX_100K_PU (PM8550B_SID << 8 | 0x53)
/* 400k pull-up */
#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_400K_PU (PM8550B_SID << 8 | 0x64)
#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_400K_PU (PM8550B_SID << 8 | 0x65)
#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_400K_PU (PM8550B_SID << 8 | 0x66)
#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_400K_PU (PM8550B_SID << 8 | 0x67)
#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_400K_PU (PM8550B_SID << 8 | 0x68)
#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_400K_PU (PM8550B_SID << 8 | 0x69)
#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_400K_PU (PM8550B_SID << 8 | 0x6a)
#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_400K_PU (PM8550B_SID << 8 | 0x6b)
#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_400K_PU (PM8550B_SID << 8 | 0x6c)
#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_400K_PU (PM8550B_SID << 8 | 0x6d)
#define PM8550B_ADC5_GEN3_USBC_MUX_400K_PU (PM8550B_SID << 8 | 0x73)
/* 1/3 Divider */
#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_DIV3 (PM8550B_SID << 8 | 0x8a)
#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_DIV3 (PM8550B_SID << 8 | 0x8b)
#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_DIV3 (PM8550B_SID << 8 | 0x8c)
#define PM8550B_ADC5_GEN3_VPH_PWR (PM8550B_SID << 8 | 0x8e)
#define PM8550B_ADC5_GEN3_VBAT_SNS_QBG (PM8550B_SID << 8 | 0x8f)
#define PM8550B_ADC5_GEN3_VBAT_SNS_CHGR (PM8550B_SID << 8 | 0x94)
#define PM8550B_ADC5_GEN3_VBAT_2S_MID_QBG (PM8550B_SID << 8 | 0x96)
#define PM8550B_ADC5_GEN3_VBAT_2S_MID_CHGR (PM8550B_SID << 8 | 0x9d)
#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H */

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include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H
#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H
#include <dt-bindings/iio/qcom,spmi-vadc.h>
/* ADC channels for PM8550VX_ADC for PMIC5 Gen3 */
#define PM8550VX_ADC5_GEN3_OFFSET_REF(sid) ((sid) << 8 | ADC5_GEN3_OFFSET_REF)
#define PM8550VX_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | ADC5_GEN3_1P25VREF)
#define PM8550VX_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | ADC5_GEN3_VREF_VADC)
#define PM8550VX_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | ADC5_GEN3_DIE_TEMP)
#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H */

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include/dt-bindings/iio/qcom,spmi-adc5-gen3-pmiv0104.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMIV0104_H
#define _DT_BINDINGS_QCOM_SPMI_VADC_PMIV0104_H
#ifndef PMIV0104_SID
#define PMIV0104_SID 7
#endif
/* ADC channels for PMIV0104_ADC for PMIC5 Gen3 */
#define PMIV0104_ADC5_GEN3_OFFSET_REF (PMIV0104_SID << 8 | 0x00)
#define PMIV0104_ADC5_GEN3_1P25VREF (PMIV0104_SID << 8 | 0x01)
#define PMIV0104_ADC5_GEN3_VREF_VADC (PMIV0104_SID << 8 | 0x02)
#define PMIV0104_ADC5_GEN3_DIE_TEMP (PMIV0104_SID << 8 | 0x03)
#define PMIV0104_ADC5_GEN3_AMUX_THM1_BATT_THERM (PMIV0104_SID << 8 | 0x04)
#define PMIV0104_ADC5_GEN3_AMUX_THM2_BATT_ID (PMIV0104_SID << 8 | 0x05)
#define PMIV0104_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V (PMIV0104_SID << 8 | 0x06)
#define PMIV0104_ADC5_GEN3_AMUX_THM4_USB_THERM (PMIV0104_SID << 8 | 0x07)
#define PMIV0104_ADC5_GEN3_AMUX_THM5_OPTION (PMIV0104_SID << 8 | 0x08)
#define PMIV0104_ADC5_GEN3_AMUX_THM6_GPIO6 (PMIV0104_SID << 8 | 0x09)
#define PMIV0104_ADC5_GEN3_AMUX1_GPIO1 (PMIV0104_SID << 8 | 0x0a)
#define PMIV0104_ADC5_GEN3_AMUX2_GPIO2 (PMIV0104_SID << 8 | 0x0b)
#define PMIV0104_ADC5_GEN3_AMUX3_GPIO7 (PMIV0104_SID << 8 | 0x0c)
#define PMIV0104_ADC5_GEN3_AMUX4_GPIO8 (PMIV0104_SID << 8 | 0x0d)
#define PMIV0104_ADC5_GEN3_CHG_TEMP (PMIV0104_SID << 8 | 0x10)
#define PMIV0104_ADC5_GEN3_USB_SNS_V_16 (PMIV0104_SID << 8 | 0x11)
#define PMIV0104_ADC5_GEN3_VIN_DIV16_MUX (PMIV0104_SID << 8 | 0x12)
#define PMIV0104_ADC5_GEN3_USBC_MUX (PMIV0104_SID << 8 | 0x13)
#define PMIV0104_ADC5_GEN3_VREF_BAT_THERM (PMIV0104_SID << 8 | 0x15)
#define PMIV0104_ADC5_GEN3_IIN_FB (PMIV0104_SID << 8 | 0x17)
#define PMIV0104_ADC5_GEN3_SMB_IIN (PMIV0104_SID << 8 | 0x19)
#define PMIV0104_ADC5_GEN3_SMB_ICHG (PMIV0104_SID << 8 | 0x1b)
#define PMIV0104_ADC5_GEN3_SMB_TEMP_I (PMIV0104_SID << 8 | 0x1e)
#define PMIV0104_ADC5_GEN3_CHG_TEMP_I (PMIV0104_SID << 8 | 0x1f)
#define PMIV0104_ADC5_GEN3_ICHG_FB (PMIV0104_SID << 8 | 0xa1)
/* 30k pull-up */
#define PMIV0104_ADC5_GEN3_AMUX_THM1_BATT_THERM_30K_PU (PMIV0104_SID << 8 | 0x24)
#define PMIV0104_ADC5_GEN3_AMUX_THM2_BATT_ID_30K_PU (PMIV0104_SID << 8 | 0x25)
#define PMIV0104_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_30K_PU (PMIV0104_SID << 8 | 0x26)
#define PMIV0104_ADC5_GEN3_AMUX_THM4_USB_THERM_30K_PU (PMIV0104_SID << 8 | 0x27)
#define PMIV0104_ADC5_GEN3_AMUX_THM5_OPTION_30K_PU (PMIV0104_SID << 8 | 0x28)
#define PMIV0104_ADC5_GEN3_AMUX_THM6_GPIO6_30K_PU (PMIV0104_SID << 8 | 0x29)
#define PMIV0104_ADC5_GEN3_AMUX1_GPIO1_30K_PU (PMIV0104_SID << 8 | 0x2a)
#define PMIV0104_ADC5_GEN3_AMUX2_GPIO2_30K_PU (PMIV0104_SID << 8 | 0x2b)
#define PMIV0104_ADC5_GEN3_AMUX3_GPIO7_30K_PU (PMIV0104_SID << 8 | 0x2c)
#define PMIV0104_ADC5_GEN3_AMUX4_GPIO8_30K_PU (PMIV0104_SID << 8 | 0x2d)
#define PMIV0104_ADC5_GEN3_USBC_MUX_30K_PU (PMIV0104_SID << 8 | 0x33)
/* 100k pull-up */
#define PMIV0104_ADC5_GEN3_AMUX_THM1_BATT_THERM_100K_PU (PMIV0104_SID << 8 | 0x44)
#define PMIV0104_ADC5_GEN3_AMUX_THM2_BATT_ID_100K_PU (PMIV0104_SID << 8 | 0x45)
#define PMIV0104_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_100K_PU (PMIV0104_SID << 8 | 0x46)
#define PMIV0104_ADC5_GEN3_AMUX_THM4_USB_THERM_100K_PU (PMIV0104_SID << 8 | 0x47)
#define PMIV0104_ADC5_GEN3_AMUX_THM5_OPTION_100K_PU (PMIV0104_SID << 8 | 0x48)
#define PMIV0104_ADC5_GEN3_AMUX_THM6_GPIO6_100K_PU (PMIV0104_SID << 8 | 0x49)
#define PMIV0104_ADC5_GEN3_AMUX1_GPIO1_100K_PU (PMIV0104_SID << 8 | 0x4a)
#define PMIV0104_ADC5_GEN3_AMUX2_GPIO2_100K_PU (PMIV0104_SID << 8 | 0x4b)
#define PMIV0104_ADC5_GEN3_AMUX3_GPIO7_100K_PU (PMIV0104_SID << 8 | 0x4c)
#define PMIV0104_ADC5_GEN3_AMUX4_GPIO8_100K_PU (PMIV0104_SID << 8 | 0x4d)
#define PMIV0104_ADC5_GEN3_USBC_MUX_100K_PU (PMIV0104_SID << 8 | 0x53)
/* 400k pull-up */
#define PMIV0104_ADC5_GEN3_AMUX_THM1_BATT_THERM_400K_PU (PMIV0104_SID << 8 | 0x64)
#define PMIV0104_ADC5_GEN3_AMUX_THM2_BATT_ID_400K_PU (PMIV0104_SID << 8 | 0x65)
#define PMIV0104_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_400K_PU (PMIV0104_SID << 8 | 0x66)
#define PMIV0104_ADC5_GEN3_AMUX_THM4_USB_THERM_400K_PU (PMIV0104_SID << 8 | 0x67)
#define PMIV0104_ADC5_GEN3_AMUX_THM5_OPTION_400K_PU (PMIV0104_SID << 8 | 0x68)
#define PMIV0104_ADC5_GEN3_AMUX_THM6_GPIO6_400K_PU (PMIV0104_SID << 8 | 0x69)
#define PMIV0104_ADC5_GEN3_AMUX1_GPIO1_400K_PU (PMIV0104_SID << 8 | 0x6a)
#define PMIV0104_ADC5_GEN3_AMUX2_GPIO2_400K_PU (PMIV0104_SID << 8 | 0x6b)
#define PMIV0104_ADC5_GEN3_AMUX3_GPIO7_400K_PU (PMIV0104_SID << 8 | 0x6c)
#define PMIV0104_ADC5_GEN3_AMUX4_GPIO8_400K_PU (PMIV0104_SID << 8 | 0x6d)
#define PMIV0104_ADC5_GEN3_USBC_MUX_400K_PU (PMIV0104_SID << 8 | 0x73)
/* 1/3 Divider */
#define PMIV0104_ADC5_GEN3_AMUX1_GPIO1_DIV3 (PMIV0104_SID << 8 | 0x8a)
#define PMIV0104_ADC5_GEN3_AMUX2_GPIO2_DIV3 (PMIV0104_SID << 8 | 0x8b)
#define PMIV0104_ADC5_GEN3_VPH_PWR (PMIV0104_SID << 8 | 0x8e)
#define PMIV0104_ADC5_GEN3_VBAT_SNS_QBG (PMIV0104_SID << 8 | 0x8f)
#define PMIV0104_ADC5_GEN3_VBAT_SNS_CHGR (PMIV0104_SID << 8 | 0x94)
#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMIV0104_H */

54
include/dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H
#define _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H
#ifndef PMK8550_SID
#define PMK8550_SID 0
#endif
/* ADC channels for PMK8550_ADC for PMIC5 Gen3 */
#define PMK8550_ADC5_GEN3_OFFSET_REF (PMK8550_SID << 8 | 0x00)
#define PMK8550_ADC5_GEN3_1P25VREF (PMK8550_SID << 8 | 0x01)
#define PMK8550_ADC5_GEN3_VREF_VADC (PMK8550_SID << 8 | 0x02)
#define PMK8550_ADC5_GEN3_DIE_TEMP (PMK8550_SID << 8 | 0x03)
#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM (PMK8550_SID << 8 | 0x04)
#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1 (PMK8550_SID << 8 | 0x05)
#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2 (PMK8550_SID << 8 | 0x06)
#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3 (PMK8550_SID << 8 | 0x07)
#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4 (PMK8550_SID << 8 | 0x08)
#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5 (PMK8550_SID << 8 | 0x09)
#define PMK8550_ADC5_GEN3_AMUX1_GPIO6 (PMK8550_SID << 8 | 0x0a)
/* 30k pull-up */
#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_30K_PU (PMK8550_SID << 8 | 0x24)
#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_30K_PU (PMK8550_SID << 8 | 0x25)
#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_30K_PU (PMK8550_SID << 8 | 0x26)
#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_30K_PU (PMK8550_SID << 8 | 0x27)
#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_30K_PU (PMK8550_SID << 8 | 0x28)
#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_30K_PU (PMK8550_SID << 8 | 0x29)
#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_30K_PU (PMK8550_SID << 8 | 0x2a)
/* 100k pull-up */
#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU (PMK8550_SID << 8 | 0x44)
#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_100K_PU (PMK8550_SID << 8 | 0x45)
#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_100K_PU (PMK8550_SID << 8 | 0x46)
#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_100K_PU (PMK8550_SID << 8 | 0x47)
#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_100K_PU (PMK8550_SID << 8 | 0x48)
#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_100K_PU (PMK8550_SID << 8 | 0x49)
#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_100K_PU (PMK8550_SID << 8 | 0x4a)
/* 400k pull-up */
#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_400K_PU (PMK8550_SID << 8 | 0x64)
#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_400K_PU (PMK8550_SID << 8 | 0x65)
#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_400K_PU (PMK8550_SID << 8 | 0x66)
#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_400K_PU (PMK8550_SID << 8 | 0x67)
#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_400K_PU (PMK8550_SID << 8 | 0x68)
#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_400K_PU (PMK8550_SID << 8 | 0x69)
#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_400K_PU (PMK8550_SID << 8 | 0x6a)
#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H */

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include/dt-bindings/iio/qcom,spmi-adc5-gen3-pmx75.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMX75_H
#define _DT_BINDINGS_QCOM_SPMI_VADC_PMX75_H
#ifndef PMX75_SID
#define PMX75_SID 1
#endif
/* ADC channels for PMX75_ADC for PMIC5 Gen3 */
#define PMX75_ADC5_GEN3_OFFSET_REF (PMX75_SID << 8 | 0x00)
#define PMX75_ADC5_GEN3_1P25VREF (PMX75_SID << 8 | 0X01)
#define PMX75_ADC5_GEN3_VREF_VADC (PMX75_SID << 8 | 0x02)
#define PMX75_ADC5_GEN3_DIE_TEMP (PMX75_SID << 8 | 0x03)
#define PMX75_ADC5_GEN3_AMUX_THM1 (PMX75_SID << 8 | 0x04)
#define PMX75_ADC5_GEN3_AMUX_THM2 (PMX75_SID << 8 | 0x05)
#define PMX75_ADC5_GEN3_AMUX_THM3 (PMX75_SID << 8 | 0x06)
#define PMX75_ADC5_GEN3_AMUX_THM4 (PMX75_SID << 8 | 0x07)
#define PMX75_ADC5_GEN3_AMUX_THM5 (PMX75_SID << 8 | 0x08)
#define PMX75_ADC5_GEN3_AMUX_THM6 (PMX75_SID << 8 | 0x09)
#define PMX75_ADC5_GEN3_AMUX1_GPIO5 (PMX75_SID << 8 | 0x0a)
#define PMX75_ADC5_GEN3_AMUX2_GPIO12 (PMX75_SID << 8 | 0x0b)
#define PMX75_ADC5_GEN3_AMUX3_GPIO15 (PMX75_SID << 8 | 0x0c)
#define PMX75_ADC5_GEN3_AMUX4_GPIO1 (PMX75_SID << 8 | 0x0d)
/* 100K pull-up */
#define PMX75_ADC5_GEN3_AMUX_THM1_100K_PU (PMX75_SID << 8 | 0x44)
#define PMX75_ADC5_GEN3_AMUX_THM2_100K_PU (PMX75_SID << 8 | 0x45)
#define PMX75_ADC5_GEN3_AMUX_THM3_100K_PU (PMX75_SID << 8 | 0x46)
#define PMX75_ADC5_GEN3_AMUX_THM4_100K_PU (PMX75_SID << 8 | 0x47)
#define PMX75_ADC5_GEN3_AMUX_THM5_100K_PU (PMX75_SID << 8 | 0x48)
#define PMX75_ADC5_GEN3_AMUX_THM6_100K_PU (PMX75_SID << 8 | 0x49)
#define PMX75_ADC5_GEN3_AMUX1_GPIO5_100K_PU (PMX75_SID << 8 | 0x4a)
#define PMX75_ADC5_GEN3_AMUX2_GPIO12_100K_PU (PMX75_SID << 8 | 0x4b)
#define PMX75_ADC5_GEN3_AMUX3_GPIO15_100K_PU (PMX75_SID << 8 | 0x4c)
#define PMX75_ADC5_GEN3_AMUX4_GPIO1_100K_PU (PMX75_SID << 8 | 0x4d)
/* 1/3 Divider */
#define PMX75_ADC5_GEN3_AMUX2_GPIO12_DIV3 (PMX75_SID << 8 | 0x8b)
#define PMX75_ADC5_GEN3_AMUX3_GPIO15_DIV3 (PMX75_SID << 8 | 0x8c)
#define PMX75_ADC5_GEN3_VPH_PWR (PMX75_SID << 8 | 0x8e)
#endif /* __DT_BINDINGS_QCOM_SPMI_VADC_PMX75_H */

48
include/dt-bindings/iio/qcom,spmi-adc5-gen3-pmxr2230.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMXR2230_H
#define _DT_BINDINGS_QCOM_SPMI_VADC_PMXR2230_H
#ifndef PMXR2230_SID
#define PMXR2230_SID 1
#endif
/* ADC channels for PMXR2230_ADC for PMIC5 Gen3 */
#define PMXR2230_ADC5_GEN3_OFFSET_REF (PMXR2230_SID << 8 | 0x00)
#define PMXR2230_ADC5_GEN3_1P25VREF (PMXR2230_SID << 8 | 0x01)
#define PMXR2230_ADC5_GEN3_VREF_VADC (PMXR2230_SID << 8 | 0x02)
#define PMXR2230_ADC5_GEN3_DIE_TEMP (PMXR2230_SID << 8 | 0x03)
#define PMXR2230_ADC5_GEN3_AMUX_THM1 (PMXR2230_SID << 8 | 0x04)
#define PMXR2230_ADC5_GEN3_AMUX_THM2 (PMXR2230_SID << 8 | 0x05)
#define PMXR2230_ADC5_GEN3_AMUX_THM3 (PMXR2230_SID << 8 | 0x06)
#define PMXR2230_ADC5_GEN3_AMUX_THM4 (PMXR2230_SID << 8 | 0x07)
#define PMXR2230_ADC5_GEN3_AMUX_THM5 (PMXR2230_SID << 8 | 0x08)
#define PMXR2230_ADC5_GEN3_AMUX_THM6_GPIO2 (PMXR2230_SID << 8 | 0x09)
#define PMXR2230_ADC5_GEN3_AMUX1_GPIO3 (PMXR2230_SID << 8 | 0x0a)
#define PMXR2230_ADC5_GEN3_AMUX2_GPIO4 (PMXR2230_SID << 8 | 0x0b)
#define PMXR2230_ADC5_GEN3_AMUX3_GPIO7 (PMXR2230_SID << 8 | 0x0c)
#define PMXR2230_ADC5_GEN3_AMUX4_GPIO10 (PMXR2230_SID << 8 | 0x0d)
/* 100k pull-up */
#define PMXR2230_ADC5_GEN3_AMUX_THM1_100K_PU (PMXR2230_SID << 8 | 0x44)
#define PMXR2230_ADC5_GEN3_AMUX_THM2_100K_PU (PMXR2230_SID << 8 | 0x45)
#define PMXR2230_ADC5_GEN3_AMUX_THM3_100K_PU (PMXR2230_SID << 8 | 0x46)
#define PMXR2230_ADC5_GEN3_AMUX_THM4_100K_PU (PMXR2230_SID << 8 | 0x47)
#define PMXR2230_ADC5_GEN3_AMUX_THM5_100K_PU (PMXR2230_SID << 8 | 0x48)
#define PMXR2230_ADC5_GEN3_AMUX_THM6_GPIO2_100K_PU (PMXR2230_SID << 8 | 0x49)
#define PMXR2230_ADC5_GEN3_AMUX1_GPIO3_100K_PU (PMXR2230_SID << 8 | 0x4a)
#define PMXR2230_ADC5_GEN3_AMUX2_GPIO4_100K_PU (PMXR2230_SID << 8 | 0x4b)
#define PMXR2230_ADC5_GEN3_AMUX3_GPIO7_100K_PU (PMXR2230_SID << 8 | 0x4c)
#define PMXR2230_ADC5_GEN3_AMUX4_GPIO10_100K_PU (PMXR2230_SID << 8 | 0x4d)
/* 1/3 Divider */
#define PMXR2230_ADC5_GEN3_AMUX3_GPIO7_DIV3 (PMXR2230_SID << 8 | 0x8c)
#define PMXR2230_ADC5_GEN3_AMUX4_GPIO10_DIV3 (PMXR2230_SID << 8 | 0x8d)
#define PMXR2230_ADC5_GEN3_VPH_PWR (PMXR2230_SID << 8 | 0x8e)
#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMXR2230_H */

25
include/dt-bindings/iio/qcom,spmi-adc5-gen3-smb139x.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_GEN3_SMB139X_H
#define _DT_BINDINGS_QCOM_SPMI_VADC_GEN3_SMB139X_H
#ifndef SMB1394_1_SID
#define SMB1394_1_SID 0x09
#endif
#ifndef SMB1394_2_SID
#define SMB1394_2_SID 0x0b
#endif
#define SMB1394_1_ADC5_GEN3_SMB_TEMP (SMB1394_1_SID << 8 | 0x06)
#define SMB1394_1_ADC5_GEN3_IIN_SMB (SMB1394_1_SID << 8 | 0x19)
#define SMB1394_1_ADC5_GEN3_ICHG_SMB (SMB1394_1_SID << 8 | 0x1b)
#define SMB1394_2_ADC5_GEN3_SMB_TEMP (SMB1394_2_SID << 8 | 0x06)
#define SMB1394_2_ADC5_GEN3_IIN_SMB (SMB1394_2_SID << 8 | 0x19)
#define SMB1394_2_ADC5_GEN3_ICHG_SMB (SMB1394_2_SID << 8 | 0x1b)
#endif

96
include/dt-bindings/iio/qcom,spmi-adc5-gen4-pmih010x.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMIH010X_H
#define _DT_BINDINGS_QCOM_SPMI_VADC_PMIH010X_H
#ifndef PMIH010X_SID
#define PMIH010X_SID 7
#endif
#define PMI_SID (PMIH010X_SID << 8)
/* ADC channels for PMIH010X_ADC for PMIC5 Gen4 */
#define PMIH010X_ADC5_GEN4_OFFSET_REF (PMI_SID | ADC5_GEN4_OFFSET_REF)
#define PMIH010X_ADC5_GEN4_1P25VREF (PMI_SID | ADC5_GEN4_1P25VREF)
#define PMIH010X_ADC5_GEN4_VREF_VADC (PMI_SID | ADC5_GEN4_VREF_VADC)
#define PMIH010X_ADC5_GEN4_DIE_TEMP (PMI_SID | ADC5_GEN4_DIE_TEMP)
#define PMIH010X_ADC5_GEN4_AMUX_THM1_BAT_THERM (PMI_SID | ADC5_GEN4_AMUX1_THM)
#define PMIH010X_ADC5_GEN4_AMUX_THM2_BAT_ID (PMI_SID | ADC5_GEN4_AMUX2_THM)
#define PMIH010X_ADC5_GEN4_AMUX_THM3_SMB_TEMP_V (PMI_SID | ADC5_GEN4_AMUX3_THM)
#define PMIH010X_ADC5_GEN4_AMUX_THM4_USB_THERM (PMI_SID | ADC5_GEN4_AMUX4_THM)
#define PMIH010X_ADC5_GEN4_AMUX_THM5_OPTION (PMI_SID | ADC5_GEN4_AMUX5_THM)
#define PMIH010X_ADC5_GEN4_AMUX_THM6_OPTION2 (PMI_SID | ADC5_GEN4_AMUX6_THM)
#define PMIH010X_ADC5_GEN4_AMUX1_GPIO6 (PMI_SID | ADC5_GEN4_AMUX1_GPIO)
#define PMIH010X_ADC5_GEN4_AMUX2_BAT2_ID (PMI_SID | ADC5_GEN4_AMUX2_GPIO)
#define PMIH010X_ADC5_GEN4_AMUX3_BAT2_THERM (PMI_SID | ADC5_GEN4_AMUX3_GPIO)
#define PMIH010X_ADC5_GEN4_AMUX4_GPIO12 (PMI_SID | ADC5_GEN4_AMUX4_GPIO)
#define PMIH010X_ADC5_GEN4_CHG_TEMP (PMI_SID | ADC5_GEN4_CHG_TEMP)
#define PMIH010X_ADC5_GEN4_USB_SNS_DIV20 (PMI_SID | ADC5_GEN4_USB_SNS_DIV20)
#define PMIH010X_ADC5_GEN4_VIN_DIV20_MUX (PMI_SID | ADC5_GEN4_VIN_DIV20_MUX)
#define PMIH010X_ADC5_GEN4_USBC_MUX (PMI_SID | ADC5_GEN4_USBC_MUX)
#define PMIH010X_ADC5_GEN4_VREF_BAT_THERM (PMI_SID | ADC5_GEN4_VREF_BAT_THERM)
#define PMIH010X_ADC5_GEN4_IIN (PMI_SID | ADC5_GEN4_IIN)
#define PMIH010X_ADC5_GEN4_TEMP_ALARM_LITE (PMI_SID | ADC5_GEN4_TEMP_ALARM_LITE)
#define PMIH010X_ADC5_GEN4_VREF_BAT2_THERM (PMI_SID | ADC5_GEN4_VREF_BAT2_THERM)
#define PMIH010X_ADC5_GEN4_ATEST1 (PMI_SID | ADC5_GEN4_ATEST1)
#define PMIH010X_ADC5_GEN4_ATEST2 (PMI_SID | ADC5_GEN4_ATEST2)
#define PMIH010X_ADC5_GEN4_VBAT_2S_MID_CHGR (PMI_SID | ADC5_GEN4_VBAT_2S_MID_CHGR)
#define PMIH010X_ADC5_GEN4_AMUX5_GPIO18 (PMI_SID | ADC5_GEN4_AMUX5_GPIO)
#define PMIH010X_ADC5_GEN4_ICHG_FB (PMI_SID | ADC5_GEN4_ICHG_FB)
/* 10k pull-up */
#define PMIH010X_ADC5_GEN4_AMUX_THM1_BAT_THERM_10K_PU (PMI_SID | ADC5_GEN4_AMUX1_THM_10K_PU)
#define PMIH010X_ADC5_GEN4_AMUX_THM2_BAT_ID_10K_PU (PMI_SID | ADC5_GEN4_AMUX2_THM_10K_PU)
#define PMIH010X_ADC5_GEN4_AMUX_THM3_SMB_TEMP_V_10K_PU (PMI_SID | ADC5_GEN4_AMUX3_THM_10K_PU)
#define PMIH010X_ADC5_GEN4_AMUX_THM4_USB_THERM_10K_PU (PMI_SID | ADC5_GEN4_AMUX4_THM_10K_PU)
#define PMIH010X_ADC5_GEN4_AMUX_THM5_OPTION_10K_PU (PMI_SID | ADC5_GEN4_AMUX5_THM_10K_PU)
#define PMIH010X_ADC5_GEN4_AMUX_THM6_OPTION2_10K_PU (PMI_SID | ADC5_GEN4_AMUX6_THM_10K_PU)
#define PMIH010X_ADC5_GEN4_AMUX1_GPIO6_10K_PU (PMI_SID | ADC5_GEN4_AMUX1_GPIO_10K_PU)
#define PMIH010X_ADC5_GEN4_AMUX2_BAT2_ID_10K_PU (PMI_SID | ADC5_GEN4_AMUX2_GPIO_10K_PU)
#define PMIH010X_ADC5_GEN4_AMUX3_BAT2_THERM_10K_PU (PMI_SID | ADC5_GEN4_AMUX3_GPIO_10K_PU)
#define PMIH010X_ADC5_GEN4_AMUX4_GPIO12_10K_PU (PMI_SID | ADC5_GEN4_AMUX4_GPIO_10K_PU)
#define PMIH010X_ADC5_GEN4_USBC_MUX_10K_PU (PMI_SID | ADC5_GEN4_USBC_MUX_10K_PU)
#define PMIH010X_ADC5_GEN4_AMUX5_GPIO18_10K_PU (PMI_SID | ADC5_GEN4_AMUX5_GPIO_10K_PU)
/* 100k pull-up */
#define PMIH010X_ADC5_GEN4_AMUX_THM1_BAT_THERM_100K_PU (PMI_SID | ADC5_GEN4_AMUX1_THM_100K_PU)
#define PMIH010X_ADC5_GEN4_AMUX_THM2_BAT_ID_100K_PU (PMI_SID | ADC5_GEN4_AMUX2_THM_100K_PU)
#define PMIH010X_ADC5_GEN4_AMUX_THM3_SMB_TEMP_V_100K_PU (PMI_SID | ADC5_GEN4_AMUX3_THM_100K_PU)
#define PMIH010X_ADC5_GEN4_AMUX_THM4_USB_THERM_100K_PU (PMI_SID | ADC5_GEN4_AMUX4_THM_100K_PU)
#define PMIH010X_ADC5_GEN4_AMUX_THM5_OPTION_100K_PU (PMI_SID | ADC5_GEN4_AMUX5_THM_100K_PU)
#define PMIH010X_ADC5_GEN4_AMUX_THM6_OPTION2_100K_PU (PMI_SID | ADC5_GEN4_AMUX6_THM_100K_PU)
#define PMIH010X_ADC5_GEN4_AMUX1_GPIO6_100K_PU (PMI_SID | ADC5_GEN4_AMUX1_GPIO_100K_PU)
#define PMIH010X_ADC5_GEN4_AMUX2_BAT2_ID_100K_PU (PMI_SID | ADC5_GEN4_AMUX2_GPIO_100K_PU)
#define PMIH010X_ADC5_GEN4_AMUX3_BAT2_THERM_100K_PU (PMI_SID | ADC5_GEN4_AMUX3_GPIO_100K_PU)
#define PMIH010X_ADC5_GEN4_AMUX4_GPIO12_100K_PU (PMI_SID | ADC5_GEN4_AMUX4_GPIO_100K_PU)
#define PMIH010X_ADC5_GEN4_USBC_MUX_100K_PU (PMI_SID | ADC5_GEN4_USBC_MUX_100K_PU)
#define PMIH010X_ADC5_GEN4_AMUX5_GPIO18_100K_PU (PMI_SID | ADC5_GEN4_AMUX5_GPIO_100K_PU)
/* 400k pull-up */
#define PMIH010X_ADC5_GEN4_AMUX_THM1_BAT_THERM_400K_PU (PMI_SID | ADC5_GEN4_AMUX1_THM_400K_PU)
#define PMIH010X_ADC5_GEN4_AMUX_THM2_BAT_ID_400K_PU (PMI_SID | ADC5_GEN4_AMUX2_THM_400K_PU)
#define PMIH010X_ADC5_GEN4_AMUX_THM3_SMB_TEMP_V_400K_PU (PMI_SID | ADC5_GEN4_AMUX3_THM_400K_PU)
#define PMIH010X_ADC5_GEN4_AMUX_THM4_USB_THERM_400K_PU (PMI_SID | ADC5_GEN4_AMUX4_THM_400K_PU)
#define PMIH010X_ADC5_GEN4_AMUX_THM5_OPTION_400K_PU (PMI_SID | ADC5_GEN4_AMUX5_THM_400K_PU)
#define PMIH010X_ADC5_GEN4_AMUX_THM6_OPTION2_400K_PU (PMI_SID | ADC5_GEN4_AMUX6_THM_400K_PU)
#define PMIH010X_ADC5_GEN4_AMUX1_GPIO6_400K_PU (PMI_SID | ADC5_GEN4_AMUX1_GPIO_400K_PU)
#define PMIH010X_ADC5_GEN4_AMUX2_BAT2_ID_400K_PU (PMI_SID | ADC5_GEN4_AMUX2_GPIO_400K_PU)
#define PMIH010X_ADC5_GEN4_AMUX3_BAT2_THERM_400K_PU (PMI_SID | ADC5_GEN4_AMUX3_GPIO_400K_PU)
#define PMIH010X_ADC5_GEN4_AMUX4_GPIO12_400K_PU (PMI_SID | ADC5_GEN4_AMUX4_GPIO_400K_PU)
#define PMIH010X_ADC5_GEN4_USBC_MUX_400K_PU (PMI_SID | ADC5_GEN4_USBC_MUX_400K_PU)
#define PMIH010X_ADC5_GEN4_AMUX5_GPIO18_400K_PU (PMI_SID | ADC5_GEN4_AMUX5_GPIO_400K_PU)
/* 1/3 Divider */
#define PMIH010X_ADC5_GEN4_AMUX1_GPIO6_DIV3 (PMI_SID | ADC5_GEN4_AMUX1_GPIO_DIV3)
#define PMIH010X_ADC5_GEN4_VPH_PWR (PMI_SID | ADC5_GEN4_VPH_PWR)
#define PMIH010X_ADC5_GEN4_VBAT_SNS_QBG (PMI_SID | ADC5_GEN4_VBAT_SNS_QBG)
#define PMIH010X_ADC5_GEN4_VBAT_SNS_CHG (PMI_SID | ADC5_GEN4_VBAT_SNS_CHG)
#define PMIH010X_ADC5_GEN4_VBAT_2S_MID_QBG (PMI_SID | ADC5_GEN4_VBAT_2S_MID_QBG)
#define PMIH010X_ADC5_GEN4_VPH2_PWR (PMI_SID | ADC5_GEN4_VPH2_PWR)
#define PMIH010X_ADC5_GEN4_VBAT_2S_MID_CHGR_DIV3 (PMI_SID | ADC5_GEN4_VBAT_2S_MID_CHGR_DIV3)
#define PMIH010X_ADC5_GEN4_VBAT_2S_MID2 (PMI_SID | ADC5_GEN4_VBAT_2S_MID2)
#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMIH010X_H */

30
include/dt-bindings/iio/qcom,spmi-adc7-pm6450.h Normal file
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@@ -0,0 +1,30 @@
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
/*
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM6450_H
#define _DT_BINDINGS_QCOM_SPMI_VADC_PM6450_H
#ifndef PM6450_SID
#define PM6450_SID 1
#endif
/* ADC channels for PM6450_ADC for PMIC7 */
#define PM6450_ADC7_REF_GND (PM6450_SID << 8 | 0x0)
#define PM6450_ADC7_1P25VREF (PM6450_SID << 8 | 0x01)
#define PM6450_ADC7_VREF_VADC (PM6450_SID << 8 | 0x02)
#define PM6450_ADC7_DIE_TEMP (PM6450_SID << 8 | 0x03)
#define PM6450_ADC7_AMUX1_GPIO2 (PM6450_SID << 8 | 0x0a)
#define PM6450_ADC7_AMUX2_GPIO3 (PM6450_SID << 8 | 0x0b)
#define PM6450_ADC7_AMUX3_GPIO4 (PM6450_SID << 8 | 0x0c)
#define PM6450_ADC7_AMUX4_GPIO5 (PM6450_SID << 8 | 0x0d)
/* 100k pull-up2 */
#define PM6450_ADC7_AMUX1_GPIO2_100K_PU (PM6450_SID << 8 | 0x4a)
#define PM6450_ADC7_AMUX2_GPIO3_100K_PU (PM6450_SID << 8 | 0x4b)
#define PM6450_ADC7_AMUX3_GPIO4_100K_PU (PM6450_SID << 8 | 0x4c)
#define PM6450_ADC7_AMUX4_GPIO5_100K_PU (PM6450_SID << 8 | 0x4d)
#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM6450_H */

1
include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h
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@@ -86,5 +86,6 @@
#define PM8350B_ADC7_SBUx (PM8350B_SID << 8 | ADC7_SBU)
#define PM8350B_ADC7_VBAT_2S_MID (PM8350B_SID << 8 | ADC7_VBAT_2S_MID)
#define PM8350B_ADC7_ICHG_FB (PM8350B_SID << 8 | 0xa1)
#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H */

42
include/dt-bindings/iio/qcom,spmi-adc7-smb139x.h Normal file
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@@ -0,0 +1,42 @@
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
/*
* Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_SMB139X_H
#define _DT_BINDINGS_QCOM_SPMI_VADC_SMB139X_H
#ifndef SMB139x_1_SID
#define SMB139x_1_SID 0x0b
#endif
#ifndef SMB139x_2_SID
#define SMB139x_2_SID 0x0c
#endif
#ifndef SMB1394_1_SID
#define SMB1394_1_SID 0x09
#endif
#ifndef SMB1394_2_SID
#define SMB1394_2_SID 0x0b
#endif
#define SMB139x_1_ADC7_SMB_TEMP (SMB139x_1_SID << 8 | 0x06)
#define SMB139x_1_ADC7_ICHG_SMB (SMB139x_1_SID << 8 | 0x18)
#define SMB139x_1_ADC7_IIN_SMB (SMB139x_1_SID << 8 | 0x19)
#define SMB139x_2_ADC7_SMB_TEMP (SMB139x_2_SID << 8 | 0x06)
#define SMB139x_2_ADC7_ICHG_SMB (SMB139x_2_SID << 8 | 0x18)
#define SMB139x_2_ADC7_IIN_SMB (SMB139x_2_SID << 8 | 0x19)
#define SMB1394_1_ADC7_SMB_TEMP (SMB1394_1_SID << 8 | 0x06)
#define SMB1394_1_ADC7_ICHG_SMB (SMB1394_1_SID << 8 | 0x18)
#define SMB1394_1_ADC7_IIN_SMB (SMB1394_1_SID << 8 | 0x19)
#define SMB1394_2_ADC7_SMB_TEMP (SMB1394_2_SID << 8 | 0x06)
#define SMB1394_2_ADC7_ICHG_SMB (SMB1394_2_SID << 8 | 0x18)
#define SMB1394_2_ADC7_IIN_SMB (SMB1394_2_SID << 8 | 0x19)
#endif

198
include/dt-bindings/iio/qcom,spmi-vadc.h
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@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved.
* Copyright (c) 2012-2014,2018-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H
@@ -245,6 +246,9 @@
#define ADC7_CC1_ID 0x13
#define ADC7_VREF_BAT_THERM 0x15
#define ADC7_IIN_FB 0x17
#define ADC7_ICHG_SMB 0x18
#define ADC7_IIN_SMB 0x19
#define ADC7_ICHG_FB 0xa1
/* 30k pull-up1 */
#define ADC7_AMUX_THM1_30K_PU 0x24
@@ -297,4 +301,196 @@
#define ADC7_SBUx 0x94
#define ADC7_VBAT_2S_MID 0x96
/* ADC channels for PMIC5 Gen3 */
#define ADC5_GEN3_OFFSET_REF 0x00
#define ADC5_GEN3_1P25VREF 0x01
#define ADC5_GEN3_VREF_VADC 0x02
#define ADC5_GEN3_DIE_TEMP 0x03
#define ADC5_GEN3_AMUX1_THM 0x04
#define ADC5_GEN3_AMUX2_THM 0x05
#define ADC5_GEN3_AMUX3_THM 0x06
#define ADC5_GEN3_AMUX4_THM 0x07
#define ADC5_GEN3_AMUX5_THM 0x08
#define ADC5_GEN3_AMUX6_THM 0x09
#define ADC5_GEN3_AMUX1_GPIO 0x0a
#define ADC5_GEN3_AMUX2_GPIO 0x0b
#define ADC5_GEN3_AMUX3_GPIO 0x0c
#define ADC5_GEN3_AMUX4_GPIO 0x0d
#define ADC5_GEN3_CHG_TEMP 0x10
#define ADC5_GEN3_USB_SNS_V_16 0x11
#define ADC5_GEN3_VIN_DIV16_MUX 0x12
#define ADC5_GEN3_VREF_BAT_THERM 0x15
#define ADC5_GEN3_IIN_FB 0x17
#define ADC5_GEN3_TEMP_ALARM_LITE 0x18
#define ADC5_GEN3_IIN_SMB 0x19
#define ADC5_GEN3_ICHG_SMB 0x1b
#define ADC5_GEN3_ICHG_FB 0xa1
/* 30k pull-up1 */
#define ADC5_GEN3_AMUX1_THM_30K_PU 0x24
#define ADC5_GEN3_AMUX2_THM_30K_PU 0x25
#define ADC5_GEN3_AMUX3_THM_30K_PU 0x26
#define ADC5_GEN3_AMUX4_THM_30K_PU 0x27
#define ADC5_GEN3_AMUX5_THM_30K_PU 0x28
#define ADC5_GEN3_AMUX6_THM_30K_PU 0x29
#define ADC5_GEN3_AMUX1_GPIO_30K_PU 0x2a
#define ADC5_GEN3_AMUX2_GPIO_30K_PU 0x2b
#define ADC5_GEN3_AMUX3_GPIO_30K_PU 0x2c
#define ADC5_GEN3_AMUX4_GPIO_30K_PU 0x2d
/* 100k pull-up2 */
#define ADC5_GEN3_AMUX1_THM_100K_PU 0x44
#define ADC5_GEN3_AMUX2_THM_100K_PU 0x45
#define ADC5_GEN3_AMUX3_THM_100K_PU 0x46
#define ADC5_GEN3_AMUX4_THM_100K_PU 0x47
#define ADC5_GEN3_AMUX5_THM_100K_PU 0x48
#define ADC5_GEN3_AMUX6_THM_100K_PU 0x49
#define ADC5_GEN3_AMUX1_GPIO_100K_PU 0x4a
#define ADC5_GEN3_AMUX2_GPIO_100K_PU 0x4b
#define ADC5_GEN3_AMUX3_GPIO_100K_PU 0x4c
#define ADC5_GEN3_AMUX4_GPIO_100K_PU 0x4d
/* 400k pull-up3 */
#define ADC5_GEN3_AMUX1_THM_400K_PU 0x64
#define ADC5_GEN3_AMUX2_THM_400K_PU 0x65
#define ADC5_GEN3_AMUX3_THM_400K_PU 0x66
#define ADC5_GEN3_AMUX4_THM_400K_PU 0x67
#define ADC5_GEN3_AMUX5_THM_400K_PU 0x68
#define ADC5_GEN3_AMUX6_THM_400K_PU 0x69
#define ADC5_GEN3_AMUX1_GPIO_400K_PU 0x6a
#define ADC5_GEN3_AMUX2_GPIO_400K_PU 0x6b
#define ADC5_GEN3_AMUX3_GPIO_400K_PU 0x6c
#define ADC5_GEN3_AMUX4_GPIO_400K_PU 0x6d
/* 1/3 Divider */
#define ADC5_GEN3_AMUX1_GPIO_DIV3 0x8a
#define ADC5_GEN3_AMUX2_GPIO_DIV3 0x8b
#define ADC5_GEN3_AMUX3_GPIO_DIV3 0x8c
#define ADC5_GEN3_VPH_PWR 0x8e
#define ADC5_GEN3_VBAT_SNS_QBG 0x8f
#define ADC5_GEN3_VBAT_SNS_CHGR 0x94
#define ADC5_GEN3_VBAT_2S_MID_QBG 0x96
#define ADC5_GEN3_VBAT_2S_MID_CHGR 0x9d
#define ADC5_OFFSET_EXT2 0xf8
/* ADC channels for PMIC5 Gen4 */
#define ADC5_GEN4_OFFSET_REF 0x00
#define ADC5_GEN4_1P25VREF 0x01
#define ADC5_GEN4_VREF_VADC 0x02
#define ADC5_GEN4_DIE_TEMP 0x03
#define ADC5_GEN4_AMUX1_THM 0x04
#define ADC5_GEN4_AMUX2_THM 0x05
#define ADC5_GEN4_AMUX3_THM 0x06
#define ADC5_GEN4_AMUX4_THM 0x07
#define ADC5_GEN4_AMUX5_THM 0x08
#define ADC5_GEN4_AMUX6_THM 0x09
#define ADC5_GEN4_AMUX1_GPIO 0x0a
#define ADC5_GEN4_AMUX2_GPIO 0x0b
#define ADC5_GEN4_AMUX3_GPIO 0x0c
#define ADC5_GEN4_AMUX4_GPIO 0x0d
#define ADC5_GEN4_AMUX5_GPIO 0x1e
#define ADC5_GEN4_CHG_TEMP 0x10
#define ADC5_GEN4_USB_SNS_DIV20 0x11
#define ADC5_GEN4_VIN_DIV20_MUX 0x12
#define ADC5_GEN4_USBC_MUX 0x13
#define ADC5_GEN4_VREF_BAT_THERM 0x15
#define ADC5_GEN4_IIN 0x17
#define ADC5_GEN4_TEMP_ALARM_LITE 0x18
#define ADC5_GEN4_VREF_BAT2_THERM 0x1a
#define ADC5_GEN4_ATEST1 0x1b
#define ADC5_GEN4_ATEST2 0x1c
#define ADC5_GEN4_VBAT_2S_MID_CHGR 0x1d
/* 10k pull-up */
#define ADC5_GEN4_AMUX1_THM_10K_PU 0x24
#define ADC5_GEN4_AMUX2_THM_10K_PU 0x25
#define ADC5_GEN4_AMUX3_THM_10K_PU 0x26
#define ADC5_GEN4_AMUX4_THM_10K_PU 0x27
#define ADC5_GEN4_AMUX5_THM_10K_PU 0x28
#define ADC5_GEN4_AMUX6_THM_10K_PU 0x29
#define ADC5_GEN4_AMUX1_GPIO_10K_PU 0x2a
#define ADC5_GEN4_AMUX2_GPIO_10K_PU 0x2b
#define ADC5_GEN4_AMUX3_GPIO_10K_PU 0x2c
#define ADC5_GEN4_AMUX4_GPIO_10K_PU 0x2d
#define ADC5_GEN4_USBC_MUX_10K_PU 0x33
#define ADC5_GEN4_AMUX5_GPIO_10K_PU 0x3e
/* 100k pull-up */
#define ADC5_GEN4_AMUX1_THM_100K_PU 0x44
#define ADC5_GEN4_AMUX2_THM_100K_PU 0x45
#define ADC5_GEN4_AMUX3_THM_100K_PU 0x46
#define ADC5_GEN4_AMUX4_THM_100K_PU 0x47
#define ADC5_GEN4_AMUX5_THM_100K_PU 0x48
#define ADC5_GEN4_AMUX6_THM_100K_PU 0x49
#define ADC5_GEN4_AMUX1_GPIO_100K_PU 0x4a
#define ADC5_GEN4_AMUX2_GPIO_100K_PU 0x4b
#define ADC5_GEN4_AMUX3_GPIO_100K_PU 0x4c
#define ADC5_GEN4_AMUX4_GPIO_100K_PU 0x4d
#define ADC5_GEN4_USBC_MUX_100K_PU 0x53
#define ADC5_GEN4_AMUX5_GPIO_100K_PU 0x5e
/* 400k pull-up */
#define ADC5_GEN4_AMUX1_THM_400K_PU 0x64
#define ADC5_GEN4_AMUX2_THM_400K_PU 0x65
#define ADC5_GEN4_AMUX3_THM_400K_PU 0x66
#define ADC5_GEN4_AMUX4_THM_400K_PU 0x67
#define ADC5_GEN4_AMUX5_THM_400K_PU 0x68
#define ADC5_GEN4_AMUX6_THM_400K_PU 0x69
#define ADC5_GEN4_AMUX1_GPIO_400K_PU 0x6a
#define ADC5_GEN4_AMUX2_GPIO_400K_PU 0x6b
#define ADC5_GEN4_AMUX3_GPIO_400K_PU 0x6c
#define ADC5_GEN4_AMUX4_GPIO_400K_PU 0x6d
#define ADC5_GEN4_USBC_MUX_400K_PU 0x73
#define ADC5_GEN4_AMUX5_GPIO_400K_PU 0x7e
/* 1/3 Divider */
#define ADC5_GEN4_AMUX1_GPIO_DIV3 0x8a
#define ADC5_GEN4_VPH_PWR 0x8e
#define ADC5_GEN4_VBAT_SNS_QBG 0x8f
#define ADC5_GEN4_VBAT_SNS_CHG 0x94
#define ADC5_GEN4_VBAT_2S_MID_QBG 0x96
#define ADC5_GEN4_VPH2_PWR 0x99
#define ADC5_GEN4_VBAT_2S_MID_CHGR_DIV3 0x9d
#define ADC5_GEN4_VBAT_2S_MID2 0x9f
#define ADC5_GEN4_ICHG_FB 0xa1
/* VADC scale function index */
#define ADC_SCALE_DEFAULT 0
#define ADC_SCALE_THERM_100K_PULLUP 1
#define ADC_SCALE_PMIC_THERM 2
#define ADC_SCALE_XOTHERM 3
#define ADC_SCALE_PMI_CHG_TEMP 4
#define ADC_SCALE_HW_CALIB_DEFAULT 5
#define ADC_SCALE_HW_CALIB_THERM_100K_PULLUP 6
#define ADC_SCALE_HW_CALIB_XOTHERM 7
#define ADC_SCALE_HW_CALIB_THERM_100K_PU_PM7 8
#define ADC_SCALE_HW_CALIB_PMIC_THERM 9
#define ADC_SCALE_HW_CALIB_PMIC_THERM_PM7 10
#define ADC_SCALE_HW_CALIB_PM5_CHG_TEMP 11
#define ADC_SCALE_HW_CALIB_PM5_SMB_TEMP 12
#define ADC_SCALE_HW_CALIB_BATT_THERM_100K 13
#define ADC_SCALE_HW_CALIB_BATT_THERM_30K 14
#define ADC_SCALE_HW_CALIB_BATT_THERM_400K 15
#define ADC_SCALE_HW_CALIB_PM5_SMB1398_TEMP 16
#define ADC_SCALE_HW_CALIB_PM7_SMB_TEMP 17
#define ADC_SCALE_HW_CALIB_PM7_CHG_TEMP 18
#define ADC_SCALE_HW_CALIB_CUR 19
#define ADC_SCALE_HW_CALIB_CUR_RAW 20
#define ADC_SCALE_HW_CALIB_PM2250_S3_DIE_TEMP 21
#define ADC_SCALE_HW_CALIB_PM5_CUR 22
#define ADC_SCALE_HW_CALIB_PM5_GEN3_BATT_THERM_100K 23
#define ADC_SCALE_HW_CALIB_PM5_GEN3_BATT_ID_100K 24
#define ADC_SCALE_HW_CALIB_PM5_GEN3_USB_IN_I 25
#define ADC_SCALE_HW_CALIB_PM5_GEN4_BATT_THERM_10K 26
#define ADC_SCALE_HW_CALIB_PM5_GEN4_BATT_ID_10K 27
#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */

174
include/dt-bindings/iio/qti_power_supply_iio.h Normal file
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@@ -0,0 +1,174 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __QTI_POWER_SUPPLY_IIO_H__
#define __QTI_POWER_SUPPLY_IIO_H__
/* PSY_IIO properties */
/* USB */
#define PSY_IIO_PD_CURRENT_MAX 0x00
#define PSY_IIO_TYPEC_MODE 0x01
#define PSY_IIO_TYPEC_POWER_ROLE 0x02
#define PSY_IIO_TYPEC_CC_ORIENTATION 0x03
#define PSY_IIO_PD_ACTIVE 0x04
#define PSY_IIO_USB_INPUT_CURRENT_SETTLED 0x05
#define PSY_IIO_INPUT_CURRENT_NOW 0x06
#define PSY_IIO_PE_START 0x07
#define PSY_IIO_CTM_CURRENT_MAX 0x08
#define PSY_IIO_HW_CURRENT_MAX 0x09
#define PSY_IIO_USB_REAL_TYPE 0x0a
#define PSY_IIO_PD_VOLTAGE_MAX 0x0b
#define PSY_IIO_PD_VOLTAGE_MIN 0x0c
#define PSY_IIO_CONNECTOR_TYPE 0x0d
#define PSY_IIO_CONNECTOR_HEALTH 0x0e
#define PSY_IIO_VOLTAGE_MAX_LIMIT 0x0f
#define PSY_IIO_SMB_EN_MODE 0x10
#define PSY_IIO_SMB_EN_REASON 0x11
#define PSY_IIO_ADAPTER_CC_MODE 0x12
#define PSY_IIO_MOISTURE_DETECTED 0x13
#define PSY_IIO_HVDCP_OPTI_ALLOWED 0x14
#define PSY_IIO_QC_OPTI_DISABLE 0x15
#define PSY_IIO_VOLTAGE_VPH 0x16
#define PSY_IIO_THERM_ICL_LIMIT 0x17
#define PSY_IIO_SKIN_HEALTH 0x18
#define PSY_IIO_APSD_RERUN 0x19
#define PSY_IIO_APSD_TIMEOUT 0x1a
#define PSY_IIO_CHARGER_STATUS 0x1b
#define PSY_IIO_USB_INPUT_VOLTAGE_SETTLED 0x1c
#define PSY_IIO_TYPEC_SRC_RP 0x1d
#define PSY_IIO_PD_IN_HARD_RESET 0x1e
#define PSY_IIO_PD_USB_SUSPEND_SUPPORTED 0x1f
#define PSY_IIO_PR_SWAP 0x20
/* MAIN */
#define PSY_IIO_MAIN_INPUT_CURRENT_SETTLED 0x21
#define PSY_IIO_MAIN_INPUT_VOLTAGE_SETTLED 0x22
#define PSY_IIO_FCC_DELTA 0x23
#define PSY_IIO_FLASH_ACTIVE 0x24
#define PSY_IIO_FLASH_TRIGGER 0x25
#define PSY_IIO_TOGGLE_STAT 0x26
#define PSY_IIO_MAIN_FCC_MAX 0x27
#define PSY_IIO_IRQ_STATUS 0x28
#define PSY_IIO_FORCE_MAIN_FCC 0x29
#define PSY_IIO_FORCE_MAIN_ICL 0x2a
#define PSY_IIO_COMP_CLAMP_LEVEL 0x2b
#define PSY_IIO_HOT_TEMP 0x2c
#define PSY_IIO_VOLTAGE_MAX 0x2d
#define PSY_IIO_CONSTANT_CHARGE_CURRENT_MAX 0x2e
#define PSY_IIO_CURRENT_MAX 0x2f
#define PSY_IIO_HEALTH 0x30
/* DC */
#define PSY_IIO_INPUT_VOLTAGE_REGULATION 0x31
#define PSY_IIO_DC_REAL_TYPE 0x32
#define PSY_IIO_DC_RESET 0x33
#define PSY_IIO_AICL_DONE 0x34
/* BATTERY */
#define PSY_IIO_CHARGER_TEMP 0x35
#define PSY_IIO_CHARGER_TEMP_MAX 0x36
#define PSY_IIO_INPUT_CURRENT_LIMITED 0x37
#define PSY_IIO_SW_JEITA_ENABLED 0x38
#define PSY_IIO_CHARGE_DONE 0x39
#define PSY_IIO_PARALLEL_DISABLE 0x3a
#define PSY_IIO_SET_SHIP_MODE 0x3b
#define PSY_IIO_DIE_HEALTH 0x3c
#define PSY_IIO_RERUN_AICL 0x3d
#define PSY_IIO_DP_DM 0x3e
#define PSY_IIO_RECHARGE_SOC 0x3f
#define PSY_IIO_FORCE_RECHARGE 0x40
#define PSY_IIO_FCC_STEPPER_ENABLE 0x41
/* BMS */
#define PSY_IIO_CAPACITY 0x42
#define PSY_IIO_CAPACITY_RAW 0x43
#define PSY_IIO_REAL_CAPACITY 0x44
#define PSY_IIO_TEMP 0x45
#define PSY_IIO_VOLTAGE_NOW 0x46
#define PSY_IIO_VOLTAGE_OCV 0x47
#define PSY_IIO_CURRENT_NOW 0x48
#define PSY_IIO_CHARGE_COUNTER 0x49
#define PSY_IIO_RESISTANCE 0x4a
#define PSY_IIO_RESISTANCE_ID 0x4b
#define PSY_IIO_SOC_REPORTING_READY 0x4c
#define PSY_IIO_RESISTANCE_CAPACITIVE 0x4d
#define PSY_IIO_DEBUG_BATTERY 0x4e
#define PSY_IIO_VOLTAGE_MIN 0x4f
#define PSY_IIO_BATT_FULL_CURRENT 0x50
#define PSY_IIO_BATT_PROFILE_VERSION 0x51
#define PSY_IIO_CYCLE_COUNT 0x52
#define PSY_IIO_CHARGE_FULL 0x53
#define PSY_IIO_CHARGE_FULL_DESIGN 0x54
#define PSY_IIO_TIME_TO_FULL_AVG 0x55
#define PSY_IIO_TIME_TO_FULL_NOW 0x56
#define PSY_IIO_TIME_TO_EMPTY_AVG 0x57
#define PSY_IIO_ESR_ACTUAL 0x58
#define PSY_IIO_ESR_NOMINAL 0x59
#define PSY_IIO_SOH 0x5a
#define PSY_IIO_CC_SOC 0x5b
#define PSY_IIO_FG_RESET 0x5c
#define PSY_IIO_VOLTAGE_AVG 0x5d
#define PSY_IIO_CURRENT_AVG 0x5e
#define PSY_IIO_POWER_AVG 0x5f
#define PSY_IIO_POWER_NOW 0x60
#define PSY_IIO_SCALE_MODE_EN 0x61
#define PSY_IIO_BATT_AGE_LEVEL 0x62
#define PSY_IIO_FG_TYPE 0x63
#define PSY_IIO_TYPEC_ACCESSORY_MODE 0x64
/* CHARGE PUMP */
#define PSY_IIO_CP_STATUS1 0x65
#define PSY_IIO_CP_STATUS2 0x66
#define PSY_IIO_CP_ENABLE 0x67
#define PSY_IIO_CP_SWITCHER_EN 0x68
#define PSY_IIO_CP_DIE_TEMP 0x69
#define PSY_IIO_CP_ISNS 0x6a
#define PSY_IIO_CP_ISNS_SLAVE 0x6b
#define PSY_IIO_CP_TOGGLE_SWITCHER 0x6c
#define PSY_IIO_CP_ILIM 0x6d
#define PSY_IIO_CHIP_VERSION 0x6e
#define PSY_IIO_PARALLEL_MODE 0x6f
#define PSY_IIO_PARALLEL_OUTPUT_MODE 0x70
#define PSY_IIO_MIN_ICL 0x71
#define PSY_IIO_CP_INPUT_CURRENT_MAX 0x72
#define PSY_IIO_CURRENT_CAPABILITY 0x73
/* SMB1355 Parallel */
#define PSY_IIO_CHARGE_TYPE 0x74
#define PSY_IIO_ONLINE 0x75
#define PSY_IIO_CHARGING_ENABLED 0x76
#define PSY_IIO_PIN_ENABLED 0x77
#define PSY_IIO_INPUT_SUSPEND 0x78
#define PSY_IIO_PARALLEL_BATFET_MODE 0x79
#define PSY_IIO_PARALLEL_FCC_MAX 0x7a
/* USB */
#define PSY_IIO_MOISTURE_DETECTION_EN 0x7b
/* BMS */
#define PSY_IIO_CLEAR_SOH 0x7c
#define PSY_IIO_SYS_SOC 0x7d
/* QNOVO5 */
#define PSY_IIO_VOLTAGE_QNOVO 0x7e
#define PSY_IIO_CURRENT_QNOVO 0x7f
/* FG */
#define PSY_IIO_CHARGE_COUNTER_SHADOW 0x80
#define PSY_IIO_CHARGE_NOW_RAW 0x81
#define PSY_IIO_CYCLE_COUNTS 0x82
#define PSY_IIO_CC_STEP 0x83
#define PSY_IIO_CC_STEP_SEL 0x84
#define PSY_IIO_VOLTAGE_MAX_DESIGN 0x85
#define PSY_IIO_CHARGE_NOW 0x86
#define PSY_IIO_CONSTANT_CHARGE_VOLTAGE 0x87
#define PSY_IIO_CALIBRATE 0x88
#endif /* __QTI_POWER_SUPPLY_IIO_H__ */

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include/dt-bindings/input/qcom,hv-haptics.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020 The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
/* definitions for drive waveform shape */
#define WF_SQUARE 0 /* LRA only */
#define WF_SINE 1 /* LRA only */
#define WF_NO_MODULATION 2 /* ERM only */
/* definitions for brake mode */
#define BRAKE_OPEN_LOOP 0
#define BRAKE_CLOSE_LOOP 1
#define BRAKE_PREDICTIVE 2
#define BRAKE_AUTO 3
/* definitions for brake sine signal gain */
#define BRAKE_SINE_GAIN_X1 0
#define BRAKE_SINE_GAIN_X2 1
#define BRAKE_SINE_GAIN_X4 2
#define BRAKE_SINE_GAIN_X8 3
/* definitions for pattern sample period */
#define S_PERIOD_T_LRA 0
#define S_PERIOD_T_LRA_DIV_2 1
#define S_PERIOD_T_LRA_DIV_4 2
#define S_PERIOD_T_LRA_DIV_8 3
#define S_PERIOD_T_LRA_X_2 4
#define S_PERIOD_T_LRA_X_4 5
#define S_PERIOD_T_LRA_X_8 6
/* F_8KHZ to F_48KHZ periods can only be specified for FIFO based effects */
#define S_PERIOD_F_8KHZ 8
#define S_PERIOD_F_16KHZ 9
#define S_PERIOD_F_24KHZ 10
#define S_PERIOD_F_32KHZ 11
#define S_PERIOD_F_44P1KHZ 12
#define S_PERIOD_F_48KHZ 13

23
include/dt-bindings/input/qcom,qpnp-power-on.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2018-2019,2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_INPUT_QCOM_POWER_ON_H
#define _DT_BINDINGS_INPUT_QCOM_POWER_ON_H
/* PMIC PON peripheral logical power on types: */
#define PON_POWER_ON_TYPE_KPDPWR 0
#define PON_POWER_ON_TYPE_RESIN 1
#define PON_POWER_ON_TYPE_CBLPWR 2
#define PON_POWER_ON_TYPE_KPDPWR_RESIN 3
/* PMIC PON peripheral physical power off types: */
#define PON_POWER_OFF_TYPE_WARM_RESET 0x01
#define PON_POWER_OFF_TYPE_SHUTDOWN 0x04
#define PON_POWER_OFF_TYPE_DVDD_SHUTDOWN 0x05
#define PON_POWER_OFF_TYPE_HARD_RESET 0x07
#define PON_POWER_OFF_TYPE_DVDD_HARD_RESET 0x08
#endif

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include/dt-bindings/interconnect/qcom,monaco.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MONACO_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_MONACO_H
#define MASTER_AMPSS_M0 0
#define MASTER_SNOC_BIMC_RT 1
#define MASTER_SNOC_BIMC_NRT 2
#define SNOC_BIMC_MAS 3
#define MASTER_GRAPHICS_3D 4
#define MASTER_TCU_0 5
#define MASTER_QUP_CORE_0 6
#define MASTER_CRYPTO_CORE0 7
#define SNOC_CNOC_MAS 8
#define MASTER_QDSS_DAP 9
#define MASTER_CAMNOC_SF 10
#define MASTER_VIDEO_P0 11
#define MASTER_VIDEO_PROC 12
#define MASTER_CAMNOC_HF 13
#define MASTER_MDP_PORT0 14
#define MASTER_SNOC_CFG 15
#define MASTER_TIC 16
#define MASTER_ANOC_SNOC 17
#define BIMC_SNOC_MAS 18
#define MASTER_PIMEM 19
#define MASTER_QDSS_BAM 20
#define MASTER_QUP_0 21
#define CNOC_SNOC_MAS 22
#define MASTER_IPA 23
#define MASTER_QDSS_ETR 24
#define MASTER_SDCC_1 25
#define MASTER_SDCC_2 26
#define MASTER_USB3 27
#define MASTER_CAMNOC_SF_SNOC 28
#define MASTER_CAMNOC_HF_SNOC 29
#define MASTER_MDP_PORT0_SNOC 30
#define MASTER_VIDEO_P0_SNOC 31
#define MASTER_VIDEO_PROC_SNOC 32
#define MASTER_SNOC_RT 33
#define MASTER_SNOC_NRT 34
#define SLAVE_EBI_CH0 512
#define BIMC_SNOC_SLV 513
#define SLAVE_QUP_CORE_0 514
#define SLAVE_AHB2PHY_USB 515
#define SLAVE_BIMC_CFG 516
#define SLAVE_BOOT_ROM 517
#define SLAVE_CAMERA_NRT_THROTTLE_CFG 518
#define SLAVE_CAMERA_RT_THROTTLE_CFG 519
#define SLAVE_CAMERA_CFG 520
#define SLAVE_CLK_CTL 521
#define SLAVE_RBCPR_CX_CFG 522
#define SLAVE_RBCPR_MXA_CFG 523
#define SLAVE_RBCPR_MXC_CFG 524
#define SLAVE_CRYPTO_0_CFG 525
#define SLAVE_DCC_CFG 526
#define SLAVE_DDR_PHY_CFG 527
#define SLAVE_DDR_SS_CFG 528
#define SLAVE_DDRSS_THROTTLE_CFG 529
#define SLAVE_DISPLAY_CFG 530
#define SLAVE_DISPLAY_THROTTLE_CFG 531
#define SLAVE_GPU_CFG 532
#define SLAVE_HWKM 533
#define SLAVE_IMEM_CFG 534
#define SLAVE_IPA_CFG 535
#define SLAVE_LPASS 536
#define SLAVE_MAPSS 537
#define SLAVE_MDSP_MPU_CFG 538
#define SLAVE_MESSAGE_RAM 539
#define SLAVE_CNOC_MSS 540
#define SLAVE_PDM 541
#define SLAVE_PIMEM_CFG 542
#define SLAVE_PKA_WRAPPER_CFG 543
#define SLAVE_PMIC_ARB 544
#define SLAVE_QDSS_CFG 545
#define SLAVE_QM_CFG 546
#define SLAVE_QM_MPU_CFG 547
#define SLAVE_QUP_0 548
#define SLAVE_RPM 549
#define SLAVE_SDCC_1 550
#define SLAVE_SDCC_2 551
#define SLAVE_SECURITY 552
#define SLAVE_SNOC_CFG 553
#define SLAVE_TCSR 554
#define SLAVE_TLMM 555
#define SLAVE_USB3 556
#define SLAVE_VENUS_CFG 557
#define SLAVE_VENUS_THROTTLE_CFG 558
#define SLAVE_VSENSE_CTRL_CFG 559
#define CNOC_SNOC_SLV 560
#define SLAVE_TCU 561
#define SLAVE_SNOC_BIMC_NRT 562
#define SLAVE_SNOC_BIMC_RT 563
#define SLAVE_APPSS 564
#define SNOC_CNOC_SLV 565
#define SLAVE_OCIMEM 566
#define SLAVE_PIMEM 567
#define SNOC_BIMC_SLV 568
#define SLAVE_SERVICE_SNOC 569
#define SLAVE_QDSS_STM 570
#define SLAVE_ANOC_SNOC 571
#define SLAVE_CAMNOC_HF_SNOC 572
#define SLAVE_MDP_PORT0_SNOC 573
#define SLAVE_CAMNOC_SF_SNOC 574
#define SLAVE_VIDEO_P0_SNOC 575
#define SLAVE_VIDEO_PROC_SNOC 576
#define SLAVE_SNOC_RT 577
#define SLAVE_SNOC_NRT 578
#endif

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include/dt-bindings/interconnect/qcom,parrot.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_PARROT_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_PARROT_H
#define MASTER_GPU_TCU 0
#define MASTER_SYS_TCU 1
#define MASTER_APPSS_PROC 2
#define MASTER_LLCC 3
#define MASTER_CNOC_LPASS_AG_NOC 4
#define MASTER_GIC_AHB 5
#define MASTER_CDSP_NOC_CFG 6
#define MASTER_QDSS_BAM 7
#define MASTER_QSPI_0 8
#define MASTER_QUP_0 9
#define MASTER_QUP_1 10
#define MASTER_A1NOC_CFG 11
#define MASTER_A2NOC_CFG 12
#define MASTER_A1NOC_SNOC 13
#define MASTER_A2NOC_SNOC 14
#define MASTER_CAMNOC_HF 15
#define MASTER_CAMNOC_ICP 16
#define MASTER_CAMNOC_SF 17
#define MASTER_CNOC2_CNOC3 18
#define MASTER_CNOC3_CNOC2 19
#define MASTER_CNOC_A2NOC 20
#define MASTER_GEM_NOC_CNOC 21
#define MASTER_GEM_NOC_PCIE_SNOC 22
#define MASTER_GFX3D 23
#define MASTER_LPASS_ANOC 24
#define MASTER_MDP 25
#define MASTER_MSS_PROC 26
#define MASTER_CNOC_MNOC_CFG 27
#define MASTER_MNOC_HF_MEM_NOC 28
#define MASTER_MNOC_SF_MEM_NOC 29
#define MASTER_COMPUTE_NOC 30
#define MASTER_ANOC_PCIE_GEM_NOC 31
#define MASTER_PCIE_ANOC_CFG 32
#define MASTER_SNOC_CFG 33
#define MASTER_SNOC_GC_MEM_NOC 34
#define MASTER_SNOC_SF_MEM_NOC 35
#define MASTER_VIDEO_P0 36
#define MASTER_VIDEO_PROC 37
#define MASTER_QUP_CORE_0 38
#define MASTER_QUP_CORE_1 39
#define MASTER_CRYPTO 40
#define MASTER_IPA 41
#define MASTER_LPASS_PROC 42
#define MASTER_CDSP_PROC 43
#define MASTER_PIMEM 44
#define MASTER_TME 45
#define MASTER_WLAN_Q6 46
#define MASTER_GIC 47
#define MASTER_PCIE_0 48
#define MASTER_QDSS_DAP 49
#define MASTER_QDSS_ETR 50
#define MASTER_QDSS_ETR_1 51
#define MASTER_SDCC_1 52
#define MASTER_SDCC_2 53
#define MASTER_UFS_MEM 54
#define MASTER_USB3_0 55
#define SLAVE_EBI1 512
#define SLAVE_AHB2PHY_SOUTH 513
#define SLAVE_AHB2PHY_NORTH 514
#define SLAVE_ANOC_THROTTLE_CFG 515
#define SLAVE_AOSS 516
#define SLAVE_APPSS 517
#define SLAVE_CAMERA_CFG 518
#define SLAVE_CLK_CTL 519
#define SLAVE_CDSP_CFG 520
#define SLAVE_RBCPR_CX_CFG 521
#define SLAVE_RBCPR_MX_CFG 522
#define SLAVE_CRYPTO_0_CFG 523
#define SLAVE_CX_RDPM 524
#define SLAVE_DISPLAY_CFG 525
#define SLAVE_GFX3D_CFG 526
#define SLAVE_IMEM_CFG 527
#define SLAVE_IPA_CFG 528
#define SLAVE_IPC_ROUTER_CFG 529
#define SLAVE_LPASS 530
#define SLAVE_LPASS_CORE_CFG 531
#define SLAVE_LPASS_LPI_CFG 532
#define SLAVE_LPASS_MPU_CFG 533
#define SLAVE_LPASS_TOP_CFG 534
#define SLAVE_CNOC_MSS 535
#define SLAVE_MX_RDPM 536
#define SLAVE_PCIE_0_CFG 537
#define SLAVE_PDM 538
#define SLAVE_PIMEM_CFG 539
#define SLAVE_PMU_WRAPPER_CFG 540
#define SLAVE_PRNG 541
#define SLAVE_QDSS_CFG 542
#define SLAVE_QSPI_0 543
#define SLAVE_QUP_0 544
#define SLAVE_QUP_1 545
#define SLAVE_SDC1 546
#define SLAVE_SDCC_2 547
#define SLAVE_TCSR 548
#define SLAVE_TLMM 549
#define SLAVE_TME_CFG 550
#define SLAVE_UFS_MEM_CFG 551
#define SLAVE_USB3_0 552
#define SLAVE_VENUS_CFG 553
#define SLAVE_VSENSE_CTRL_CFG 554
#define SLAVE_WLAN 555
#define SLAVE_A1NOC_CFG 556
#define SLAVE_A1NOC_SNOC 557
#define SLAVE_A2NOC_CFG 558
#define SLAVE_A2NOC_SNOC 559
#define SLAVE_CNOC2_CNOC3 560
#define SLAVE_CNOC3_CNOC2 561
#define SLAVE_CNOC_A2NOC 562
#define SLAVE_GEM_NOC_CNOC 563
#define SLAVE_SNOC_GEM_NOC_GC 564
#define SLAVE_SNOC_GEM_NOC_SF 565
#define SLAVE_LLCC 566
#define SLAVE_MNOC_HF_MEM_NOC 567
#define SLAVE_MNOC_SF_MEM_NOC 568
#define SLAVE_CNOC_MNOC_CFG 569
#define SLAVE_CDSP_MEM_NOC 570
#define SLAVE_MEM_NOC_PCIE_SNOC 571
#define SLAVE_PCIE_ANOC_CFG 572
#define SLAVE_ANOC_PCIE_GEM_NOC 573
#define SLAVE_SNOC_CFG 574
#define SLAVE_LPASS_SNOC 575
#define SLAVE_QUP_CORE_0 576
#define SLAVE_QUP_CORE_1 577
#define SLAVE_BOOT_IMEM 578
#define SLAVE_IMEM 579
#define SLAVE_PIMEM 580
#define SLAVE_SERVICE_NSP_NOC 581
#define SLAVE_SERVICE_A1NOC 582
#define SLAVE_SERVICE_A2NOC 583
#define SLAVE_SERVICE_MNOC 584
#define SLAVE_SERVICES_LPASS_AML_NOC 585
#define SLAVE_SERVICE_LPASS_AG_NOC 586
#define SLAVE_SERVICE_PCIE_ANOC 587
#define SLAVE_SERVICE_SNOC 588
#define SLAVE_PCIE_0 589
#define SLAVE_QDSS_STM 590
#define SLAVE_TCU 591
#define MASTER_LLCC_DISP 1000
#define MASTER_MDP_DISP 1001
#define MASTER_MNOC_HF_MEM_NOC_DISP 1002
#define MASTER_ANOC_PCIE_GEM_NOC_DISP 1003
#define SLAVE_EBI1_DISP 1512
#define SLAVE_LLCC_DISP 1513
#define SLAVE_MNOC_HF_MEM_NOC_DISP 1514
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_PINEAPPLE_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_PINEAPPLE_H
#define MASTER_GPU_TCU 0
#define MASTER_SYS_TCU 1
#define MASTER_UBWC_P_TCU 2
#define MASTER_APPSS_PROC 3
#define MASTER_LLCC 4
#define MASTER_QDSS_BAM 5
#define MASTER_QSPI_0 6
#define MASTER_QUP_1 7
#define MASTER_QUP_2 8
#define MASTER_A1NOC_SNOC 9
#define MASTER_A2NOC_SNOC 10
#define MASTER_CAMNOC_HF 11
#define MASTER_CAMNOC_ICP 12
#define MASTER_CAMNOC_SF 13
#define MASTER_GEM_NOC_CNOC 14
#define MASTER_GEM_NOC_PCIE_SNOC 15
#define MASTER_GFX3D 16
#define MASTER_LPASS_GEM_NOC 17
#define MASTER_LPASS_LPINOC 18
#define MASTER_LPIAON_NOC 19
#define MASTER_MDP 20
#define MASTER_MSS_PROC 21
#define MASTER_MNOC_HF_MEM_NOC 22
#define MASTER_MNOC_SF_MEM_NOC 23
#define MASTER_CDSP_PROC 24
#define MASTER_COMPUTE_NOC 25
#define MASTER_ANOC_PCIE_GEM_NOC 26
#define MASTER_SNOC_SF_MEM_NOC 27
#define MASTER_UBWC_P 28
#define MASTER_CDSP_HCP 29
#define MASTER_VIDEO 30
#define MASTER_VIDEO_CV_PROC 31
#define MASTER_VIDEO_PROC 32
#define MASTER_VIDEO_V_PROC 33
#define MASTER_CNOC_CFG 34
#define MASTER_CNOC_MNOC_CFG 35
#define MASTER_PCIE_ANOC_CFG 36
#define MASTER_QUP_CORE_0 37
#define MASTER_QUP_CORE_1 38
#define MASTER_QUP_CORE_2 39
#define MASTER_CRYPTO 40
#define MASTER_IPA 41
#define MASTER_LPASS_PROC 42
#define MASTER_QUP_3 43
#define MASTER_SP 44
#define MASTER_GIC 45
#define MASTER_PCIE_0 46
#define MASTER_PCIE_1 47
#define MASTER_QDSS_ETR 48
#define MASTER_QDSS_ETR_1 49
#define MASTER_SDCC_2 50
#define MASTER_SDCC_4 51
#define MASTER_UFS_MEM 52
#define MASTER_USB3_0 53
#define SLAVE_EBI1 512
#define SLAVE_AHB2PHY_SOUTH 513
#define SLAVE_AHB2PHY_NORTH 514
#define SLAVE_AOSS 515
#define SLAVE_CAMERA_CFG 516
#define SLAVE_CLK_CTL 517
#define SLAVE_RBCPR_CX_CFG 518
#define SLAVE_CPR_HMX 519
#define SLAVE_RBCPR_MMCX_CFG 520
#define SLAVE_RBCPR_MXA_CFG 521
#define SLAVE_RBCPR_MXC_CFG 522
#define SLAVE_CPR_NSPCX 523
#define SLAVE_CRYPTO_0_CFG 524
#define SLAVE_CX_RDPM 525
#define SLAVE_DISPLAY_CFG 526
#define SLAVE_GFX3D_CFG 527
#define SLAVE_I2C 528
#define SLAVE_I3C_IBI0_CFG 529
#define SLAVE_I3C_IBI1_CFG 530
#define SLAVE_IMEM_CFG 531
#define SLAVE_IPA_CFG 532
#define SLAVE_IPC_ROUTER_CFG 533
#define SLAVE_CNOC_MSS 534
#define SLAVE_MX_2_RDPM 535
#define SLAVE_MX_RDPM 536
#define SLAVE_PCIE_0_CFG 537
#define SLAVE_PCIE_1_CFG 538
#define SLAVE_PCIE_RSCC 539
#define SLAVE_PDM 540
#define SLAVE_PRNG 541
#define SLAVE_QDSS_CFG 542
#define SLAVE_QSPI_0 543
#define SLAVE_QUP_3 544
#define SLAVE_QUP_1 545
#define SLAVE_QUP_2 546
#define SLAVE_SDCC_2 547
#define SLAVE_SDCC_4 548
#define SLAVE_SPSS_CFG 549
#define SLAVE_TCSR 550
#define SLAVE_TLMM 551
#define SLAVE_TME_CFG 552
#define SLAVE_UFS_MEM_CFG 553
#define SLAVE_USB3_0 554
#define SLAVE_VENUS_CFG 555
#define SLAVE_VSENSE_CTRL_CFG 556
#define SLAVE_A1NOC_SNOC 557
#define SLAVE_A2NOC_SNOC 558
#define SLAVE_GEM_NOC_CNOC 559
#define SLAVE_SNOC_GEM_NOC_SF 560
#define SLAVE_LLCC 561
#define SLAVE_LPASS_GEM_NOC 562
#define SLAVE_LPIAON_NOC_LPASS_AG_NOC 563
#define SLAVE_LPICX_NOC_LPIAON_NOC 564
#define SLAVE_MNOC_HF_MEM_NOC 565
#define SLAVE_MNOC_SF_MEM_NOC 566
#define SLAVE_CDSP_MEM_NOC 567
#define SLAVE_MEM_NOC_PCIE_SNOC 568
#define SLAVE_ANOC_PCIE_GEM_NOC 569
#define SLAVE_APPSS 570
#define SLAVE_CNOC_CFG 571
#define SLAVE_DDRSS_CFG 572
#define SLAVE_CNOC_MNOC_CFG 573
#define SLAVE_NSP_QTB_CFG 574
#define SLAVE_PCIE_ANOC_CFG 575
#define SLAVE_QUP_CORE_0 576
#define SLAVE_QUP_CORE_1 577
#define SLAVE_QUP_CORE_2 578
#define SLAVE_IMEM 579
#define SLAVE_SERVICE_CNOC_CFG 580
#define SLAVE_SERVICE_CNOC 581
#define SLAVE_SERVICE_MNOC 582
#define SLAVE_SERVICE_PCIE_ANOC 583
#define SLAVE_PCIE_0 584
#define SLAVE_QDSS_STM 585
#define SLAVE_TCU 586
#define MASTER_LLCC_DISP 1000
#define MASTER_MDP_DISP 1001
#define MASTER_MNOC_HF_MEM_NOC_DISP 1002
#define MASTER_ANOC_PCIE_GEM_NOC_DISP 1003
#define SLAVE_EBI1_DISP 1512
#define SLAVE_LLCC_DISP 1513
#define SLAVE_MNOC_HF_MEM_NOC_DISP 1514
#define MASTER_LLCC_CAM_IFE_0 2000
#define MASTER_CAMNOC_HF_CAM_IFE_0 2001
#define MASTER_CAMNOC_ICP_CAM_IFE_0 2002
#define MASTER_CAMNOC_SF_CAM_IFE_0 2003
#define MASTER_MNOC_HF_MEM_NOC_CAM_IFE_0 2004
#define MASTER_MNOC_SF_MEM_NOC_CAM_IFE_0 2005
#define MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_0 2006
#define SLAVE_EBI1_CAM_IFE_0 2512
#define SLAVE_LLCC_CAM_IFE_0 2513
#define SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_0 2514
#define SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0 2515
#define MASTER_LLCC_CAM_IFE_1 3000
#define MASTER_CAMNOC_HF_CAM_IFE_1 3001
#define MASTER_CAMNOC_ICP_CAM_IFE_1 3002
#define MASTER_CAMNOC_SF_CAM_IFE_1 3003
#define MASTER_MNOC_HF_MEM_NOC_CAM_IFE_1 3004
#define MASTER_MNOC_SF_MEM_NOC_CAM_IFE_1 3005
#define MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_1 3006
#define SLAVE_EBI1_CAM_IFE_1 3512
#define SLAVE_LLCC_CAM_IFE_1 3513
#define SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_1 3514
#define SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1 3515
#define MASTER_LLCC_CAM_IFE_2 4000
#define MASTER_CAMNOC_HF_CAM_IFE_2 4001
#define MASTER_CAMNOC_ICP_CAM_IFE_2 4002
#define MASTER_CAMNOC_SF_CAM_IFE_2 4003
#define MASTER_MNOC_HF_MEM_NOC_CAM_IFE_2 4004
#define MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2 4005
#define MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_2 4006
#define SLAVE_EBI1_CAM_IFE_2 4512
#define SLAVE_LLCC_CAM_IFE_2 4513
#define SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_2 4514
#define SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2 4515
#define MASTER_IPA_CORE_PCIE_CRM_HW_0 5000
#define MASTER_LLCC_PCIE_CRM_HW_0 5001
#define MASTER_ANOC_PCIE_GEM_NOC_PCIE_CRM_HW_0 5002
#define MASTER_PCIE_0_PCIE_CRM_HW_0 5003
#define MASTER_PCIE_1_PCIE_CRM_HW_0 5004
#define SLAVE_EBI1_PCIE_CRM_HW_0 5512
#define SLAVE_IPA_CORE_PCIE_CRM_HW_0 5513
#define SLAVE_LLCC_PCIE_CRM_HW_0 5514
#define SLAVE_ANOC_PCIE_GEM_NOC_PCIE_CRM_HW_0 5515
#define MASTER_IPA_CORE_PCIE_CRM_HW_1 6000
#define MASTER_LLCC_PCIE_CRM_HW_1 6001
#define MASTER_ANOC_PCIE_GEM_NOC_PCIE_CRM_HW_1 6002
#define MASTER_PCIE_0_PCIE_CRM_HW_1 6003
#define MASTER_PCIE_1_PCIE_CRM_HW_1 6004
#define SLAVE_EBI1_PCIE_CRM_HW_1 6512
#define SLAVE_IPA_CORE_PCIE_CRM_HW_1 6513
#define SLAVE_LLCC_PCIE_CRM_HW_1 6514
#define SLAVE_ANOC_PCIE_GEM_NOC_PCIE_CRM_HW_1 6515
#endif

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2022, 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_RAVELIN_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_RAVELIN_H
#define MASTER_GPU_TCU 0
#define MASTER_SYS_TCU 1
#define MASTER_APPSS_PROC 2
#define MASTER_LLCC 3
#define MASTER_CNOC_LPASS_AG_NOC 4
#define MASTER_GIC_AHB 5
#define MASTER_QDSS_BAM 6
#define MASTER_QUP_0 7
#define MASTER_QUP_1 8
#define MASTER_A1NOC_CFG 9
#define MASTER_A2NOC_CFG 10
#define MASTER_A1NOC_SNOC 11
#define MASTER_A2NOC_SNOC 12
#define MASTER_CAMNOC_HF 13
#define MASTER_CAMNOC_ICP 14
#define MASTER_CAMNOC_SF 15
#define MASTER_CNOC2_CNOC3 16
#define MASTER_CNOC3_CNOC2 17
#define MASTER_CNOC_A2NOC 18
#define MASTER_GEM_NOC_CNOC 19
#define MASTER_GEM_NOC_PCIE_SNOC 20
#define MASTER_GFX3D 21
#define MASTER_LPASS_ANOC 22
#define MASTER_MDP 23
#define MASTER_MSS_PROC 24
#define MASTER_CNOC_MNOC_CFG 25
#define MASTER_MNOC_HF_MEM_NOC 26
#define MASTER_MNOC_SF_MEM_NOC 27
#define MASTER_ANOC_PCIE_GEM_NOC 28
#define MASTER_PCIE_ANOC_CFG 29
#define MASTER_SNOC_CFG 30
#define MASTER_SNOC_GC_MEM_NOC 31
#define MASTER_SNOC_SF_MEM_NOC 32
#define MASTER_VIDEO_P0_MMNOC 33
#define MASTER_VIDEO_ANOC_CFG 34
#define MASTER_VIDEO_PROC_MMNOC 35
#define MASTER_QUP_CORE_0 36
#define MASTER_QUP_CORE_1 37
#define MASTER_CRYPTO 38
#define MASTER_IPA 39
#define MASTER_LPASS_PROC 40
#define MASTER_PIMEM 41
#define MASTER_VIDEO_P0 42
#define MASTER_VIDEO_PROC 43
#define MASTER_WLAN 44
#define MASTER_WLAN_Q6 45
#define MASTER_GIC 46
#define MASTER_PCIE_0 47
#define MASTER_QDSS_DAP 48
#define MASTER_QDSS_ETR 49
#define MASTER_QDSS_ETR_1 50
#define MASTER_SDCC_1 51
#define MASTER_SDCC_2 52
#define MASTER_UFS_MEM 53
#define MASTER_USB3_0 54
#define SLAVE_EBI1 512
#define SLAVE_AHB2PHY_SOUTH 513
#define SLAVE_AHB2PHY_NORTH 514
#define SLAVE_ANOC_THROTTLE_CFG 515
#define SLAVE_AOSS 516
#define SLAVE_APPSS 517
#define SLAVE_CAMERA_CFG 518
#define SLAVE_CLK_CTL 519
#define SLAVE_RBCPR_CX_CFG 520
#define SLAVE_RBCPR_MX_CFG 521
#define SLAVE_CRYPTO_0_CFG 522
#define SLAVE_CX_RDPM 523
#define SLAVE_DISPLAY_CFG 524
#define SLAVE_GFX3D_CFG 525
#define SLAVE_IMEM_CFG 526
#define SLAVE_IPA_CFG 527
#define SLAVE_IPC_ROUTER_CFG 528
#define SLAVE_LPASS 529
#define SLAVE_LPASS_CORE_CFG 530
#define SLAVE_LPASS_LPI_CFG 531
#define SLAVE_LPASS_MPU_CFG 532
#define SLAVE_LPASS_TOP_CFG 533
#define SLAVE_CNOC_MSS 534
#define SLAVE_MX_RDPM 535
#define SLAVE_PCIE_0_CFG 536
#define SLAVE_PDM 537
#define SLAVE_PIMEM_CFG 538
#define SLAVE_PMU_WRAPPER_CFG 539
#define SLAVE_PRNG 540
#define SLAVE_QDSS_CFG 541
#define SLAVE_QUP_0 542
#define SLAVE_QUP_1 543
#define SLAVE_SDC1 544
#define SLAVE_SDCC_2 545
#define SLAVE_TCSR 546
#define SLAVE_TLMM 547
#define SLAVE_TME_CFG 548
#define SLAVE_UFS_MEM_CFG 549
#define SLAVE_USB3_0 550
#define SLAVE_VENUS_CFG 551
#define SLAVE_VSENSE_CTRL_CFG 552
#define SLAVE_WLAN 553
#define SLAVE_A1NOC_CFG 554
#define SLAVE_A1NOC_SNOC 555
#define SLAVE_A2NOC_CFG 556
#define SLAVE_A2NOC_SNOC 557
#define SLAVE_CNOC2_CNOC3 558
#define SLAVE_CNOC3_CNOC2 559
#define SLAVE_CNOC_A2NOC 560
#define SLAVE_GEM_NOC_CNOC 561
#define SLAVE_SNOC_GEM_NOC_GC 562
#define SLAVE_SNOC_GEM_NOC_SF 563
#define SLAVE_LLCC 564
#define SLAVE_MNOC_HF_MEM_NOC 565
#define SLAVE_MNOC_SF_MEM_NOC 566
#define SLAVE_CNOC_MNOC_CFG 567
#define SLAVE_MEM_NOC_PCIE_SNOC 568
#define SLAVE_PCIE_ANOC_CFG 569
#define SLAVE_ANOC_PCIE_GEM_NOC 570
#define SLAVE_SNOC_CFG 571
#define SLAVE_LPASS_SNOC 572
#define SLAVE_VIDEO_0_ANOC_MMNOC 573
#define SLAVE_VIDEO_1_ANOC_MMNOC 574
#define SLAVE_VIDEO_ANOC_CFG 575
#define SLAVE_QUP_CORE_0 576
#define SLAVE_QUP_CORE_1 577
#define SLAVE_BOOT_IMEM 578
#define SLAVE_IMEM 579
#define SLAVE_PIMEM 580
#define SLAVE_SERVICE_A1NOC 581
#define SLAVE_SERVICE_A2NOC 582
#define SLAVE_SERVICE_MNOC 583
#define SLAVE_SERVICES_LPASS_AML_NOC 584
#define SLAVE_SERVICE_LPASS_AG_NOC 585
#define SLAVE_SERVICE_PCIE_ANOC 586
#define SLAVE_SERVICE_SNOC 587
#define SLAVE_SERVICE_SRVC_VIDEO_ANOC 588
#define SLAVE_PCIE_0 589
#define SLAVE_QDSS_STM 590
#define SLAVE_TCU 591
#define MASTER_LLCC_DISP 1000
#define MASTER_MDP_DISP 1001
#define MASTER_MNOC_HF_MEM_NOC_DISP 1002
#define MASTER_ANOC_PCIE_GEM_NOC_DISP 1003
#define SLAVE_EBI1_DISP 1512
#define SLAVE_LLCC_DISP 1513
#define SLAVE_MNOC_HF_MEM_NOC_DISP 1514
#endif

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include/dt-bindings/interconnect/qcom,sdx75.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */
/*
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDX75_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_SDX75_H
#define MASTER_SYS_TCU 0
#define MASTER_APPSS_PROC 1
#define MASTER_LLCC 2
#define MASTER_AUDIO 3
#define MASTER_GIC_AHB 4
#define MASTER_PCIE_RSCC 5
#define MASTER_QDSS_BAM 6
#define MASTER_QPIC 7
#define MASTER_QUP_0 8
#define MASTER_ANOC_SNOC 9
#define MASTER_CNOC_DC_NOC 10
#define MASTER_GEM_NOC_CFG 11
#define MASTER_GEM_NOC_CNOC 12
#define MASTER_GEM_NOC_PCIE_SNOC 13
#define MASTER_MSS_PROC 14
#define MASTER_ANOC_PCIE_GEM_NOC 15
#define MASTER_SNOC_SF_MEM_NOC 16
#define MASTER_SNOC_CFG 17
#define MASTER_PCIE_ANOC_CFG 18
#define MASTER_QPIC_CORE 19
#define MASTER_QUP_CORE_0 20
#define MASTER_CRYPTO 21
#define MASTER_IPA 22
#define MASTER_MVMSS 23
#define MASTER_EMAC_0 24
#define MASTER_EMAC_1 25
#define MASTER_GIC 26
#define MASTER_IPA_PCIE 27
#define MASTER_PCIE_0 28
#define MASTER_PCIE_1 29
#define MASTER_PCIE_2 30
#define MASTER_QDSS_ETR 31
#define MASTER_QDSS_ETR_1 32
#define MASTER_SDCC_1 33
#define MASTER_SDCC_4 34
#define MASTER_USB3_0 35
#define SLAVE_EBI1 512
#define SLAVE_ETH0_CFG 513
#define SLAVE_ETH1_CFG 514
#define SLAVE_AUDIO 515
#define SLAVE_CLK_CTL 516
#define SLAVE_CRYPTO_0_CFG 517
#define SLAVE_IMEM_CFG 518
#define SLAVE_IPA_CFG 519
#define SLAVE_IPC_ROUTER_CFG 520
#define SLAVE_LAGG_CFG 521
#define SLAVE_MCCC_MASTER 522
#define SLAVE_CNOC_MSS 523
#define ICBDI_SLAVE_MVMSS_CFG 524
#define SLAVE_PCIE_0_CFG 525
#define SLAVE_PCIE_1_CFG 526
#define SLAVE_PCIE_2_CFG 527
#define SLAVE_PCIE_RSC_CFG 528
#define SLAVE_PDM 529
#define SLAVE_PRNG 530
#define SLAVE_QDSS_CFG 531
#define SLAVE_QPIC 532
#define SLAVE_QUP_0 533
#define SLAVE_SDCC_1 534
#define SLAVE_SDCC_4 535
#define SLAVE_SPMI_VGI_COEX 536
#define SLAVE_TCSR 537
#define SLAVE_TLMM 538
#define SLAVE_USB3 539
#define SLAVE_USB3_PHY_CFG 540
#define SLAVE_A1NOC_CFG 541
#define SLAVE_DDRSS_CFG 542
#define SLAVE_GEM_NOC_CFG 543
#define SLAVE_GEM_NOC_CNOC 544
#define SLAVE_SNOC_GEM_NOC_SF 545
#define SLAVE_LLCC 546
#define SLAVE_MEM_NOC_PCIE_SNOC 547
#define SLAVE_ANOC_PCIE_GEM_NOC 548
#define SLAVE_SNOC_CFG 549
#define SLAVE_PCIE_ANOC_CFG 550
#define SLAVE_QPIC_CORE 551
#define SLAVE_SNOOP_BWMON 552
#define SLAVE_QUP_CORE_0 553
#define SLAVE_IMEM 554
#define SLAVE_SERVICE_GEM_NOC 555
#define SLAVE_SERVICE_PCIE_ANOC 556
#define SLAVE_SERVICE_SNOC 557
#define SLAVE_PCIE_0 558
#define SLAVE_PCIE_1 559
#define SLAVE_PCIE_2 560
#define SLAVE_QDSS_STM 561
#define SLAVE_TCU 562
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SUN_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_SUN_H
#define MASTER_GPU_TCU 0
#define MASTER_SYS_TCU 1
#define MASTER_APPSS_PROC 2
#define MASTER_LLCC 3
#define MASTER_QDSS_BAM 4
#define MASTER_QSPI_0 5
#define MASTER_QUP_1 6
#define MASTER_QUP_2 7
#define MASTER_A1NOC_SNOC 8
#define MASTER_A2NOC_SNOC 9
#define MASTER_CAMNOC_HF 10
#define MASTER_CAMNOC_NRT_ICP_SF 11
#define MASTER_CAMNOC_RT_CDM_SF 12
#define MASTER_CAMNOC_SF 13
#define MASTER_GEM_NOC_CNOC 14
#define MASTER_GEM_NOC_PCIE_SNOC 15
#define MASTER_GFX3D 16
#define MASTER_LPASS_GEM_NOC 17
#define MASTER_LPASS_LPINOC 18
#define MASTER_LPIAON_NOC 19
#define MASTER_LPASS_PROC 20
#define MASTER_MDP 21
#define MASTER_MSS_PROC 22
#define MASTER_MNOC_HF_MEM_NOC 23
#define MASTER_MNOC_SF_MEM_NOC 24
#define MASTER_CDSP_PROC 25
#define MASTER_COMPUTE_NOC 26
#define MASTER_ANOC_PCIE_GEM_NOC 27
#define MASTER_SNOC_SF_MEM_NOC 28
#define MASTER_UBWC_P 29
#define MASTER_CDSP_HCP 30
#define MASTER_VIDEO_CV_PROC 31
#define MASTER_VIDEO_EVA 32
#define MASTER_VIDEO_MVP 33
#define MASTER_VIDEO_V_PROC 34
#define MASTER_CNOC_CFG 35
#define MASTER_CNOC_MNOC_CFG 36
#define MASTER_PCIE_ANOC_CFG 37
#define MASTER_QUP_CORE_0 38
#define MASTER_QUP_CORE_1 39
#define MASTER_QUP_CORE_2 40
#define MASTER_CRYPTO 41
#define MASTER_IPA 42
#define MASTER_QUP_3 43
#define MASTER_SOCCP_AGGR_NOC 44
#define MASTER_SP 45
#define MASTER_GIC 46
#define MASTER_PCIE_0 47
#define MASTER_QDSS_ETR 48
#define MASTER_QDSS_ETR_1 49
#define MASTER_SDCC_2 50
#define MASTER_SDCC_4 51
#define MASTER_UFS_MEM 52
#define MASTER_USB3_0 53
#define SLAVE_UBWC_P 512
#define SLAVE_EBI1 513
#define SLAVE_AHB2PHY_SOUTH 514
#define SLAVE_AHB2PHY_NORTH 515
#define SLAVE_AOSS 516
#define SLAVE_CAMERA_CFG 517
#define SLAVE_CLK_CTL 518
#define SLAVE_CRYPTO_0_CFG 519
#define SLAVE_DISPLAY_CFG 520
#define SLAVE_EVA_CFG 521
#define SLAVE_GFX3D_CFG 522
#define SLAVE_I2C 523
#define SLAVE_I3C_IBI0_CFG 524
#define SLAVE_I3C_IBI1_CFG 525
#define SLAVE_IMEM_CFG 526
#define SLAVE_IPA_CFG 527
#define SLAVE_IPC_ROUTER_CFG 528
#define SLAVE_CNOC_MSS 529
#define SLAVE_PCIE_CFG 530
#define SLAVE_PRNG 531
#define SLAVE_QDSS_CFG 532
#define SLAVE_QSPI_0 533
#define SLAVE_QUP_3 534
#define SLAVE_QUP_1 535
#define SLAVE_QUP_2 536
#define SLAVE_SDCC_2 537
#define SLAVE_SDCC_4 538
#define SLAVE_SOCCP 539
#define SLAVE_SPSS_CFG 540
#define SLAVE_TCSR 541
#define SLAVE_TLMM 542
#define SLAVE_TME_CFG 543
#define SLAVE_UFS_MEM_CFG 544
#define SLAVE_USB3_0 545
#define SLAVE_VENUS_CFG 546
#define SLAVE_VSENSE_CTRL_CFG 547
#define SLAVE_A1NOC_SNOC 548
#define SLAVE_A2NOC_SNOC 549
#define SLAVE_APPSS 550
#define SLAVE_GEM_NOC_CNOC 551
#define SLAVE_SNOC_GEM_NOC_SF 552
#define SLAVE_LLCC 553
#define SLAVE_LPASS_GEM_NOC 554
#define SLAVE_LPIAON_NOC_LPASS_AG_NOC 555
#define SLAVE_LPICX_NOC_LPIAON_NOC 556
#define SLAVE_MNOC_HF_MEM_NOC 557
#define SLAVE_MNOC_SF_MEM_NOC 558
#define SLAVE_CDSP_MEM_NOC 559
#define SLAVE_MEM_NOC_PCIE_SNOC 560
#define SLAVE_ANOC_PCIE_GEM_NOC 561
#define SLAVE_CNOC_CFG 562
#define SLAVE_DDRSS_CFG 563
#define SLAVE_CNOC_MNOC_CFG 564
#define SLAVE_PCIE_ANOC_CFG 565
#define SLAVE_QUP_CORE_0 566
#define SLAVE_QUP_CORE_1 567
#define SLAVE_QUP_CORE_2 568
#define SLAVE_BOOT_IMEM 569
#define SLAVE_IMEM 570
#define SLAVE_BOOT_IMEM_2 571
#define SLAVE_SERVICE_CNOC 572
#define SLAVE_SERVICE_MNOC 573
#define SLAVE_SERVICE_PCIE_ANOC 574
#define SLAVE_PCIE_0 575
#define SLAVE_QDSS_STM 576
#define SLAVE_TCU 577
#define MASTER_LLCC_DISP 1000
#define MASTER_MDP_DISP 1001
#define MASTER_MNOC_HF_MEM_NOC_DISP 1002
#define MASTER_ANOC_PCIE_GEM_NOC_DISP 1003
#define SLAVE_EBI1_DISP 1512
#define SLAVE_LLCC_DISP 1513
#define SLAVE_MNOC_HF_MEM_NOC_DISP 1514
#define MASTER_LLCC_CAM_IFE_0 2000
#define MASTER_CAMNOC_HF_CAM_IFE_0 2001
#define MASTER_CAMNOC_NRT_ICP_SF_CAM_IFE_0 2002
#define MASTER_CAMNOC_RT_CDM_SF_CAM_IFE_0 2003
#define MASTER_CAMNOC_SF_CAM_IFE_0 2004
#define MASTER_MNOC_HF_MEM_NOC_CAM_IFE_0 2005
#define MASTER_MNOC_SF_MEM_NOC_CAM_IFE_0 2006
#define MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_0 2007
#define SLAVE_EBI1_CAM_IFE_0 2512
#define SLAVE_LLCC_CAM_IFE_0 2513
#define SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_0 2514
#define SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0 2515
#define MASTER_LLCC_CAM_IFE_1 3000
#define MASTER_CAMNOC_HF_CAM_IFE_1 3001
#define MASTER_CAMNOC_NRT_ICP_SF_CAM_IFE_1 3002
#define MASTER_CAMNOC_RT_CDM_SF_CAM_IFE_1 3003
#define MASTER_CAMNOC_SF_CAM_IFE_1 3004
#define MASTER_MNOC_HF_MEM_NOC_CAM_IFE_1 3005
#define MASTER_MNOC_SF_MEM_NOC_CAM_IFE_1 3006
#define MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_1 3007
#define SLAVE_EBI1_CAM_IFE_1 3512
#define SLAVE_LLCC_CAM_IFE_1 3513
#define SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_1 3514
#define SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1 3515
#define MASTER_LLCC_CAM_IFE_2 4000
#define MASTER_CAMNOC_HF_CAM_IFE_2 4001
#define MASTER_CAMNOC_NRT_ICP_SF_CAM_IFE_2 4002
#define MASTER_CAMNOC_RT_CDM_SF_CAM_IFE_2 4003
#define MASTER_CAMNOC_SF_CAM_IFE_2 4004
#define MASTER_MNOC_HF_MEM_NOC_CAM_IFE_2 4005
#define MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2 4006
#define MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_2 4007
#define SLAVE_EBI1_CAM_IFE_2 4512
#define SLAVE_LLCC_CAM_IFE_2 4513
#define SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_2 4514
#define SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2 4515
#define MASTER_IPA_CORE_PCIE_CRM_HW_0 5000
#define MASTER_LLCC_PCIE_CRM_HW_0 5001
#define MASTER_ANOC_PCIE_GEM_NOC_PCIE_CRM_HW_0 5002
#define MASTER_PCIE_0_PCIE_CRM_HW_0 5003
#define SLAVE_EBI1_PCIE_CRM_HW_0 5512
#define SLAVE_IPA_CORE_PCIE_CRM_HW_0 5513
#define SLAVE_LLCC_PCIE_CRM_HW_0 5514
#define SLAVE_ANOC_PCIE_GEM_NOC_PCIE_CRM_HW_0 5515
#define MASTER_LLCC_DISP_CRM_HW_0 6000
#define MASTER_MDP_DISP_CRM_HW_0 6001
#define MASTER_MNOC_HF_MEM_NOC_DISP_CRM_HW_0 6002
#define MASTER_ANOC_PCIE_GEM_NOC_DISP_CRM_HW_0 6003
#define SLAVE_EBI1_DISP_CRM_HW_0 6512
#define SLAVE_LLCC_DISP_CRM_HW_0 6513
#define SLAVE_MNOC_HF_MEM_NOC_DISP_CRM_HW_0 6514
#define MASTER_LLCC_DISP_CRM_HW_1 7000
#define MASTER_MDP_DISP_CRM_HW_1 7001
#define MASTER_MNOC_HF_MEM_NOC_DISP_CRM_HW_1 7002
#define MASTER_ANOC_PCIE_GEM_NOC_DISP_CRM_HW_1 7003
#define SLAVE_EBI1_DISP_CRM_HW_1 7512
#define SLAVE_LLCC_DISP_CRM_HW_1 7513
#define SLAVE_MNOC_HF_MEM_NOC_DISP_CRM_HW_1 7514
#define MASTER_LLCC_DISP_CRM_HW_2 8000
#define MASTER_MDP_DISP_CRM_HW_2 8001
#define MASTER_MNOC_HF_MEM_NOC_DISP_CRM_HW_2 8002
#define MASTER_ANOC_PCIE_GEM_NOC_DISP_CRM_HW_2 8003
#define SLAVE_EBI1_DISP_CRM_HW_2 8512
#define SLAVE_LLCC_DISP_CRM_HW_2 8513
#define SLAVE_MNOC_HF_MEM_NOC_DISP_CRM_HW_2 8514
#define MASTER_LLCC_DISP_CRM_HW_3 9000
#define MASTER_MDP_DISP_CRM_HW_3 9001
#define MASTER_MNOC_HF_MEM_NOC_DISP_CRM_HW_3 9002
#define MASTER_ANOC_PCIE_GEM_NOC_DISP_CRM_HW_3 9003
#define SLAVE_EBI1_DISP_CRM_HW_3 9512
#define SLAVE_LLCC_DISP_CRM_HW_3 9513
#define SLAVE_MNOC_HF_MEM_NOC_DISP_CRM_HW_3 9514
#define MASTER_LLCC_DISP_CRM_HW_4 10000
#define MASTER_MDP_DISP_CRM_HW_4 10001
#define MASTER_MNOC_HF_MEM_NOC_DISP_CRM_HW_4 10002
#define MASTER_ANOC_PCIE_GEM_NOC_DISP_CRM_HW_4 10003
#define SLAVE_EBI1_DISP_CRM_HW_4 10512
#define SLAVE_LLCC_DISP_CRM_HW_4 10513
#define SLAVE_MNOC_HF_MEM_NOC_DISP_CRM_HW_4 10514
#define MASTER_LLCC_DISP_CRM_HW_5 11000
#define MASTER_MDP_DISP_CRM_HW_5 11001
#define MASTER_MNOC_HF_MEM_NOC_DISP_CRM_HW_5 11002
#define MASTER_ANOC_PCIE_GEM_NOC_DISP_CRM_HW_5 11003
#define SLAVE_EBI1_DISP_CRM_HW_5 11512
#define SLAVE_LLCC_DISP_CRM_HW_5 11513
#define SLAVE_MNOC_HF_MEM_NOC_DISP_CRM_HW_5 11514
#define MASTER_LLCC_DISP_CRM_SW_0 12000
#define MASTER_MDP_DISP_CRM_SW_0 12001
#define MASTER_MNOC_HF_MEM_NOC_DISP_CRM_SW_0 12002
#define MASTER_ANOC_PCIE_GEM_NOC_DISP_CRM_SW_0 12003
#define SLAVE_EBI1_DISP_CRM_SW_0 12512
#define SLAVE_LLCC_DISP_CRM_SW_0 12513
#define SLAVE_MNOC_HF_MEM_NOC_DISP_CRM_SW_0 12514
#define MASTER_UBWC MASTER_UBWC_P
#define MASTER_PCIE_3 MASTER_PCIE_0
#define SLAVE_UBWC SLAVE_UBWC_P
#define MASTER_PCIE_3_PCIE_CRM_HW_0 MASTER_PCIE_0_PCIE_CRM_HW_0
#endif

164
include/dt-bindings/interconnect/qcom,tuna.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_TUNA_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_TUNA_H
#define MASTER_GPU_TCU 0
#define MASTER_SYS_TCU 1
#define MASTER_APPSS_PROC 2
#define MASTER_LLCC 3
#define MASTER_QSPI_0 4
#define MASTER_QUP_1 5
#define MASTER_QUP_2 6
#define MASTER_A1NOC_SNOC 7
#define MASTER_A2NOC_SNOC 8
#define MASTER_CAMNOC_HF 9
#define MASTER_CAMNOC_NRT_ICP_SF 10
#define MASTER_CAMNOC_RT_CDM_SF 11
#define MASTER_CAMNOC_SF 12
#define MASTER_GEM_NOC_CNOC 13
#define MASTER_GEM_NOC_PCIE_SNOC 14
#define MASTER_GFX3D 15
#define MASTER_LPASS_GEM_NOC 16
#define MASTER_LPASS_LPINOC 17
#define MASTER_LPIAON_NOC 18
#define MASTER_MDP 19
#define MASTER_MSS_PROC 20
#define MASTER_MNOC_HF_MEM_NOC 21
#define MASTER_MNOC_SF_MEM_NOC 22
#define MASTER_COMPUTE_NOC 23
#define MASTER_ANOC_PCIE_GEM_NOC 24
#define MASTER_SNOC_SF_MEM_NOC 25
#define MASTER_VIDEO_CV_PROC 26
#define MASTER_VIDEO_EVA 27
#define MASTER_VIDEO_MVP 28
#define MASTER_VIDEO_V_PROC 29
#define MASTER_CNOC_CFG 30
#define MASTER_CNOC_MNOC_HF_CFG 31
#define MASTER_PCIE_ANOC_CFG 32
#define MASTER_CNOC_MNOC_SF_CFG 33
#define MASTER_QUP_CORE_1 34
#define MASTER_QUP_CORE_2 35
#define MASTER_CRYPTO 36
#define MASTER_IPA 37
#define MASTER_LPASS_PROC 38
#define MASTER_CDSP_PROC 39
#define MASTER_SOCCP_AGGR_NOC 40
#define MASTER_WLAN_Q6 41
#define MASTER_GIC 42
#define MASTER_PCIE_0 43
#define MASTER_QDSS_ETR 44
#define MASTER_QDSS_ETR_1 45
#define MASTER_SDCC_2 46
#define MASTER_UFS_MEM 47
#define MASTER_USB3_0 48
#define SLAVE_EBI1 512
#define SLAVE_AHB2PHY_SOUTH 513
#define SLAVE_AHB2PHY_NORTH 514
#define SLAVE_AOSS 515
#define SLAVE_CAMERA_CFG 516
#define SLAVE_CLK_CTL 517
#define SLAVE_CRYPTO_0_CFG 518
#define SLAVE_DISPLAY_CFG 519
#define SLAVE_EVA_CFG 520
#define SLAVE_GFX3D_CFG 521
#define SLAVE_I3C_IBI0_CFG 522
#define SLAVE_I3C_IBI1_CFG 523
#define SLAVE_IMEM_CFG 524
#define SLAVE_IPA_CFG 525
#define SLAVE_IPC_ROUTER_CFG 526
#define SLAVE_CNOC_MSS 527
#define SLAVE_PCIE_CFG 528
#define SLAVE_PRNG 529
#define SLAVE_QDSS_CFG 530
#define SLAVE_QSPI_0 531
#define SLAVE_QUP_1 532
#define SLAVE_QUP_2 533
#define SLAVE_SDCC_2 534
#define SLAVE_SOCCP 535
#define SLAVE_TCSR 536
#define SLAVE_TLMM 537
#define SLAVE_TME_CFG 538
#define SLAVE_UFS_MEM_CFG 539
#define SLAVE_USB3_0 540
#define SLAVE_VENUS_CFG 541
#define SLAVE_VSENSE_CTRL_CFG 542
#define SLAVE_A1NOC_SNOC 543
#define SLAVE_A2NOC_SNOC 544
#define SLAVE_GEM_NOC_CNOC 545
#define SLAVE_SNOC_GEM_NOC_SF 546
#define SLAVE_LLCC 547
#define SLAVE_LPASS_GEM_NOC 548
#define SLAVE_LPIAON_NOC_LPASS_AG_NOC 549
#define SLAVE_LPICX_NOC_LPIAON_NOC 550
#define SLAVE_MNOC_HF_MEM_NOC 551
#define SLAVE_MNOC_SF_MEM_NOC 552
#define SLAVE_CDSP_MEM_NOC 553
#define SLAVE_MEM_NOC_PCIE_SNOC 554
#define SLAVE_ANOC_PCIE_GEM_NOC 555
#define SLAVE_APPSS 556
#define SLAVE_CNOC_CFG 557
#define SLAVE_DDRSS_CFG 558
#define SLAVE_CNOC_MNOC_HF_CFG 559
#define SLAVE_CNOC_MNOC_SF_CFG 560
#define SLAVE_PCIE_ANOC_CFG 561
#define SLAVE_QUP_CORE_1 562
#define SLAVE_QUP_CORE_2 563
#define SLAVE_BOOT_IMEM 564
#define SLAVE_IMEM 565
#define SLAVE_BOOT_IMEM_2 566
#define SLAVE_SERVICE_CNOC 567
#define SLAVE_SERVICE_MNOC_HF 568
#define SLAVE_SERVICE_MNOC_SF 569
#define SLAVE_SERVICE_PCIE_ANOC 570
#define SLAVE_PCIE_0 571
#define SLAVE_QDSS_STM 572
#define SLAVE_TCU 573
#define MASTER_LLCC_DISP 1000
#define MASTER_MDP_DISP 1001
#define MASTER_MNOC_HF_MEM_NOC_DISP 1002
#define MASTER_ANOC_PCIE_GEM_NOC_DISP 1003
#define SLAVE_EBI1_DISP 1512
#define SLAVE_LLCC_DISP 1513
#define SLAVE_MNOC_HF_MEM_NOC_DISP 1514
#define MASTER_LLCC_CAM_IFE_0 2000
#define MASTER_CAMNOC_HF_CAM_IFE_0 2001
#define MASTER_CAMNOC_NRT_ICP_SF_CAM_IFE_0 2002
#define MASTER_CAMNOC_RT_CDM_SF_CAM_IFE_0 2003
#define MASTER_CAMNOC_SF_CAM_IFE_0 2004
#define MASTER_MNOC_HF_MEM_NOC_CAM_IFE_0 2005
#define MASTER_MNOC_SF_MEM_NOC_CAM_IFE_0 2006
#define MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_0 2007
#define SLAVE_EBI1_CAM_IFE_0 2512
#define SLAVE_LLCC_CAM_IFE_0 2513
#define SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_0 2514
#define SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0 2515
#define MASTER_LLCC_CAM_IFE_1 3000
#define MASTER_CAMNOC_HF_CAM_IFE_1 3001
#define MASTER_CAMNOC_NRT_ICP_SF_CAM_IFE_1 3002
#define MASTER_CAMNOC_RT_CDM_SF_CAM_IFE_1 3003
#define MASTER_CAMNOC_SF_CAM_IFE_1 3004
#define MASTER_MNOC_HF_MEM_NOC_CAM_IFE_1 3005
#define MASTER_MNOC_SF_MEM_NOC_CAM_IFE_1 3006
#define MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_1 3007
#define SLAVE_EBI1_CAM_IFE_1 3512
#define SLAVE_LLCC_CAM_IFE_1 3513
#define SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_1 3514
#define SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1 3515
#define MASTER_LLCC_CAM_IFE_2 4000
#define MASTER_CAMNOC_HF_CAM_IFE_2 4001
#define MASTER_CAMNOC_NRT_ICP_SF_CAM_IFE_2 4002
#define MASTER_CAMNOC_RT_CDM_SF_CAM_IFE_2 4003
#define MASTER_CAMNOC_SF_CAM_IFE_2 4004
#define MASTER_MNOC_HF_MEM_NOC_CAM_IFE_2 4005
#define MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2 4006
#define MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_2 4007
#define SLAVE_EBI1_CAM_IFE_2 4512
#define SLAVE_LLCC_CAM_IFE_2 4513
#define SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_2 4514
#define SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2 4515
#endif

5
include/dt-bindings/mailbox/qcom-ipcc.h
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#define IPCC_CLIENT_NSP1 18
#define IPCC_CLIENT_TME 23
#define IPCC_CLIENT_WPSS 24
#define IPCC_CLIENT_SOCCP 46
#define IPCC_CLIENT_CAM1 47
#define IPCC_CLIENT_BROADCAST 0xF000
#endif

880
include/dt-bindings/phy/qcom,usb3-3nm-qmp-combo.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_PHY_QCOM_3NM_QMP_COMBO_USB_H
#define _DT_BINDINGS_PHY_QCOM_3NM_QMP_COMBO_USB_H
/* USB3-DP Combo PHY register offsets */
/* Module: USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM */
#define USB3_DP_COM_PHY_MODE_CTRL 0x0000
#define USB3_DP_COM_SW_RESET 0x0004
#define USB3_DP_COM_POWER_DOWN_CTRL 0x0008
#define USB3_DP_COM_SWI_CTRL 0x000C
#define USB3_DP_COM_TYPEC_CTRL 0x0010
#define USB3_DP_COM_TYPEC_PWRDN_CTRL 0x0014
#define USB3_DP_COM_DP_BIST_CFG_0 0x0018
#define USB3_DP_COM_RESET_OVRD_CTRL 0x001C
#define USB3_DP_COM_DBG_CLK_MUX_CTRL 0x0020
#define USB3_DP_COM_TYPEC_STATUS 0x0024
#define USB3_DP_COM_PLACEHOLDER_STATUS 0x0028
#define USB3_DP_COM_REVISION_ID0 0x002C
#define USB3_DP_COM_REVISION_ID1 0x0030
#define USB3_DP_COM_REVISION_ID2 0x0034
#define USB3_DP_COM_REVISION_ID3 0x0038
/* Module: USB3_DP_PHY_USB3_DP_DBGINT_USB3_DP_DBGINT_USB3_PCS_DEBUG_INT */
#define USB3_DP_DBGINT_INTGEN_STATUS1 0x0200
#define USB3_DP_DBGINT_INTGEN_STATUS2 0x0204
#define USB3_DP_DBGINT_CONFIG1 0x0208
#define USB3_DP_DBGINT_SIGNALBLK1_CONFIG1 0x020C
#define USB3_DP_DBGINT_SIGNALBLK1_CONFIG2 0x0210
#define USB3_DP_DBGINT_SIGNALBLK1_CONFIG3 0x0214
#define USB3_DP_DBGINT_SIGNALBLK1_CONFIG4 0x0218
#define USB3_DP_DBGINT_SIGNALBLK1_CONFIG5 0x021C
#define USB3_DP_DBGINT_SIGNALBLK2_CONFIG1 0x0220
#define USB3_DP_DBGINT_SIGNALBLK2_CONFIG2 0x0224
#define USB3_DP_DBGINT_SIGNALBLK2_CONFIG3 0x0228
#define USB3_DP_DBGINT_SIGNALBLK2_CONFIG4 0x022C
#define USB3_DP_DBGINT_SIGNALBLK2_CONFIG5 0x0230
#define USB3_DP_DBGINT_STRINGBLK1_CONFIG1 0x0234
#define USB3_DP_DBGINT_STRINGBLK1_CONFIG2 0x0238
#define USB3_DP_DBGINT_STRINGBLK1_CONFIG3 0x023C
#define USB3_DP_DBGINT_STRINGBLK1_CONFIG4 0x0240
#define USB3_DP_DBGINT_STRINGBLK1_CONFIG5 0x0244
#define USB3_DP_DBGINT_STRINGBLK2_CONFIG1 0x0248
#define USB3_DP_DBGINT_STRINGBLK2_CONFIG2 0x024C
#define USB3_DP_DBGINT_STRINGBLK2_CONFIG3 0x0250
#define USB3_DP_DBGINT_STRINGBLK2_CONFIG4 0x0254
#define USB3_DP_DBGINT_STRINGBLK2_CONFIG5 0x0258
/* Module: USB3_DP_PHY_USB3_QSERDES_COM_USB3_QSERDES_COM_USB3_DP_QMP_PLL */
#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0x1000
#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x1004
#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE1 0x1008
#define USB3_DP_QSERDES_COM_CLK_EP_DIV_MODE1 0x100C
#define USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x1010
#define USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x1014
#define USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x1018
#define USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x101C
#define USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x1020
#define USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x1024
#define USB3_DP_QSERDES_COM_DEC_START_MODE1 0x1028
#define USB3_DP_QSERDES_COM_DEC_START_MSB_MODE1 0x102C
#define USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0x1030
#define USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0x1034
#define USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x1038
#define USB3_DP_QSERDES_COM_HSCLK_SEL_1 0x103C
#define USB3_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x1040
#define USB3_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x1044
#define USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x1048
#define USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x104C
#define USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1050
#define USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1054
#define USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1058
#define USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x105C
#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0x1060
#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x1064
#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE0 0x1068
#define USB3_DP_QSERDES_COM_CLK_EP_DIV_MODE0 0x106C
#define USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x1070
#define USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x1074
#define USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x1078
#define USB3_DP_QSERDES_COM_CORECLK_DIV_MODE0 0x107C
#define USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x1080
#define USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x1084
#define USB3_DP_QSERDES_COM_DEC_START_MODE0 0x1088
#define USB3_DP_QSERDES_COM_DEC_START_MSB_MODE0 0x108C
#define USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0x1090
#define USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0x1094
#define USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x1098
#define USB3_DP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_1 0x109C
#define USB3_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x10A0
#define USB3_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10A4
#define USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x10A8
#define USB3_DP_QSERDES_COM_VCO_TUNE2_MODE0 0x10AC
#define USB3_DP_QSERDES_COM_ATB_SEL1 0x10B0
#define USB3_DP_QSERDES_COM_ATB_SEL2 0x10B4
#define USB3_DP_QSERDES_COM_FREQ_UPDATE 0x10B8
#define USB3_DP_QSERDES_COM_BG_TIMER 0x10BC
#define USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x10C0
#define USB3_DP_QSERDES_COM_SSC_ADJ_PER1 0x10C4
#define USB3_DP_QSERDES_COM_SSC_ADJ_PER2 0x10C8
#define USB3_DP_QSERDES_COM_SSC_PER1 0x10CC
#define USB3_DP_QSERDES_COM_SSC_PER2 0x10D0
#define USB3_DP_QSERDES_COM_POST_DIV 0x10D4
#define USB3_DP_QSERDES_COM_POST_DIV_MUX 0x10D8
#define USB3_DP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x10DC
#define USB3_DP_QSERDES_COM_CLK_ENABLE1 0x10E0
#define USB3_DP_QSERDES_COM_SYS_CLK_CTRL 0x10E4
#define USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x10E8
#define USB3_DP_QSERDES_COM_PLL_EN 0x10EC
#define USB3_DP_QSERDES_COM_DEBUG_BUS_OVRD 0x10F0
#define USB3_DP_QSERDES_COM_PLL_IVCO 0x10F4
#define USB3_DP_QSERDES_COM_PLL_IVCO_MODE1 0x10F8
#define USB3_DP_QSERDES_COM_CMN_IETRIM 0x10FC
#define USB3_DP_QSERDES_COM_CMN_IPTRIM 0x1100
#define USB3_DP_QSERDES_COM_EP_CLOCK_DETECT_CTRL 0x1104
#define USB3_DP_QSERDES_COM_PLL_CNTRL 0x1108
#define USB3_DP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x110C
#define USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1110
#define USB3_DP_QSERDES_COM_CML_SYSCLK_SEL 0x1114
#define USB3_DP_QSERDES_COM_RESETSM_CNTRL 0x1118
#define USB3_DP_QSERDES_COM_RESETSM_CNTRL2 0x111C
#define USB3_DP_QSERDES_COM_LOCK_CMP_EN 0x1120
#define USB3_DP_QSERDES_COM_LOCK_CMP_CFG 0x1124
#define USB3_DP_QSERDES_COM_INTEGLOOP_INITVAL 0x1128
#define USB3_DP_QSERDES_COM_INTEGLOOP_EN 0x112C
#define USB3_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0 0x1130
#define USB3_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1 0x1134
#define USB3_DP_QSERDES_COM_VCOCAL_DEADMAN_CTRL 0x1138
#define USB3_DP_QSERDES_COM_VCO_TUNE_CTRL 0x113C
#define USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x1140
#define USB3_DP_QSERDES_COM_VCO_TUNE_INITVAL1 0x1144
#define USB3_DP_QSERDES_COM_VCO_TUNE_INITVAL2 0x1148
#define USB3_DP_QSERDES_COM_VCO_TUNE_MINVAL1 0x114C
#define USB3_DP_QSERDES_COM_VCO_TUNE_MINVAL2 0x1150
#define USB3_DP_QSERDES_COM_VCO_TUNE_MAXVAL1 0x1154
#define USB3_DP_QSERDES_COM_VCO_TUNE_MAXVAL2 0x1158
#define USB3_DP_QSERDES_COM_VCO_TUNE_TIMER1 0x115C
#define USB3_DP_QSERDES_COM_VCO_TUNE_TIMER2 0x1160
#define USB3_DP_QSERDES_COM_CLK_SELECT 0x1164
#define USB3_DP_QSERDES_COM_PLL_ANALOG 0x1168
#define USB3_DP_QSERDES_COM_SW_RESET 0x116C
#define USB3_DP_QSERDES_COM_CORE_CLK_EN 0x1170
#define USB3_DP_QSERDES_COM_CMN_CONFIG_1 0x1174
#define USB3_DP_QSERDES_COM_CMN_RATE_OVERRIDE 0x1178
#define USB3_DP_QSERDES_COM_SVS_MODE_CLK_SEL 0x117C
#define USB3_DP_QSERDES_COM_DEBUG_BUS_SEL 0x1180
#define USB3_DP_QSERDES_COM_CMN_MISC1 0x1184
#define USB3_DP_QSERDES_COM_CMN_MODE 0x1188
#define USB3_DP_QSERDES_COM_CMN_MODE_CONTD 0x118C
#define USB3_DP_QSERDES_COM_CMN_MODE_CONTD1 0x1190
#define USB3_DP_QSERDES_COM_CMN_MODE_CONTD2 0x1194
#define USB3_DP_QSERDES_COM_VCO_DC_LEVEL_CTRL 0x1198
#define USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_1 0x119C
#define USB3_DP_QSERDES_COM_ADDITIONAL_CTRL_1 0x11A0
#define USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_1 0x11A4
#define USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_2 0x11A8
#define USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_3 0x11AC
#define USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_4 0x11B0
#define USB3_DP_QSERDES_COM_ADDITIONAL_MISC 0x11B4
#define USB3_DP_QSERDES_COM_ADDITIONAL_MISC_2 0x11B8
#define USB3_DP_QSERDES_COM_ADDITIONAL_MISC_3 0x11BC
#define USB3_DP_QSERDES_COM_ADDITIONAL_MISC_4 0x11C0
#define USB3_DP_QSERDES_COM_ADDITIONAL_MISC_5 0x11C4
#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE2 0x11C8
#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE2 0x11CC
#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE2 0x11D0
#define USB3_DP_QSERDES_COM_CLK_EP_DIV_MODE2 0x11D4
#define USB3_DP_QSERDES_COM_CP_CTRL_MODE2 0x11D8
#define USB3_DP_QSERDES_COM_PLL_RCTRL_MODE2 0x11DC
#define USB3_DP_QSERDES_COM_PLL_CCTRL_MODE2 0x11E0
#define USB3_DP_QSERDES_COM_CORECLK_DIV_MODE2 0x11E4
#define USB3_DP_QSERDES_COM_LOCK_CMP1_MODE2 0x11E8
#define USB3_DP_QSERDES_COM_LOCK_CMP2_MODE2 0x11EC
#define USB3_DP_QSERDES_COM_DEC_START_MODE2 0x11F0
#define USB3_DP_QSERDES_COM_DEC_START_MSB_MODE2 0x11F4
#define USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE2 0x11F8
#define USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE2 0x11FC
#define USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE2 0x1200
#define USB3_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE2 0x1204
#define USB3_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE2 0x1208
#define USB3_DP_QSERDES_COM_VCO_TUNE1_MODE2 0x120C
#define USB3_DP_QSERDES_COM_VCO_TUNE2_MODE2 0x1210
#define USB3_DP_QSERDES_COM_PLL_IVCO_MODE2 0x1214
#define USB3_DP_QSERDES_COM_HSCLK_SEL_2 0x1218
#define USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE2 0x121C
#define USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE2 0x1220
#define USB3_DP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_2 0x1224
#define USB3_DP_QSERDES_COM_CMN_CONFIG_2 0x1228
#define USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_2 0x122C
#define USB3_DP_QSERDES_COM_IVCOCAL_CONFIG_0 0x1230
#define USB3_DP_QSERDES_COM_IVCOCAL_CONFIG_1 0x1234
#define USB3_DP_QSERDES_COM_IVCOCAL_CONFIG_2 0x1238
#define USB3_DP_QSERDES_COM_IVCOCAL_CONFIG_3 0x123C
#define USB3_DP_QSERDES_COM_IVCOCAL_CONFIG_4 0x1240
#define USB3_DP_QSERDES_COM_IVCOCAL_CONFIG_5 0x1244
#define USB3_DP_QSERDES_COM_LOCK_CMP1_EARLY_MODE0 0x1248
#define USB3_DP_QSERDES_COM_LOCK_CMP2_EARLY_MODE0 0x124C
#define USB3_DP_QSERDES_COM_LOCK_CMP1_EARLY_MODE1 0x1250
#define USB3_DP_QSERDES_COM_LOCK_CMP2_EARLY_MODE1 0x1254
#define USB3_DP_QSERDES_COM_LOCK_CMP1_EARLY_MODE2 0x1258
#define USB3_DP_QSERDES_COM_LOCK_CMP2_EARLY_MODE2 0x125C
#define USB3_DP_QSERDES_COM_EARLY_LOCK_CONFIG_0 0x1260
#define USB3_DP_QSERDES_COM_EARLY_LOCK_CONFIG_1 0x1264
#define USB3_DP_QSERDES_COM_ADAPTIVE_ANALOG_CONFIG 0x1268
#define USB3_DP_QSERDES_COM_CP_CTRL_ADAPTIVE_MODE0 0x126C
#define USB3_DP_QSERDES_COM_PLL_RCCTRL_ADAPTIVE_MODE0 0x1270
#define USB3_DP_QSERDES_COM_PLL_CCTRL_ADAPTIVE_MODE0 0x1274
#define USB3_DP_QSERDES_COM_CP_CTRL_ADAPTIVE_MODE1 0x1278
#define USB3_DP_QSERDES_COM_PLL_RCCTRL_ADAPTIVE_MODE1 0x127C
#define USB3_DP_QSERDES_COM_PLL_CCTRL_ADAPTIVE_MODE1 0x1280
#define USB3_DP_QSERDES_COM_CP_CTRL_ADAPTIVE_MODE2 0x1284
#define USB3_DP_QSERDES_COM_PLL_RCCTRL_ADAPTIVE_MODE2 0x1288
#define USB3_DP_QSERDES_COM_PLL_CCTRL_ADAPTIVE_MODE2 0x128C
#define USB3_DP_QSERDES_COM_CMN_MODE_CONTD3 0x1290
#define USB3_DP_QSERDES_COM_CMN_MODE_CONTD4 0x1294
#define USB3_DP_QSERDES_COM_CMN_MODE_CONTD5 0x1298
#define USB3_DP_QSERDES_COM_CMN_MODE_CONTD6 0x129C
#define USB3_DP_QSERDES_COM_ADDITIONAL_MISC_6 0x12A0
#define USB3_DP_QSERDES_COM_ADDITIONAL_MISC_7 0x12A4
#define USB3_DP_QSERDES_COM_VCO_WAIT_CYCLES 0x12A8
#define USB3_DP_QSERDES_COM_BIAS_WAIT_CYCLES 0x12AC
#define USB3_DP_QSERDES_COM_AUX_CLK_PSM_ENABLE 0x12B0
#define USB3_DP_QSERDES_COM_PLL_SPARE_FOR_ECO 0x12B4
#define USB3_DP_QSERDES_COM_PLL_SPARE_FOR_ECO_1 0x12B8
#define USB3_DP_QSERDES_COM_PLL_SPARE_FOR_ECO_2 0x12BC
#define USB3_DP_QSERDES_COM_MODE_OPERATION_STATUS 0x12C0
#define USB3_DP_QSERDES_COM_SYSCLK_DET_COMP_STATUS 0x12C4
#define USB3_DP_QSERDES_COM_CMN_STATUS 0x12C8
#define USB3_DP_QSERDES_COM_RESET_SM_STATUS 0x12CC
#define USB3_DP_QSERDES_COM_RESTRIM_CODE_STATUS 0x12D0
#define USB3_DP_QSERDES_COM_PLLCAL_CODE1_STATUS 0x12D4
#define USB3_DP_QSERDES_COM_PLLCAL_CODE2_STATUS 0x12D8
#define USB3_DP_QSERDES_COM_INTEGLOOP_BINCODE_STATUS 0x12DC
#define USB3_DP_QSERDES_COM_DEBUG_BUS0 0x12E0
#define USB3_DP_QSERDES_COM_DEBUG_BUS1 0x12E4
#define USB3_DP_QSERDES_COM_DEBUG_BUS2 0x12E8
#define USB3_DP_QSERDES_COM_DEBUG_BUS3 0x12EC
#define USB3_DP_QSERDES_COM_C_READY_STATUS 0x12F0
#define USB3_DP_QSERDES_COM_READ_DUMMY_1 0x12F4
#define USB3_DP_QSERDES_COM_READ_DUMMY_2 0x12F8
#define USB3_DP_QSERDES_COM_READ_DUMMY_3 0x12FC
#define USB3_DP_QSERDES_COM_IVCO_CAL_CODE_STATUS 0x1300
/* Module: USB3_DP_PHY_USB3_QSERDES_TXA_USB3_QSERDES_TXA_USB3_DP_QMP_TX */
#define USB3_DP_QSERDES_TXA_BIST_MODE_LANENO 0x1400
#define USB3_DP_QSERDES_TXA_BIST_INVERT 0x1404
#define USB3_DP_QSERDES_TXA_CLKBUF_ENABLE 0x1408
#define USB3_DP_QSERDES_TXA_TX_EMP_POST1_LVL 0x140C
#define USB3_DP_QSERDES_TXA_TX_IDLE_LVL_LARGE_AMP 0x1410
#define USB3_DP_QSERDES_TXA_TX_DRV_LVL 0x1414
#define USB3_DP_QSERDES_TXA_TX_DRV_LVL_OFFSET 0x1418
#define USB3_DP_QSERDES_TXA_RESET_TSYNC_EN 0x141C
#define USB3_DP_QSERDES_TXA_PRE_STALL_LDO_BOOST_EN 0x1420
#define USB3_DP_QSERDES_TXA_TX_BAND 0x1424
#define USB3_DP_QSERDES_TXA_SLEW_CNTL 0x1428
#define USB3_DP_QSERDES_TXA_INTERFACE_SELECT 0x142C
#define USB3_DP_QSERDES_TXA_LPB_EN 0x1430
#define USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x1434
#define USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x1438
#define USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x143C
#define USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x1440
#define USB3_DP_QSERDES_TXA_PERL_LENGTH1 0x1444
#define USB3_DP_QSERDES_TXA_PERL_LENGTH2 0x1448
#define USB3_DP_QSERDES_TXA_SERDES_BYP_EN_OUT 0x144C
#define USB3_DP_QSERDES_TXA_DEBUG_BUS_SEL 0x1450
#define USB3_DP_QSERDES_TXA_TRANSCEIVER_BIAS_EN 0x1454
#define USB3_DP_QSERDES_TXA_HIGHZ_DRVR_EN 0x1458
#define USB3_DP_QSERDES_TXA_TX_POL_INV 0x145C
#define USB3_DP_QSERDES_TXA_PARRATE_REC_DETECT_IDLE_EN 0x1460
#define USB3_DP_QSERDES_TXA_BIST_PATTERN1 0x1464
#define USB3_DP_QSERDES_TXA_BIST_PATTERN2 0x1468
#define USB3_DP_QSERDES_TXA_BIST_PATTERN3 0x146C
#define USB3_DP_QSERDES_TXA_BIST_PATTERN4 0x1470
#define USB3_DP_QSERDES_TXA_BIST_PATTERN5 0x1474
#define USB3_DP_QSERDES_TXA_BIST_PATTERN6 0x1478
#define USB3_DP_QSERDES_TXA_BIST_PATTERN7 0x147C
#define USB3_DP_QSERDES_TXA_BIST_PATTERN8 0x1480
#define USB3_DP_QSERDES_TXA_LANE_MODE_1 0x1484
#define USB3_DP_QSERDES_TXA_LANE_MODE_2 0x1488
#define USB3_DP_QSERDES_TXA_LANE_MODE_3 0x148C
#define USB3_DP_QSERDES_TXA_LANE_MODE_4 0x1490
#define USB3_DP_QSERDES_TXA_LANE_MODE_5 0x1494
#define USB3_DP_QSERDES_TXA_ATB_SEL1 0x1498
#define USB3_DP_QSERDES_TXA_ATB_SEL2 0x149C
#define USB3_DP_QSERDES_TXA_RCV_DETECT_LVL 0x14A0
#define USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x14A4
#define USB3_DP_QSERDES_TXA_PRBS_SEED1 0x14A8
#define USB3_DP_QSERDES_TXA_PRBS_SEED2 0x14AC
#define USB3_DP_QSERDES_TXA_PRBS_SEED3 0x14B0
#define USB3_DP_QSERDES_TXA_PRBS_SEED4 0x14B4
#define USB3_DP_QSERDES_TXA_RESET_GEN 0x14B8
#define USB3_DP_QSERDES_TXA_RESET_GEN_MUXES 0x14BC
#define USB3_DP_QSERDES_TXA_TRAN_DRVR_EMP_EN 0x14C0
#define USB3_DP_QSERDES_TXA_TX_INTERFACE_MODE 0x14C4
#define USB3_DP_QSERDES_TXA_VMODE_CTRL1 0x14C8
#define USB3_DP_QSERDES_TXA_ALOG_OBSV_BUS_CTRL_1 0x14CC
#define USB3_DP_QSERDES_TXA_BIST_STATUS 0x14D0
#define USB3_DP_QSERDES_TXA_BIST_ERROR_COUNT1 0x14D4
#define USB3_DP_QSERDES_TXA_BIST_ERROR_COUNT2 0x14D8
#define USB3_DP_QSERDES_TXA_ALOG_OBSV_BUS_STATUS_1 0x14DC
#define USB3_DP_QSERDES_TXA_LANE_DIG_CONFIG 0x14E0
#define USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x14E4
#define USB3_DP_QSERDES_TXA_PRE_EMPH 0x14E8
#define USB3_DP_QSERDES_TXA_SW_RESET 0x14EC
#define USB3_DP_QSERDES_TXA_DCC_OFFSET 0x14F0
#define USB3_DP_QSERDES_TXA_DCC_CMUX_POSTCAL_OFFSET 0x14F4
#define USB3_DP_QSERDES_TXA_DCC_CMUX_CAL_CTRL1 0x14F8
#define USB3_DP_QSERDES_TXA_DCC_CMUX_CAL_CTRL2 0x14FC
#define USB3_DP_QSERDES_TXA_DIG_BKUP_CTRL 0x1500
#define USB3_DP_QSERDES_TXA_DEBUG_BUS0 0x1504
#define USB3_DP_QSERDES_TXA_DEBUG_BUS1 0x1508
#define USB3_DP_QSERDES_TXA_DEBUG_BUS2 0x150C
#define USB3_DP_QSERDES_TXA_DEBUG_BUS3 0x1510
#define USB3_DP_QSERDES_TXA_READ_EQCODE 0x1514
#define USB3_DP_QSERDES_TXA_READ_OFFSETCODE 0x1518
#define USB3_DP_QSERDES_TXA_IA_ERROR_COUNTER_LOW 0x151C
#define USB3_DP_QSERDES_TXA_IA_ERROR_COUNTER_HIGH 0x1520
#define USB3_DP_QSERDES_TXA_VGA_READ_CODE 0x1524
#define USB3_DP_QSERDES_TXA_VTH_READ_CODE 0x1528
#define USB3_DP_QSERDES_TXA_DFE_TAP1_READ_CODE 0x152C
#define USB3_DP_QSERDES_TXA_DFE_TAP2_READ_CODE 0x1530
#define USB3_DP_QSERDES_TXA_IDAC_STATUS_I 0x1534
#define USB3_DP_QSERDES_TXA_IDAC_STATUS_IBAR 0x1538
#define USB3_DP_QSERDES_TXA_IDAC_STATUS_Q 0x153C
#define USB3_DP_QSERDES_TXA_IDAC_STATUS_QBAR 0x1540
#define USB3_DP_QSERDES_TXA_IDAC_STATUS_A 0x1544
#define USB3_DP_QSERDES_TXA_IDAC_STATUS_ABAR 0x1548
#define USB3_DP_QSERDES_TXA_IDAC_STATUS_SM_ON 0x154C
#define USB3_DP_QSERDES_TXA_IDAC_STATUS_CAL_DONE 0x1550
#define USB3_DP_QSERDES_TXA_IDAC_STATUS_SIGNERROR 0x1554
#define USB3_DP_QSERDES_TXA_DCC_CAL_STATUS 0x1558
#define USB3_DP_QSERDES_TXA_DCC_READ_CODE_STATUS 0x155C
#define USB3_DP_QSERDES_TXA_SIGDET_CAL_ENGINE_STATUS 0x1560
#define USB3_DP_QSERDES_TXA_AC_JTAG_OUTP_OUTN_STATUS 0x1564
/* Module: USB3_DP_PHY_USB3_QSERDES_RXA_USB3_QSERDES_RXA_USB3_DP_QMP_RX */
#define USB3_DP_QSERDES_RXA_UCDR_FO_GAIN_HALF 0x1600
#define USB3_DP_QSERDES_RXA_UCDR_FO_GAIN_QUARTER 0x1604
#define USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x1608
#define USB3_DP_QSERDES_RXA_UCDR_SO_GAIN_HALF 0x160C
#define USB3_DP_QSERDES_RXA_UCDR_SO_GAIN_QUARTER 0x1610
#define USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x1614
#define USB3_DP_QSERDES_RXA_UCDR_SVS_FO_GAIN_HALF 0x1618
#define USB3_DP_QSERDES_RXA_UCDR_SVS_FO_GAIN_QUARTER 0x161C
#define USB3_DP_QSERDES_RXA_UCDR_SVS_FO_GAIN 0x1620
#define USB3_DP_QSERDES_RXA_UCDR_SVS_SO_GAIN_HALF 0x1624
#define USB3_DP_QSERDES_RXA_UCDR_SVS_SO_GAIN_QUARTER 0x1628
#define USB3_DP_QSERDES_RXA_UCDR_SVS_SO_GAIN 0x162C
#define USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x1630
#define USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x1634
#define USB3_DP_QSERDES_RXA_UCDR_FO_TO_SO_DELAY 0x1638
#define USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0x163C
#define USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x1640
#define USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x1644
#define USB3_DP_QSERDES_RXA_UCDR_PI_CTRL2 0x1648
#define USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x164C
#define USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x1650
#define USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x1654
#define USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x1658
#define USB3_DP_QSERDES_RXA_AUX_CONTROL 0x165C
#define USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0x1660
#define USB3_DP_QSERDES_RXA_RCLK_AUXDATA_SEL 0x1664
#define USB3_DP_QSERDES_RXA_AC_JTAG_ENABLE 0x1668
#define USB3_DP_QSERDES_RXA_AC_JTAG_INITP 0x166C
#define USB3_DP_QSERDES_RXA_AC_JTAG_INITN 0x1670
#define USB3_DP_QSERDES_RXA_AC_JTAG_LVL 0x1674
#define USB3_DP_QSERDES_RXA_AC_JTAG_MODE 0x1678
#define USB3_DP_QSERDES_RXA_AC_JTAG_RESET 0x167C
#define USB3_DP_QSERDES_RXA_RX_TERM_BW 0x1680
#define USB3_DP_QSERDES_RXA_RX_RCVR_IQ_EN 0x1684
#define USB3_DP_QSERDES_RXA_RX_IDAC_I_DC_OFFSETS 0x1688
#define USB3_DP_QSERDES_RXA_RX_IDAC_IBAR_DC_OFFSETS 0x168C
#define USB3_DP_QSERDES_RXA_RX_IDAC_Q_DC_OFFSETS 0x1690
#define USB3_DP_QSERDES_RXA_RX_IDAC_QBAR_DC_OFFSETS 0x1694
#define USB3_DP_QSERDES_RXA_RX_IDAC_A_DC_OFFSETS 0x1698
#define USB3_DP_QSERDES_RXA_RX_IDAC_ABAR_DC_OFFSETS 0x169C
#define USB3_DP_QSERDES_RXA_RX_IDAC_EN 0x16A0
#define USB3_DP_QSERDES_RXA_RX_IDAC_ENABLES 0x16A4
#define USB3_DP_QSERDES_RXA_RX_IDAC_SIGN 0x16A8
#define USB3_DP_QSERDES_RXA_RX_HIGHZ_HIGHRATE 0x16AC
#define USB3_DP_QSERDES_RXA_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x16B0
#define USB3_DP_QSERDES_RXA_DFE_1 0x16B4
#define USB3_DP_QSERDES_RXA_DFE_2 0x16B8
#define USB3_DP_QSERDES_RXA_DFE_3 0x16BC
#define USB3_DP_QSERDES_RXA_DFE_4 0x16C0
#define USB3_DP_QSERDES_RXA_TX_ADAPT_PRE_THRESH1 0x16C4
#define USB3_DP_QSERDES_RXA_TX_ADAPT_PRE_THRESH2 0x16C8
#define USB3_DP_QSERDES_RXA_TX_ADAPT_POST_THRESH 0x16CC
#define USB3_DP_QSERDES_RXA_TX_ADAPT_MAIN_THRESH 0x16D0
#define USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x16D4
#define USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x16D8
#define USB3_DP_QSERDES_RXA_GM_CAL 0x16DC
#define USB3_DP_QSERDES_RXA_RX_VGA_GAIN2_LSB 0x16E0
#define USB3_DP_QSERDES_RXA_RX_VGA_GAIN2_MSB 0x16E4
#define USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL1 0x16E8
#define USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x16EC
#define USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x16F0
#define USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x16F4
#define USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0x16F8
#define USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x16FC
#define USB3_DP_QSERDES_RXA_RX_IDAC_MEASURE_TIME 0x1700
#define USB3_DP_QSERDES_RXA_RX_IDAC_ACCUMULATOR 0x1704
#define USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_LSB 0x1708
#define USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_MSB 0x170C
#define USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1710
#define USB3_DP_QSERDES_RXA_RX_OFFSET_ADAPTOR_CNTRL2 0x1714
#define USB3_DP_QSERDES_RXA_SIGDET_ENABLES 0x1718
#define USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x171C
#define USB3_DP_QSERDES_RXA_SIGDET_LVL 0x1720
#define USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x1724
#define USB3_DP_QSERDES_RXA_RX_BAND 0x1728
#define USB3_DP_QSERDES_RXA_CDR_FREEZE_UP_DN 0x172C
#define USB3_DP_QSERDES_RXA_CDR_RESET_OVERRIDE 0x1730
#define USB3_DP_QSERDES_RXA_RX_INTERFACE_MODE 0x1734
#define USB3_DP_QSERDES_RXA_JITTER_GEN_MODE 0x1738
#define USB3_DP_QSERDES_RXA_SJ_AMP1 0x173C
#define USB3_DP_QSERDES_RXA_SJ_AMP2 0x1740
#define USB3_DP_QSERDES_RXA_SJ_PER1 0x1744
#define USB3_DP_QSERDES_RXA_SJ_PER2 0x1748
#define USB3_DP_QSERDES_RXA_PPM_OFFSET1 0x174C
#define USB3_DP_QSERDES_RXA_PPM_OFFSET2 0x1750
#define USB3_DP_QSERDES_RXA_SIGN_PPM_PERIOD1 0x1754
#define USB3_DP_QSERDES_RXA_SIGN_PPM_PERIOD2 0x1758
#define USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0x175C
#define USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x1760
#define USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0x1764
#define USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x1768
#define USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0x176C
#define USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0x1770
#define USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0x1774
#define USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0x1778
#define USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x177C
#define USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0x1780
#define USB3_DP_QSERDES_RXA_RX_MODE_10_LOW 0x1784
#define USB3_DP_QSERDES_RXA_RX_MODE_10_HIGH 0x1788
#define USB3_DP_QSERDES_RXA_RX_MODE_10_HIGH2 0x178C
#define USB3_DP_QSERDES_RXA_RX_MODE_10_HIGH3 0x1790
#define USB3_DP_QSERDES_RXA_RX_MODE_10_HIGH4 0x1794
#define USB3_DP_QSERDES_RXA_PHPRE_CTRL 0x1798
#define USB3_DP_QSERDES_RXA_PHPRE_INITVAL 0x179C
#define USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x17A0
#define USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x17A4
#define USB3_DP_QSERDES_RXA_DCC_CTRL1 0x17A8
#define USB3_DP_QSERDES_RXA_DCC_CTRL2 0x17AC
#define USB3_DP_QSERDES_RXA_VTH_CODE 0x17B0
#define USB3_DP_QSERDES_RXA_VTH_MIN_THRESH 0x17B4
#define USB3_DP_QSERDES_RXA_VTH_MAX_THRESH 0x17B8
#define USB3_DP_QSERDES_RXA_ALOG_OBSV_BUS_CTRL_1 0x17BC
#define USB3_DP_QSERDES_RXA_PI_CTRL1 0x17C0
#define USB3_DP_QSERDES_RXA_PI_CTRL2 0x17C4
#define USB3_DP_QSERDES_RXA_PI_QUAD 0x17C8
#define USB3_DP_QSERDES_RXA_IDATA1 0x17CC
#define USB3_DP_QSERDES_RXA_IDATA2 0x17D0
#define USB3_DP_QSERDES_RXA_AUX_DATA1 0x17D4
#define USB3_DP_QSERDES_RXA_AUX_DATA2 0x17D8
#define USB3_DP_QSERDES_RXA_RX_SIGDET_AND_CDR_FALSE_LOCK_STATUS 0x17DC
#define USB3_DP_QSERDES_RXA_ALOG_OBSV_BUS_STATUS_1 0x17E0
#define USB3_DP_QSERDES_RXA_SIGDET_CAL_CTRL1 0x17E4
#define USB3_DP_QSERDES_RXA_SIGDET_CAL_CTRL2_AND_CDR_LOCK_EDGE 0x17E8
#define USB3_DP_QSERDES_RXA_CDR_LOCK_ON_EDGE_DURATION 0x17EC
#define USB3_DP_QSERDES_RXA_CDR_LOCK_ON_EDGE_THRESH 0x17F0
#define USB3_DP_QSERDES_RXA_RX_ADAPTOR_CNTRL 0x17F4
#define USB3_DP_QSERDES_RXA_SIGDET_CAL_TRIM 0x17F8
#define USB3_DP_QSERDES_RXA_CAL_POST_WRAP 0x17FC
/* Module: USB3_DP_PHY_USB3_QSERDES_TXB_USB3_QSERDES_TXB_USB3_DP_QMP_TX */
#define USB3_DP_QSERDES_TXB_BIST_MODE_LANENO 0x1800
#define USB3_DP_QSERDES_TXB_BIST_INVERT 0x1804
#define USB3_DP_QSERDES_TXB_CLKBUF_ENABLE 0x1808
#define USB3_DP_QSERDES_TXB_TX_EMP_POST1_LVL 0x180C
#define USB3_DP_QSERDES_TXB_TX_IDLE_LVL_LARGE_AMP 0x1810
#define USB3_DP_QSERDES_TXB_TX_DRV_LVL 0x1814
#define USB3_DP_QSERDES_TXB_TX_DRV_LVL_OFFSET 0x1818
#define USB3_DP_QSERDES_TXB_RESET_TSYNC_EN 0x181C
#define USB3_DP_QSERDES_TXB_PRE_STALL_LDO_BOOST_EN 0x1820
#define USB3_DP_QSERDES_TXB_TX_BAND 0x1824
#define USB3_DP_QSERDES_TXB_SLEW_CNTL 0x1828
#define USB3_DP_QSERDES_TXB_INTERFACE_SELECT 0x182C
#define USB3_DP_QSERDES_TXB_LPB_EN 0x1830
#define USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x1834
#define USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x1838
#define USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x183C
#define USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x1840
#define USB3_DP_QSERDES_TXB_PERL_LENGTH1 0x1844
#define USB3_DP_QSERDES_TXB_PERL_LENGTH2 0x1848
#define USB3_DP_QSERDES_TXB_SERDES_BYP_EN_OUT 0x184C
#define USB3_DP_QSERDES_TXB_DEBUG_BUS_SEL 0x1850
#define USB3_DP_QSERDES_TXB_TRANSCEIVER_BIAS_EN 0x1854
#define USB3_DP_QSERDES_TXB_HIGHZ_DRVR_EN 0x1858
#define USB3_DP_QSERDES_TXB_TX_POL_INV 0x185C
#define USB3_DP_QSERDES_TXB_PARRATE_REC_DETECT_IDLE_EN 0x1860
#define USB3_DP_QSERDES_TXB_BIST_PATTERN1 0x1864
#define USB3_DP_QSERDES_TXB_BIST_PATTERN2 0x1868
#define USB3_DP_QSERDES_TXB_BIST_PATTERN3 0x186C
#define USB3_DP_QSERDES_TXB_BIST_PATTERN4 0x1870
#define USB3_DP_QSERDES_TXB_BIST_PATTERN5 0x1874
#define USB3_DP_QSERDES_TXB_BIST_PATTERN6 0x1878
#define USB3_DP_QSERDES_TXB_BIST_PATTERN7 0x187C
#define USB3_DP_QSERDES_TXB_BIST_PATTERN8 0x1880
#define USB3_DP_QSERDES_TXB_LANE_MODE_1 0x1884
#define USB3_DP_QSERDES_TXB_LANE_MODE_2 0x1888
#define USB3_DP_QSERDES_TXB_LANE_MODE_3 0x188C
#define USB3_DP_QSERDES_TXB_LANE_MODE_4 0x1890
#define USB3_DP_QSERDES_TXB_LANE_MODE_5 0x1894
#define USB3_DP_QSERDES_TXB_ATB_SEL1 0x1898
#define USB3_DP_QSERDES_TXB_ATB_SEL2 0x189C
#define USB3_DP_QSERDES_TXB_RCV_DETECT_LVL 0x18A0
#define USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x18A4
#define USB3_DP_QSERDES_TXB_PRBS_SEED1 0x18A8
#define USB3_DP_QSERDES_TXB_PRBS_SEED2 0x18AC
#define USB3_DP_QSERDES_TXB_PRBS_SEED3 0x18B0
#define USB3_DP_QSERDES_TXB_PRBS_SEED4 0x18B4
#define USB3_DP_QSERDES_TXB_RESET_GEN 0x18B8
#define USB3_DP_QSERDES_TXB_RESET_GEN_MUXES 0x18BC
#define USB3_DP_QSERDES_TXB_TRAN_DRVR_EMP_EN 0x18C0
#define USB3_DP_QSERDES_TXB_TX_INTERFACE_MODE 0x18C4
#define USB3_DP_QSERDES_TXB_VMODE_CTRL1 0x18C8
#define USB3_DP_QSERDES_TXB_ALOG_OBSV_BUS_CTRL_1 0x18CC
#define USB3_DP_QSERDES_TXB_BIST_STATUS 0x18D0
#define USB3_DP_QSERDES_TXB_BIST_ERROR_COUNT1 0x18D4
#define USB3_DP_QSERDES_TXB_BIST_ERROR_COUNT2 0x18D8
#define USB3_DP_QSERDES_TXB_ALOG_OBSV_BUS_STATUS_1 0x18DC
#define USB3_DP_QSERDES_TXB_LANE_DIG_CONFIG 0x18E0
#define USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x18E4
#define USB3_DP_QSERDES_TXB_PRE_EMPH 0x18E8
#define USB3_DP_QSERDES_TXB_SW_RESET 0x18EC
#define USB3_DP_QSERDES_TXB_DCC_OFFSET 0x18F0
#define USB3_DP_QSERDES_TXB_DCC_CMUX_POSTCAL_OFFSET 0x18F4
#define USB3_DP_QSERDES_TXB_DCC_CMUX_CAL_CTRL1 0x18F8
#define USB3_DP_QSERDES_TXB_DCC_CMUX_CAL_CTRL2 0x18FC
#define USB3_DP_QSERDES_TXB_DIG_BKUP_CTRL 0x1900
#define USB3_DP_QSERDES_TXB_DEBUG_BUS0 0x1904
#define USB3_DP_QSERDES_TXB_DEBUG_BUS1 0x1908
#define USB3_DP_QSERDES_TXB_DEBUG_BUS2 0x190C
#define USB3_DP_QSERDES_TXB_DEBUG_BUS3 0x1910
#define USB3_DP_QSERDES_TXB_READ_EQCODE 0x1914
#define USB3_DP_QSERDES_TXB_READ_OFFSETCODE 0x1918
#define USB3_DP_QSERDES_TXB_IA_ERROR_COUNTER_LOW 0x191C
#define USB3_DP_QSERDES_TXB_IA_ERROR_COUNTER_HIGH 0x1920
#define USB3_DP_QSERDES_TXB_VGA_READ_CODE 0x1924
#define USB3_DP_QSERDES_TXB_VTH_READ_CODE 0x1928
#define USB3_DP_QSERDES_TXB_DFE_TAP1_READ_CODE 0x192C
#define USB3_DP_QSERDES_TXB_DFE_TAP2_READ_CODE 0x1930
#define USB3_DP_QSERDES_TXB_IDAC_STATUS_I 0x1934
#define USB3_DP_QSERDES_TXB_IDAC_STATUS_IBAR 0x1938
#define USB3_DP_QSERDES_TXB_IDAC_STATUS_Q 0x193C
#define USB3_DP_QSERDES_TXB_IDAC_STATUS_QBAR 0x1940
#define USB3_DP_QSERDES_TXB_IDAC_STATUS_A 0x1944
#define USB3_DP_QSERDES_TXB_IDAC_STATUS_ABAR 0x1948
#define USB3_DP_QSERDES_TXB_IDAC_STATUS_SM_ON 0x194C
#define USB3_DP_QSERDES_TXB_IDAC_STATUS_CAL_DONE 0x1950
#define USB3_DP_QSERDES_TXB_IDAC_STATUS_SIGNERROR 0x1954
#define USB3_DP_QSERDES_TXB_DCC_CAL_STATUS 0x1958
#define USB3_DP_QSERDES_TXB_DCC_READ_CODE_STATUS 0x195C
#define USB3_DP_QSERDES_TXB_SIGDET_CAL_ENGINE_STATUS 0x1960
#define USB3_DP_QSERDES_TXB_AC_JTAG_OUTP_OUTN_STATUS 0x1964
/* Module: USB3_DP_PHY_USB3_QSERDES_RXB_USB3_QSERDES_RXB_USB3_DP_QMP_RX */
#define USB3_DP_QSERDES_RXB_UCDR_FO_GAIN_HALF 0x1A00
#define USB3_DP_QSERDES_RXB_UCDR_FO_GAIN_QUARTER 0x1A04
#define USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x1A08
#define USB3_DP_QSERDES_RXB_UCDR_SO_GAIN_HALF 0x1A0C
#define USB3_DP_QSERDES_RXB_UCDR_SO_GAIN_QUARTER 0x1A10
#define USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x1A14
#define USB3_DP_QSERDES_RXB_UCDR_SVS_FO_GAIN_HALF 0x1A18
#define USB3_DP_QSERDES_RXB_UCDR_SVS_FO_GAIN_QUARTER 0x1A1C
#define USB3_DP_QSERDES_RXB_UCDR_SVS_FO_GAIN 0x1A20
#define USB3_DP_QSERDES_RXB_UCDR_SVS_SO_GAIN_HALF 0x1A24
#define USB3_DP_QSERDES_RXB_UCDR_SVS_SO_GAIN_QUARTER 0x1A28
#define USB3_DP_QSERDES_RXB_UCDR_SVS_SO_GAIN 0x1A2C
#define USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x1A30
#define USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x1A34
#define USB3_DP_QSERDES_RXB_UCDR_FO_TO_SO_DELAY 0x1A38
#define USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0x1A3C
#define USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x1A40
#define USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x1A44
#define USB3_DP_QSERDES_RXB_UCDR_PI_CTRL2 0x1A48
#define USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x1A4C
#define USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x1A50
#define USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x1A54
#define USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x1A58
#define USB3_DP_QSERDES_RXB_AUX_CONTROL 0x1A5C
#define USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0x1A60
#define USB3_DP_QSERDES_RXB_RCLK_AUXDATA_SEL 0x1A64
#define USB3_DP_QSERDES_RXB_AC_JTAG_ENABLE 0x1A68
#define USB3_DP_QSERDES_RXB_AC_JTAG_INITP 0x1A6C
#define USB3_DP_QSERDES_RXB_AC_JTAG_INITN 0x1A70
#define USB3_DP_QSERDES_RXB_AC_JTAG_LVL 0x1A74
#define USB3_DP_QSERDES_RXB_AC_JTAG_MODE 0x1A78
#define USB3_DP_QSERDES_RXB_AC_JTAG_RESET 0x1A7C
#define USB3_DP_QSERDES_RXB_RX_TERM_BW 0x1A80
#define USB3_DP_QSERDES_RXB_RX_RCVR_IQ_EN 0x1A84
#define USB3_DP_QSERDES_RXB_RX_IDAC_I_DC_OFFSETS 0x1A88
#define USB3_DP_QSERDES_RXB_RX_IDAC_IBAR_DC_OFFSETS 0x1A8C
#define USB3_DP_QSERDES_RXB_RX_IDAC_Q_DC_OFFSETS 0x1A90
#define USB3_DP_QSERDES_RXB_RX_IDAC_QBAR_DC_OFFSETS 0x1A94
#define USB3_DP_QSERDES_RXB_RX_IDAC_A_DC_OFFSETS 0x1A98
#define USB3_DP_QSERDES_RXB_RX_IDAC_ABAR_DC_OFFSETS 0x1A9C
#define USB3_DP_QSERDES_RXB_RX_IDAC_EN 0x1AA0
#define USB3_DP_QSERDES_RXB_RX_IDAC_ENABLES 0x1AA4
#define USB3_DP_QSERDES_RXB_RX_IDAC_SIGN 0x1AA8
#define USB3_DP_QSERDES_RXB_RX_HIGHZ_HIGHRATE 0x1AAC
#define USB3_DP_QSERDES_RXB_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x1AB0
#define USB3_DP_QSERDES_RXB_DFE_1 0x1AB4
#define USB3_DP_QSERDES_RXB_DFE_2 0x1AB8
#define USB3_DP_QSERDES_RXB_DFE_3 0x1ABC
#define USB3_DP_QSERDES_RXB_DFE_4 0x1AC0
#define USB3_DP_QSERDES_RXB_TX_ADAPT_PRE_THRESH1 0x1AC4
#define USB3_DP_QSERDES_RXB_TX_ADAPT_PRE_THRESH2 0x1AC8
#define USB3_DP_QSERDES_RXB_TX_ADAPT_POST_THRESH 0x1ACC
#define USB3_DP_QSERDES_RXB_TX_ADAPT_MAIN_THRESH 0x1AD0
#define USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x1AD4
#define USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x1AD8
#define USB3_DP_QSERDES_RXB_GM_CAL 0x1ADC
#define USB3_DP_QSERDES_RXB_RX_VGA_GAIN2_LSB 0x1AE0
#define USB3_DP_QSERDES_RXB_RX_VGA_GAIN2_MSB 0x1AE4
#define USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL1 0x1AE8
#define USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x1AEC
#define USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x1AF0
#define USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x1AF4
#define USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0x1AF8
#define USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x1AFC
#define USB3_DP_QSERDES_RXB_RX_IDAC_MEASURE_TIME 0x1B00
#define USB3_DP_QSERDES_RXB_RX_IDAC_ACCUMULATOR 0x1B04
#define USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_LSB 0x1B08
#define USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_MSB 0x1B0C
#define USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1B10
#define USB3_DP_QSERDES_RXB_RX_OFFSET_ADAPTOR_CNTRL2 0x1B14
#define USB3_DP_QSERDES_RXB_SIGDET_ENABLES 0x1B18
#define USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x1B1C
#define USB3_DP_QSERDES_RXB_SIGDET_LVL 0x1B20
#define USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x1B24
#define USB3_DP_QSERDES_RXB_RX_BAND 0x1B28
#define USB3_DP_QSERDES_RXB_CDR_FREEZE_UP_DN 0x1B2C
#define USB3_DP_QSERDES_RXB_CDR_RESET_OVERRIDE 0x1B30
#define USB3_DP_QSERDES_RXB_RX_INTERFACE_MODE 0x1B34
#define USB3_DP_QSERDES_RXB_JITTER_GEN_MODE 0x1B38
#define USB3_DP_QSERDES_RXB_SJ_AMP1 0x1B3C
#define USB3_DP_QSERDES_RXB_SJ_AMP2 0x1B40
#define USB3_DP_QSERDES_RXB_SJ_PER1 0x1B44
#define USB3_DP_QSERDES_RXB_SJ_PER2 0x1B48
#define USB3_DP_QSERDES_RXB_PPM_OFFSET1 0x1B4C
#define USB3_DP_QSERDES_RXB_PPM_OFFSET2 0x1B50
#define USB3_DP_QSERDES_RXB_SIGN_PPM_PERIOD1 0x1B54
#define USB3_DP_QSERDES_RXB_SIGN_PPM_PERIOD2 0x1B58
#define USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0x1B5C
#define USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0x1B60
#define USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0x1B64
#define USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x1B68
#define USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0x1B6C
#define USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0x1B70
#define USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0x1B74
#define USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0x1B78
#define USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x1B7C
#define USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0x1B80
#define USB3_DP_QSERDES_RXB_RX_MODE_10_LOW 0x1B84
#define USB3_DP_QSERDES_RXB_RX_MODE_10_HIGH 0x1B88
#define USB3_DP_QSERDES_RXB_RX_MODE_10_HIGH2 0x1B8C
#define USB3_DP_QSERDES_RXB_RX_MODE_10_HIGH3 0x1B90
#define USB3_DP_QSERDES_RXB_RX_MODE_10_HIGH4 0x1B94
#define USB3_DP_QSERDES_RXB_PHPRE_CTRL 0x1B98
#define USB3_DP_QSERDES_RXB_PHPRE_INITVAL 0x1B9C
#define USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x1BA0
#define USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x1BA4
#define USB3_DP_QSERDES_RXB_DCC_CTRL1 0x1BA8
#define USB3_DP_QSERDES_RXB_DCC_CTRL2 0x1BAC
#define USB3_DP_QSERDES_RXB_VTH_CODE 0x1BB0
#define USB3_DP_QSERDES_RXB_VTH_MIN_THRESH 0x1BB4
#define USB3_DP_QSERDES_RXB_VTH_MAX_THRESH 0x1BB8
#define USB3_DP_QSERDES_RXB_ALOG_OBSV_BUS_CTRL_1 0x1BBC
#define USB3_DP_QSERDES_RXB_PI_CTRL1 0x1BC0
#define USB3_DP_QSERDES_RXB_PI_CTRL2 0x1BC4
#define USB3_DP_QSERDES_RXB_PI_QUAD 0x1BC8
#define USB3_DP_QSERDES_RXB_IDATA1 0x1BCC
#define USB3_DP_QSERDES_RXB_IDATA2 0x1BD0
#define USB3_DP_QSERDES_RXB_AUX_DATA1 0x1BD4
#define USB3_DP_QSERDES_RXB_AUX_DATA2 0x1BD8
#define USB3_DP_QSERDES_RXB_RX_SIGDET_AND_CDR_FALSE_LOCK_STATUS 0x1BDC
#define USB3_DP_QSERDES_RXB_ALOG_OBSV_BUS_STATUS_1 0x1BE0
#define USB3_DP_QSERDES_RXB_SIGDET_CAL_CTRL1 0x1BE4
#define USB3_DP_QSERDES_RXB_SIGDET_CAL_CTRL2_AND_CDR_LOCK_EDGE 0x1BE8
#define USB3_DP_QSERDES_RXB_CDR_LOCK_ON_EDGE_DURATION 0x1BEC
#define USB3_DP_QSERDES_RXB_CDR_LOCK_ON_EDGE_THRESH 0x1BF0
#define USB3_DP_QSERDES_RXB_RX_ADAPTOR_CNTRL 0x1BF4
#define USB3_DP_QSERDES_RXB_SIGDET_CAL_TRIM 0x1BF8
#define USB3_DP_QSERDES_RXB_CAL_POST_WRAP 0x1BFC
/* Module: USB3_DP_PHY_USB3_PCS_MISC_USB3_PCS_MISC_USB3_PCS_MISC */
#define USB3_DP_PCS_MISC_TYPEC_CTRL 0x1C00
#define USB3_DP_PCS_MISC_TYPEC_PWRDN_CTRL 0x1C04
#define USB3_DP_PCS_MISC_PCS_MISC_CONFIG1 0x1C08
#define USB3_DP_PCS_MISC_CLAMP_ENABLE 0x1C0C
#define USB3_DP_PCS_MISC_TYPEC_STATUS 0x1C10
#define USB3_DP_PCS_MISC_PLACEHOLDER_STATUS 0x1C14
/* Module: USB3_DP_PHY_USB3_PCS_LN_USB3_PCS_LN_USB3_PCS_LANE */
#define USB3_DP_PCS_LN_PCS_STATUS1 0x1D00
#define USB3_DP_PCS_LN_PCS_STATUS2 0x1D04
#define USB3_DP_PCS_LN_PCS_STATUS2_CLEAR 0x1D08
#define USB3_DP_PCS_LN_PCS_STATUS3 0x1D0C
#define USB3_DP_PCS_LN_BIST_CHK_ERR_CNT_L_STATUS 0x1D10
#define USB3_DP_PCS_LN_BIST_CHK_ERR_CNT_H_STATUS 0x1D14
#define USB3_DP_PCS_LN_BIST_CHK_STATUS 0x1D18
#define USB3_DP_PCS_LN_INSIG_SW_CTRL1 0x1D1C
#define USB3_DP_PCS_LN_INSIG_MX_CTRL1 0x1D20
#define USB3_DP_PCS_LN_OUTSIG_SW_CTRL1 0x1D24
#define USB3_DP_PCS_LN_OUTSIG_MX_CTRL1 0x1D28
#define USB3_DP_PCS_LN_TEST_CONTROL1 0x1D2C
#define USB3_DP_PCS_LN_BIST_CTRL 0x1D30
#define USB3_DP_PCS_LN_PRBS_SEED0 0x1D34
#define USB3_DP_PCS_LN_PRBS_SEED1 0x1D38
#define USB3_DP_PCS_LN_FIXED_PAT_CTRL 0x1D3C
#define USB3_DP_PCS_LN_EQ_CONFIG 0x1D40
#define USB3_DP_PCS_LN_TEST_CONTROL2 0x1D44
#define USB3_DP_PCS_LN_TEST_CONTROL3 0x1D48
/* Module: USB3_DP_PHY_USB3_PCS_USB3_PCS_USB3_PCS */
#define USB3_DP_PCS_SW_RESET 0x1E00
#define USB3_DP_PCS_REVISION_ID0 0x1E04
#define USB3_DP_PCS_REVISION_ID1 0x1E08
#define USB3_DP_PCS_REVISION_ID2 0x1E0C
#define USB3_DP_PCS_REVISION_ID3 0x1E10
#define USB3_DP_PCS_PCS_STATUS1 0x1E14
#define USB3_DP_PCS_PCS_STATUS2 0x1E18
#define USB3_DP_PCS_PCS_STATUS3 0x1E1C
#define USB3_DP_PCS_PCS_STATUS4 0x1E20
#define USB3_DP_PCS_PCS_STATUS5 0x1E24
#define USB3_DP_PCS_PCS_STATUS6 0x1E28
#define USB3_DP_PCS_PCS_STATUS7 0x1E2C
#define USB3_DP_PCS_DEBUG_BUS_0_STATUS 0x1E30
#define USB3_DP_PCS_DEBUG_BUS_1_STATUS 0x1E34
#define USB3_DP_PCS_DEBUG_BUS_2_STATUS 0x1E38
#define USB3_DP_PCS_DEBUG_BUS_3_STATUS 0x1E3C
#define USB3_DP_PCS_POWER_DOWN_CONTROL 0x1E40
#define USB3_DP_PCS_START_CONTROL 0x1E44
#define USB3_DP_PCS_INSIG_SW_CTRL1 0x1E48
#define USB3_DP_PCS_INSIG_SW_CTRL2 0x1E4C
#define USB3_DP_PCS_INSIG_SW_CTRL3 0x1E50
#define USB3_DP_PCS_INSIG_SW_CTRL4 0x1E54
#define USB3_DP_PCS_INSIG_SW_CTRL5 0x1E58
#define USB3_DP_PCS_INSIG_SW_CTRL6 0x1E5C
#define USB3_DP_PCS_INSIG_SW_CTRL7 0x1E60
#define USB3_DP_PCS_INSIG_SW_CTRL8 0x1E64
#define USB3_DP_PCS_INSIG_MX_CTRL1 0x1E68
#define USB3_DP_PCS_INSIG_MX_CTRL2 0x1E6C
#define USB3_DP_PCS_INSIG_MX_CTRL3 0x1E70
#define USB3_DP_PCS_INSIG_MX_CTRL4 0x1E74
#define USB3_DP_PCS_INSIG_MX_CTRL5 0x1E78
#define USB3_DP_PCS_INSIG_MX_CTRL7 0x1E7C
#define USB3_DP_PCS_INSIG_MX_CTRL8 0x1E80
#define USB3_DP_PCS_OUTSIG_SW_CTRL1 0x1E84
#define USB3_DP_PCS_OUTSIG_MX_CTRL1 0x1E88
#define USB3_DP_PCS_CLAMP_ENABLE 0x1E8C
#define USB3_DP_PCS_POWER_STATE_CONFIG1 0x1E90
#define USB3_DP_PCS_POWER_STATE_CONFIG2 0x1E94
#define USB3_DP_PCS_FLL_CNTRL1 0x1E98
#define USB3_DP_PCS_FLL_CNTRL2 0x1E9C
#define USB3_DP_PCS_FLL_CNT_VAL_L 0x1EA0
#define USB3_DP_PCS_FLL_CNT_VAL_H_TOL 0x1EA4
#define USB3_DP_PCS_FLL_MAN_CODE 0x1EA8
#define USB3_DP_PCS_TEST_CONTROL1 0x1EAC
#define USB3_DP_PCS_TEST_CONTROL2 0x1EB0
#define USB3_DP_PCS_TEST_CONTROL3 0x1EB4
#define USB3_DP_PCS_TEST_CONTROL4 0x1EB8
#define USB3_DP_PCS_TEST_CONTROL5 0x1EBC
#define USB3_DP_PCS_TEST_CONTROL6 0x1EC0
#define USB3_DP_PCS_LOCK_DETECT_CONFIG1 0x1EC4
#define USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x1EC8
#define USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x1ECC
#define USB3_DP_PCS_LOCK_DETECT_CONFIG4 0x1ED0
#define USB3_DP_PCS_LOCK_DETECT_CONFIG5 0x1ED4
#define USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x1ED8
#define USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x1EDC
#define USB3_DP_PCS_REFGEN_REQ_CONFIG2 0x1EE0
#define USB3_DP_PCS_REFGEN_REQ_CONFIG3 0x1EE4
#define USB3_DP_PCS_BIST_CTRL 0x1EE8
#define USB3_DP_PCS_PRBS_POLY0 0x1EEC
#define USB3_DP_PCS_PRBS_POLY1 0x1EF0
#define USB3_DP_PCS_FIXED_PAT0 0x1EF4
#define USB3_DP_PCS_FIXED_PAT1 0x1EF8
#define USB3_DP_PCS_FIXED_PAT2 0x1EFC
#define USB3_DP_PCS_FIXED_PAT3 0x1F00
#define USB3_DP_PCS_FIXED_PAT4 0x1F04
#define USB3_DP_PCS_FIXED_PAT5 0x1F08
#define USB3_DP_PCS_FIXED_PAT6 0x1F0C
#define USB3_DP_PCS_FIXED_PAT7 0x1F10
#define USB3_DP_PCS_FIXED_PAT8 0x1F14
#define USB3_DP_PCS_FIXED_PAT9 0x1F18
#define USB3_DP_PCS_FIXED_PAT10 0x1F1C
#define USB3_DP_PCS_FIXED_PAT11 0x1F20
#define USB3_DP_PCS_FIXED_PAT12 0x1F24
#define USB3_DP_PCS_FIXED_PAT13 0x1F28
#define USB3_DP_PCS_FIXED_PAT14 0x1F2C
#define USB3_DP_PCS_FIXED_PAT15 0x1F30
#define USB3_DP_PCS_TXMGN_CONFIG 0x1F34
#define USB3_DP_PCS_G12S1_TXMGN_V0 0x1F38
#define USB3_DP_PCS_G12S1_TXMGN_V1 0x1F3C
#define USB3_DP_PCS_G12S1_TXMGN_V2 0x1F40
#define USB3_DP_PCS_G12S1_TXMGN_V3 0x1F44
#define USB3_DP_PCS_G12S1_TXMGN_V4 0x1F48
#define USB3_DP_PCS_G12S1_TXMGN_V0_RS 0x1F4C
#define USB3_DP_PCS_G12S1_TXMGN_V1_RS 0x1F50
#define USB3_DP_PCS_G12S1_TXMGN_V2_RS 0x1F54
#define USB3_DP_PCS_G12S1_TXMGN_V3_RS 0x1F58
#define USB3_DP_PCS_G12S1_TXMGN_V4_RS 0x1F5C
#define USB3_DP_PCS_G3S2_TXMGN_MAIN 0x1F60
#define USB3_DP_PCS_G3S2_TXMGN_MAIN_RS 0x1F64
#define USB3_DP_PCS_G12S1_TXDEEMPH_M6DB 0x1F68
#define USB3_DP_PCS_G12S1_TXDEEMPH_M3P5DB 0x1F6C
#define USB3_DP_PCS_G3S2_PRE_GAIN 0x1F70
#define USB3_DP_PCS_G3S2_POST_GAIN 0x1F74
#define USB3_DP_PCS_G3S2_PRE_POST_OFFSET 0x1F78
#define USB3_DP_PCS_G3S2_PRE_GAIN_RS 0x1F7C
#define USB3_DP_PCS_G3S2_POST_GAIN_RS 0x1F80
#define USB3_DP_PCS_G3S2_PRE_POST_OFFSET_RS 0x1F84
#define USB3_DP_PCS_RX_SIGDET_LVL 0x1F88
#define USB3_DP_PCS_RX_SIGDET_DTCT_CNTRL 0x1F8C
#define USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_L 0x1F90
#define USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_H 0x1F94
#define USB3_DP_PCS_RATE_SLEW_CNTRL1 0x1F98
#define USB3_DP_PCS_RATE_SLEW_CNTRL2 0x1F9C
#define USB3_DP_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1FA0
#define USB3_DP_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1FA4
#define USB3_DP_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1FA8
#define USB3_DP_PCS_TSYNC_RSYNC_TIME 0x1FAC
#define USB3_DP_PCS_CDR_RESET_TIME 0x1FB0
#define USB3_DP_PCS_TSYNC_DLY_TIME 0x1FB4
#define USB3_DP_PCS_ELECIDLE_DLY_SEL 0x1FB8
#define USB3_DP_PCS_CMN_ACK_OUT_SEL 0x1FBC
#define USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x1FC0
#define USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x1FC4
#define USB3_DP_PCS_ALIGN_DETECT_CONFIG3 0x1FC8
#define USB3_DP_PCS_ALIGN_DETECT_CONFIG4 0x1FCC
#define USB3_DP_PCS_PCS_TX_RX_CONFIG 0x1FD0
#define USB3_DP_PCS_RX_IDLE_DTCT_CNTRL 0x1FD4
#define USB3_DP_PCS_RX_DCC_CAL_CONFIG 0x1FD8
#define USB3_DP_PCS_EQ_CONFIG1 0x1FDC
#define USB3_DP_PCS_EQ_CONFIG2 0x1FE0
#define USB3_DP_PCS_EQ_CONFIG3 0x1FE4
#define USB3_DP_PCS_EQ_CONFIG4 0x1FE8
#define USB3_DP_PCS_EQ_CONFIG5 0x1FEC
/* Module: USB3_DP_PHY_USB3_PCS_AON_USB3_PCS_AON_USB3_PCS_AON */
#define USB3_DP_PCS_AON_CLAMP_ENABLE 0x2000
/* Module: USB3_DP_PHY_USB3_PCS_USB3_USB3_PCS_USB3_USB3_PCS_USB3 */
#define USB3_DP_PCS_USB3_POWER_STATE_CONFIG1 0x2100
#define USB3_DP_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x2104
#define USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x2108
#define USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x210C
#define USB3_DP_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x2110
#define USB3_DP_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x2114
#define USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x2118
#define USB3_DP_PCS_USB3_LFPS_TX_ECSTART 0x211C
#define USB3_DP_PCS_USB3_LFPS_PER_TIMER_VAL 0x2120
#define USB3_DP_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x2124
#define USB3_DP_PCS_USB3_LFPS_CONFIG1 0x2128
#define USB3_DP_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x212C
#define USB3_DP_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x2130
#define USB3_DP_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x2134
#define USB3_DP_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x2138
#define USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x213C
#define USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x2140
#define USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x2144
#define USB3_DP_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x2148
#define USB3_DP_PCS_USB3_ARCVR_DTCT_CM_DLY 0x214C
#define USB3_DP_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x2150
#define USB3_DP_PCS_USB3_ALFPS_DEGLITCH_VAL 0x2154
#define USB3_DP_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x2158
#define USB3_DP_PCS_USB3_TEST_CONTROL 0x215C
#define USB3_DP_PCS_USB3_RXTERMINATION_DLY_SEL 0x2160
#define USB3_DP_PCS_USB3_POWER_STATE_CONFIG2 0x2164
#define USB3_DP_PCS_USB3_POWER_STATE_CONFIG3 0x2168
#define USB3_DP_PCS_USB3_POWER_STATE_CONFIG4 0x216C
#endif /* _DT_BINDINGS_PHY_QCOM_3NM_QMP_COMBO_USB_H */

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include/dt-bindings/phy/qcom,usb3-4nm-qmp-combo.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_PHY_QCOM_4NM_QMP_COMBO_USB_H
#define _DT_BINDINGS_PHY_QCOM_4NM_QMP_COMBO_USB_H
/* USB3-DP Combo PHY register offsets */
/* Module: USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM */
#define USB3_DP_COM_PHY_MODE_CTRL 0x0000
#define USB3_DP_COM_SW_RESET 0x0004
#define USB3_DP_COM_POWER_DOWN_CTRL 0x0008
#define USB3_DP_COM_SWI_CTRL 0x000C
#define USB3_DP_COM_TYPEC_CTRL 0x0010
#define USB3_DP_COM_TYPEC_PWRDN_CTRL 0x0014
#define USB3_DP_COM_DP_BIST_CFG_0 0x0018
#define USB3_DP_COM_RESET_OVRD_CTRL 0x001C
#define USB3_DP_COM_DBG_CLK_MUX_CTRL 0x0020
#define USB3_DP_COM_TYPEC_STATUS 0x0024
#define USB3_DP_COM_PLACEHOLDER_STATUS 0x0028
#define USB3_DP_COM_REVISION_ID0 0x002C
#define USB3_DP_COM_REVISION_ID1 0x0030
#define USB3_DP_COM_REVISION_ID2 0x0034
#define USB3_DP_COM_REVISION_ID3 0x0038
/* Module: USB3_DP_PHY_USB3_DP_DBGINT_USB3_DP_DBGINT_USB3_PCS_DEBUG_INT */
#define USB3_DP_DBGINT_INTGEN_STATUS1 0x0200
#define USB3_DP_DBGINT_INTGEN_STATUS2 0x0204
#define USB3_DP_DBGINT_CONFIG1 0x0208
#define USB3_DP_DBGINT_SIGNALBLK1_CONFIG1 0x020C
#define USB3_DP_DBGINT_SIGNALBLK1_CONFIG2 0x0210
#define USB3_DP_DBGINT_SIGNALBLK1_CONFIG3 0x0214
#define USB3_DP_DBGINT_SIGNALBLK1_CONFIG4 0x0218
#define USB3_DP_DBGINT_SIGNALBLK1_CONFIG5 0x021C
#define USB3_DP_DBGINT_SIGNALBLK2_CONFIG1 0x0220
#define USB3_DP_DBGINT_SIGNALBLK2_CONFIG2 0x0224
#define USB3_DP_DBGINT_SIGNALBLK2_CONFIG3 0x0228
#define USB3_DP_DBGINT_SIGNALBLK2_CONFIG4 0x022C
#define USB3_DP_DBGINT_SIGNALBLK2_CONFIG5 0x0230
#define USB3_DP_DBGINT_STRINGBLK1_CONFIG1 0x0234
#define USB3_DP_DBGINT_STRINGBLK1_CONFIG2 0x0238
#define USB3_DP_DBGINT_STRINGBLK1_CONFIG3 0x023C
#define USB3_DP_DBGINT_STRINGBLK1_CONFIG4 0x0240
#define USB3_DP_DBGINT_STRINGBLK1_CONFIG5 0x0244
#define USB3_DP_DBGINT_STRINGBLK2_CONFIG1 0x0248
#define USB3_DP_DBGINT_STRINGBLK2_CONFIG2 0x024C
#define USB3_DP_DBGINT_STRINGBLK2_CONFIG3 0x0250
#define USB3_DP_DBGINT_STRINGBLK2_CONFIG4 0x0254
#define USB3_DP_DBGINT_STRINGBLK2_CONFIG5 0x0258
/* Module: USB3_DP_PHY_USB3_QSERDES_COM_USB3_QSERDES_COM_USB3_DP_QMP_PLL */
#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0x1000
#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x1004
#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE1 0x1008
#define USB3_DP_QSERDES_COM_CLK_EP_DIV_MODE1 0x100C
#define USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x1010
#define USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x1014
#define USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x1018
#define USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x101C
#define USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x1020
#define USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x1024
#define USB3_DP_QSERDES_COM_DEC_START_MODE1 0x1028
#define USB3_DP_QSERDES_COM_DEC_START_MSB_MODE1 0x102C
#define USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0x1030
#define USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0x1034
#define USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x1038
#define USB3_DP_QSERDES_COM_HSCLK_SEL_1 0x103C
#define USB3_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x1040
#define USB3_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x1044
#define USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x1048
#define USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x104C
#define USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1050
#define USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1054
#define USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1058
#define USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x105C
#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0x1060
#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x1064
#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE0 0x1068
#define USB3_DP_QSERDES_COM_CLK_EP_DIV_MODE0 0x106C
#define USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x1070
#define USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x1074
#define USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x1078
#define USB3_DP_QSERDES_COM_CORECLK_DIV_MODE0 0x107C
#define USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x1080
#define USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x1084
#define USB3_DP_QSERDES_COM_DEC_START_MODE0 0x1088
#define USB3_DP_QSERDES_COM_DEC_START_MSB_MODE0 0x108C
#define USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0x1090
#define USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0x1094
#define USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x1098
#define USB3_DP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_1 0x109C
#define USB3_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x10A0
#define USB3_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10A4
#define USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x10A8
#define USB3_DP_QSERDES_COM_VCO_TUNE2_MODE0 0x10AC
#define USB3_DP_QSERDES_COM_ATB_SEL1 0x10B0
#define USB3_DP_QSERDES_COM_ATB_SEL2 0x10B4
#define USB3_DP_QSERDES_COM_FREQ_UPDATE 0x10B8
#define USB3_DP_QSERDES_COM_BG_TIMER 0x10BC
#define USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x10C0
#define USB3_DP_QSERDES_COM_SSC_ADJ_PER1 0x10C4
#define USB3_DP_QSERDES_COM_SSC_ADJ_PER2 0x10C8
#define USB3_DP_QSERDES_COM_SSC_PER1 0x10CC
#define USB3_DP_QSERDES_COM_SSC_PER2 0x10D0
#define USB3_DP_QSERDES_COM_POST_DIV 0x10D4
#define USB3_DP_QSERDES_COM_POST_DIV_MUX 0x10D8
#define USB3_DP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x10DC
#define USB3_DP_QSERDES_COM_CLK_ENABLE1 0x10E0
#define USB3_DP_QSERDES_COM_SYS_CLK_CTRL 0x10E4
#define USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x10E8
#define USB3_DP_QSERDES_COM_PLL_EN 0x10EC
#define USB3_DP_QSERDES_COM_DEBUG_BUS_OVRD 0x10F0
#define USB3_DP_QSERDES_COM_PLL_IVCO 0x10F4
#define USB3_DP_QSERDES_COM_PLL_IVCO_MODE1 0x10F8
#define USB3_DP_QSERDES_COM_CMN_IETRIM 0x10FC
#define USB3_DP_QSERDES_COM_CMN_IPTRIM 0x1100
#define USB3_DP_QSERDES_COM_EP_CLOCK_DETECT_CTRL 0x1104
#define USB3_DP_QSERDES_COM_PLL_CNTRL 0x1108
#define USB3_DP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x110C
#define USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1110
#define USB3_DP_QSERDES_COM_CML_SYSCLK_SEL 0x1114
#define USB3_DP_QSERDES_COM_RESETSM_CNTRL 0x1118
#define USB3_DP_QSERDES_COM_RESETSM_CNTRL2 0x111C
#define USB3_DP_QSERDES_COM_LOCK_CMP_EN 0x1120
#define USB3_DP_QSERDES_COM_LOCK_CMP_CFG 0x1124
#define USB3_DP_QSERDES_COM_INTEGLOOP_INITVAL 0x1128
#define USB3_DP_QSERDES_COM_INTEGLOOP_EN 0x112C
#define USB3_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0 0x1130
#define USB3_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1 0x1134
#define USB3_DP_QSERDES_COM_VCOCAL_DEADMAN_CTRL 0x1138
#define USB3_DP_QSERDES_COM_VCO_TUNE_CTRL 0x113C
#define USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x1140
#define USB3_DP_QSERDES_COM_VCO_TUNE_INITVAL1 0x1144
#define USB3_DP_QSERDES_COM_VCO_TUNE_INITVAL2 0x1148
#define USB3_DP_QSERDES_COM_VCO_TUNE_MINVAL1 0x114C
#define USB3_DP_QSERDES_COM_VCO_TUNE_MINVAL2 0x1150
#define USB3_DP_QSERDES_COM_VCO_TUNE_MAXVAL1 0x1154
#define USB3_DP_QSERDES_COM_VCO_TUNE_MAXVAL2 0x1158
#define USB3_DP_QSERDES_COM_VCO_TUNE_TIMER1 0x115C
#define USB3_DP_QSERDES_COM_VCO_TUNE_TIMER2 0x1160
#define USB3_DP_QSERDES_COM_CLK_SELECT 0x1164
#define USB3_DP_QSERDES_COM_PLL_ANALOG 0x1168
#define USB3_DP_QSERDES_COM_SW_RESET 0x116C
#define USB3_DP_QSERDES_COM_CORE_CLK_EN 0x1170
#define USB3_DP_QSERDES_COM_CMN_CONFIG_1 0x1174
#define USB3_DP_QSERDES_COM_CMN_RATE_OVERRIDE 0x1178
#define USB3_DP_QSERDES_COM_SVS_MODE_CLK_SEL 0x117C
#define USB3_DP_QSERDES_COM_DEBUG_BUS_SEL 0x1180
#define USB3_DP_QSERDES_COM_CMN_MISC1 0x1184
#define USB3_DP_QSERDES_COM_CMN_MODE 0x1188
#define USB3_DP_QSERDES_COM_CMN_MODE_CONTD 0x118C
#define USB3_DP_QSERDES_COM_CMN_MODE_CONTD1 0x1190
#define USB3_DP_QSERDES_COM_CMN_MODE_CONTD2 0x1194
#define USB3_DP_QSERDES_COM_VCO_DC_LEVEL_CTRL 0x1198
#define USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_1 0x119C
#define USB3_DP_QSERDES_COM_ADDITIONAL_CTRL_1 0x11A0
#define USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_1 0x11A4
#define USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_2 0x11A8
#define USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_3 0x11AC
#define USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_4 0x11B0
#define USB3_DP_QSERDES_COM_ADDITIONAL_MISC 0x11B4
#define USB3_DP_QSERDES_COM_ADDITIONAL_MISC_2 0x11B8
#define USB3_DP_QSERDES_COM_ADDITIONAL_MISC_3 0x11BC
#define USB3_DP_QSERDES_COM_ADDITIONAL_MISC_4 0x11C0
#define USB3_DP_QSERDES_COM_ADDITIONAL_MISC_5 0x11C4
#define USB3_DP_QSERDES_COM_MODE_OPERATION_STATUS 0x11C8
#define USB3_DP_QSERDES_COM_SYSCLK_DET_COMP_STATUS 0x11CC
#define USB3_DP_QSERDES_COM_CMN_STATUS 0x11D0
#define USB3_DP_QSERDES_COM_RESET_SM_STATUS 0x11D4
#define USB3_DP_QSERDES_COM_RESTRIM_CODE_STATUS 0x11D8
#define USB3_DP_QSERDES_COM_PLLCAL_CODE1_STATUS 0x11DC
#define USB3_DP_QSERDES_COM_PLLCAL_CODE2_STATUS 0x11E0
#define USB3_DP_QSERDES_COM_INTEGLOOP_BINCODE_STATUS 0x11E4
#define USB3_DP_QSERDES_COM_DEBUG_BUS0 0x11E8
#define USB3_DP_QSERDES_COM_DEBUG_BUS1 0x11EC
#define USB3_DP_QSERDES_COM_DEBUG_BUS2 0x11F0
#define USB3_DP_QSERDES_COM_DEBUG_BUS3 0x11F4
#define USB3_DP_QSERDES_COM_C_READY_STATUS 0x11F8
#define USB3_DP_QSERDES_COM_READ_DUMMY_1 0x11FC
/* Module: USB3_DP_PHY_USB3_QSERDES_TXA_USB3_QSERDES_TXA_USB3_DP_QMP_TX */
#define USB3_DP_QSERDES_TXA_BIST_MODE_LANENO 0x1200
#define USB3_DP_QSERDES_TXA_BIST_INVERT 0x1204
#define USB3_DP_QSERDES_TXA_CLKBUF_ENABLE 0x1208
#define USB3_DP_QSERDES_TXA_TX_EMP_POST1_LVL 0x120C
#define USB3_DP_QSERDES_TXA_TX_IDLE_LVL_LARGE_AMP 0x1210
#define USB3_DP_QSERDES_TXA_TX_DRV_LVL 0x1214
#define USB3_DP_QSERDES_TXA_TX_DRV_LVL_OFFSET 0x1218
#define USB3_DP_QSERDES_TXA_RESET_TSYNC_EN 0x121C
#define USB3_DP_QSERDES_TXA_PRE_STALL_LDO_BOOST_EN 0x1220
#define USB3_DP_QSERDES_TXA_TX_BAND 0x1224
#define USB3_DP_QSERDES_TXA_SLEW_CNTL 0x1228
#define USB3_DP_QSERDES_TXA_INTERFACE_SELECT 0x122C
#define USB3_DP_QSERDES_TXA_LPB_EN 0x1230
#define USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x1234
#define USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x1238
#define USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x123C
#define USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x1240
#define USB3_DP_QSERDES_TXA_PERL_LENGTH1 0x1244
#define USB3_DP_QSERDES_TXA_PERL_LENGTH2 0x1248
#define USB3_DP_QSERDES_TXA_SERDES_BYP_EN_OUT 0x124C
#define USB3_DP_QSERDES_TXA_DEBUG_BUS_SEL 0x1250
#define USB3_DP_QSERDES_TXA_TRANSCEIVER_BIAS_EN 0x1254
#define USB3_DP_QSERDES_TXA_HIGHZ_DRVR_EN 0x1258
#define USB3_DP_QSERDES_TXA_TX_POL_INV 0x125C
#define USB3_DP_QSERDES_TXA_PARRATE_REC_DETECT_IDLE_EN 0x1260
#define USB3_DP_QSERDES_TXA_BIST_PATTERN1 0x1264
#define USB3_DP_QSERDES_TXA_BIST_PATTERN2 0x1268
#define USB3_DP_QSERDES_TXA_BIST_PATTERN3 0x126C
#define USB3_DP_QSERDES_TXA_BIST_PATTERN4 0x1270
#define USB3_DP_QSERDES_TXA_BIST_PATTERN5 0x1274
#define USB3_DP_QSERDES_TXA_BIST_PATTERN6 0x1278
#define USB3_DP_QSERDES_TXA_BIST_PATTERN7 0x127C
#define USB3_DP_QSERDES_TXA_BIST_PATTERN8 0x1280
#define USB3_DP_QSERDES_TXA_LANE_MODE_1 0x1284
#define USB3_DP_QSERDES_TXA_LANE_MODE_2 0x1288
#define USB3_DP_QSERDES_TXA_LANE_MODE_3 0x128C
#define USB3_DP_QSERDES_TXA_LANE_MODE_4 0x1290
#define USB3_DP_QSERDES_TXA_LANE_MODE_5 0x1294
#define USB3_DP_QSERDES_TXA_ATB_SEL1 0x1298
#define USB3_DP_QSERDES_TXA_ATB_SEL2 0x129C
#define USB3_DP_QSERDES_TXA_RCV_DETECT_LVL 0x12A0
#define USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12A4
#define USB3_DP_QSERDES_TXA_PRBS_SEED1 0x12A8
#define USB3_DP_QSERDES_TXA_PRBS_SEED2 0x12AC
#define USB3_DP_QSERDES_TXA_PRBS_SEED3 0x12B0
#define USB3_DP_QSERDES_TXA_PRBS_SEED4 0x12B4
#define USB3_DP_QSERDES_TXA_RESET_GEN 0x12B8
#define USB3_DP_QSERDES_TXA_RESET_GEN_MUXES 0x12BC
#define USB3_DP_QSERDES_TXA_TRAN_DRVR_EMP_EN 0x12C0
#define USB3_DP_QSERDES_TXA_TX_INTERFACE_MODE 0x12C4
#define USB3_DP_QSERDES_TXA_VMODE_CTRL1 0x12C8
#define USB3_DP_QSERDES_TXA_ALOG_OBSV_BUS_CTRL_1 0x12CC
#define USB3_DP_QSERDES_TXA_BIST_STATUS 0x12D0
#define USB3_DP_QSERDES_TXA_BIST_ERROR_COUNT1 0x12D4
#define USB3_DP_QSERDES_TXA_BIST_ERROR_COUNT2 0x12D8
#define USB3_DP_QSERDES_TXA_ALOG_OBSV_BUS_STATUS_1 0x12DC
#define USB3_DP_QSERDES_TXA_LANE_DIG_CONFIG 0x12E0
#define USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x12E4
#define USB3_DP_QSERDES_TXA_PRE_EMPH 0x12E8
#define USB3_DP_QSERDES_TXA_SW_RESET 0x12EC
#define USB3_DP_QSERDES_TXA_DCC_OFFSET 0x12F0
#define USB3_DP_QSERDES_TXA_DCC_CMUX_POSTCAL_OFFSET 0x12F4
#define USB3_DP_QSERDES_TXA_DCC_CMUX_CAL_CTRL1 0x12F8
#define USB3_DP_QSERDES_TXA_DCC_CMUX_CAL_CTRL2 0x12FC
#define USB3_DP_QSERDES_TXA_DIG_BKUP_CTRL 0x1300
#define USB3_DP_QSERDES_TXA_DEBUG_BUS0 0x1304
#define USB3_DP_QSERDES_TXA_DEBUG_BUS1 0x1308
#define USB3_DP_QSERDES_TXA_DEBUG_BUS2 0x130C
#define USB3_DP_QSERDES_TXA_DEBUG_BUS3 0x1310
#define USB3_DP_QSERDES_TXA_READ_EQCODE 0x1314
#define USB3_DP_QSERDES_TXA_READ_OFFSETCODE 0x1318
#define USB3_DP_QSERDES_TXA_IA_ERROR_COUNTER_LOW 0x131C
#define USB3_DP_QSERDES_TXA_IA_ERROR_COUNTER_HIGH 0x1320
#define USB3_DP_QSERDES_TXA_VGA_READ_CODE 0x1324
#define USB3_DP_QSERDES_TXA_VTH_READ_CODE 0x1328
#define USB3_DP_QSERDES_TXA_DFE_TAP1_READ_CODE 0x132C
#define USB3_DP_QSERDES_TXA_DFE_TAP2_READ_CODE 0x1330
#define USB3_DP_QSERDES_TXA_IDAC_STATUS_I 0x1334
#define USB3_DP_QSERDES_TXA_IDAC_STATUS_IBAR 0x1338
#define USB3_DP_QSERDES_TXA_IDAC_STATUS_Q 0x133C
#define USB3_DP_QSERDES_TXA_IDAC_STATUS_QBAR 0x1340
#define USB3_DP_QSERDES_TXA_IDAC_STATUS_A 0x1344
#define USB3_DP_QSERDES_TXA_IDAC_STATUS_ABAR 0x1348
#define USB3_DP_QSERDES_TXA_IDAC_STATUS_SM_ON 0x134C
#define USB3_DP_QSERDES_TXA_IDAC_STATUS_CAL_DONE 0x1350
#define USB3_DP_QSERDES_TXA_IDAC_STATUS_SIGNERROR 0x1354
#define USB3_DP_QSERDES_TXA_DCC_CAL_STATUS 0x1358
#define USB3_DP_QSERDES_TXA_DCC_READ_CODE_STATUS 0x135C
#define USB3_DP_QSERDES_TXA_SIGDET_CAL_ENGINE_STATUS 0x1360
#define USB3_DP_QSERDES_TXA_AC_JTAG_OUTP_OUTN_STATUS 0x1364
/* Module: USB3_DP_PHY_USB3_QSERDES_RXA_USB3_QSERDES_RXA_USB3_DP_QMP_RX */
#define USB3_DP_QSERDES_RXA_UCDR_FO_GAIN_HALF 0x1400
#define USB3_DP_QSERDES_RXA_UCDR_FO_GAIN_QUARTER 0x1404
#define USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x1408
#define USB3_DP_QSERDES_RXA_UCDR_SO_GAIN_HALF 0x140C
#define USB3_DP_QSERDES_RXA_UCDR_SO_GAIN_QUARTER 0x1410
#define USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x1414
#define USB3_DP_QSERDES_RXA_UCDR_SVS_FO_GAIN_HALF 0x1418
#define USB3_DP_QSERDES_RXA_UCDR_SVS_FO_GAIN_QUARTER 0x141C
#define USB3_DP_QSERDES_RXA_UCDR_SVS_FO_GAIN 0x1420
#define USB3_DP_QSERDES_RXA_UCDR_SVS_SO_GAIN_HALF 0x1424
#define USB3_DP_QSERDES_RXA_UCDR_SVS_SO_GAIN_QUARTER 0x1428
#define USB3_DP_QSERDES_RXA_UCDR_SVS_SO_GAIN 0x142C
#define USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x1430
#define USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x1434
#define USB3_DP_QSERDES_RXA_UCDR_FO_TO_SO_DELAY 0x1438
#define USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0x143C
#define USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x1440
#define USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x1444
#define USB3_DP_QSERDES_RXA_UCDR_PI_CTRL2 0x1448
#define USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x144C
#define USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x1450
#define USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x1454
#define USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x1458
#define USB3_DP_QSERDES_RXA_AUX_CONTROL 0x145C
#define USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0x1460
#define USB3_DP_QSERDES_RXA_RCLK_AUXDATA_SEL 0x1464
#define USB3_DP_QSERDES_RXA_AC_JTAG_ENABLE 0x1468
#define USB3_DP_QSERDES_RXA_AC_JTAG_INITP 0x146C
#define USB3_DP_QSERDES_RXA_AC_JTAG_INITN 0x1470
#define USB3_DP_QSERDES_RXA_AC_JTAG_LVL 0x1474
#define USB3_DP_QSERDES_RXA_AC_JTAG_MODE 0x1478
#define USB3_DP_QSERDES_RXA_AC_JTAG_RESET 0x147C
#define USB3_DP_QSERDES_RXA_RX_TERM_BW 0x1480
#define USB3_DP_QSERDES_RXA_RX_RCVR_IQ_EN 0x1484
#define USB3_DP_QSERDES_RXA_RX_IDAC_I_DC_OFFSETS 0x1488
#define USB3_DP_QSERDES_RXA_RX_IDAC_IBAR_DC_OFFSETS 0x148C
#define USB3_DP_QSERDES_RXA_RX_IDAC_Q_DC_OFFSETS 0x1490
#define USB3_DP_QSERDES_RXA_RX_IDAC_QBAR_DC_OFFSETS 0x1494
#define USB3_DP_QSERDES_RXA_RX_IDAC_A_DC_OFFSETS 0x1498
#define USB3_DP_QSERDES_RXA_RX_IDAC_ABAR_DC_OFFSETS 0x149C
#define USB3_DP_QSERDES_RXA_RX_IDAC_EN 0x14A0
#define USB3_DP_QSERDES_RXA_RX_IDAC_ENABLES 0x14A4
#define USB3_DP_QSERDES_RXA_RX_IDAC_SIGN 0x14A8
#define USB3_DP_QSERDES_RXA_RX_HIGHZ_HIGHRATE 0x14AC
#define USB3_DP_QSERDES_RXA_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x14B0
#define USB3_DP_QSERDES_RXA_DFE_1 0x14B4
#define USB3_DP_QSERDES_RXA_DFE_2 0x14B8
#define USB3_DP_QSERDES_RXA_DFE_3 0x14BC
#define USB3_DP_QSERDES_RXA_DFE_4 0x14C0
#define USB3_DP_QSERDES_RXA_TX_ADAPT_PRE_THRESH1 0x14C4
#define USB3_DP_QSERDES_RXA_TX_ADAPT_PRE_THRESH2 0x14C8
#define USB3_DP_QSERDES_RXA_TX_ADAPT_POST_THRESH 0x14CC
#define USB3_DP_QSERDES_RXA_TX_ADAPT_MAIN_THRESH 0x14D0
#define USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x14D4
#define USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x14D8
#define USB3_DP_QSERDES_RXA_GM_CAL 0x14DC
#define USB3_DP_QSERDES_RXA_RX_VGA_GAIN2_LSB 0x14E0
#define USB3_DP_QSERDES_RXA_RX_VGA_GAIN2_MSB 0x14E4
#define USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL1 0x14E8
#define USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x14EC
#define USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x14F0
#define USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x14F4
#define USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0x14F8
#define USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x14FC
#define USB3_DP_QSERDES_RXA_RX_IDAC_MEASURE_TIME 0x1500
#define USB3_DP_QSERDES_RXA_RX_IDAC_ACCUMULATOR 0x1504
#define USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_LSB 0x1508
#define USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_MSB 0x150C
#define USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1510
#define USB3_DP_QSERDES_RXA_RX_OFFSET_ADAPTOR_CNTRL2 0x1514
#define USB3_DP_QSERDES_RXA_SIGDET_ENABLES 0x1518
#define USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x151C
#define USB3_DP_QSERDES_RXA_SIGDET_LVL 0x1520
#define USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x1524
#define USB3_DP_QSERDES_RXA_RX_BAND 0x1528
#define USB3_DP_QSERDES_RXA_CDR_FREEZE_UP_DN 0x152C
#define USB3_DP_QSERDES_RXA_CDR_RESET_OVERRIDE 0x1530
#define USB3_DP_QSERDES_RXA_RX_INTERFACE_MODE 0x1534
#define USB3_DP_QSERDES_RXA_JITTER_GEN_MODE 0x1538
#define USB3_DP_QSERDES_RXA_SJ_AMP1 0x153C
#define USB3_DP_QSERDES_RXA_SJ_AMP2 0x1540
#define USB3_DP_QSERDES_RXA_SJ_PER1 0x1544
#define USB3_DP_QSERDES_RXA_SJ_PER2 0x1548
#define USB3_DP_QSERDES_RXA_PPM_OFFSET1 0x154C
#define USB3_DP_QSERDES_RXA_PPM_OFFSET2 0x1550
#define USB3_DP_QSERDES_RXA_SIGN_PPM_PERIOD1 0x1554
#define USB3_DP_QSERDES_RXA_SIGN_PPM_PERIOD2 0x1558
#define USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0x155C
#define USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x1560
#define USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0x1564
#define USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x1568
#define USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0x156C
#define USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0x1570
#define USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0x1574
#define USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0x1578
#define USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x157C
#define USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0x1580
#define USB3_DP_QSERDES_RXA_RX_MODE_10_LOW 0x1584
#define USB3_DP_QSERDES_RXA_RX_MODE_10_HIGH 0x1588
#define USB3_DP_QSERDES_RXA_RX_MODE_10_HIGH2 0x158C
#define USB3_DP_QSERDES_RXA_RX_MODE_10_HIGH3 0x1590
#define USB3_DP_QSERDES_RXA_RX_MODE_10_HIGH4 0x1594
#define USB3_DP_QSERDES_RXA_PHPRE_CTRL 0x1598
#define USB3_DP_QSERDES_RXA_PHPRE_INITVAL 0x159C
#define USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x15A0
#define USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x15A4
#define USB3_DP_QSERDES_RXA_DCC_CTRL1 0x15A8
#define USB3_DP_QSERDES_RXA_DCC_CTRL2 0x15AC
#define USB3_DP_QSERDES_RXA_VTH_CODE 0x15B0
#define USB3_DP_QSERDES_RXA_VTH_MIN_THRESH 0x15B4
#define USB3_DP_QSERDES_RXA_VTH_MAX_THRESH 0x15B8
#define USB3_DP_QSERDES_RXA_ALOG_OBSV_BUS_CTRL_1 0x15BC
#define USB3_DP_QSERDES_RXA_PI_CTRL1 0x15C0
#define USB3_DP_QSERDES_RXA_PI_CTRL2 0x15C4
#define USB3_DP_QSERDES_RXA_PI_QUAD 0x15C8
#define USB3_DP_QSERDES_RXA_IDATA1 0x15CC
#define USB3_DP_QSERDES_RXA_IDATA2 0x15D0
#define USB3_DP_QSERDES_RXA_AUX_DATA1 0x15D4
#define USB3_DP_QSERDES_RXA_AUX_DATA2 0x15D8
#define USB3_DP_QSERDES_RXA_RX_SIGDET_AND_CDR_FALSE_LOCK_STATUS 0x15DC
#define USB3_DP_QSERDES_RXA_ALOG_OBSV_BUS_STATUS_1 0x15E0
#define USB3_DP_QSERDES_RXA_SIGDET_CAL_CTRL1 0x15E4
#define USB3_DP_QSERDES_RXA_SIGDET_CAL_CTRL2_AND_CDR_LOCK_EDGE 0x15E8
#define USB3_DP_QSERDES_RXA_CDR_LOCK_ON_EDGE_DURATION 0x15EC
#define USB3_DP_QSERDES_RXA_CDR_LOCK_ON_EDGE_THRESH 0x15F0
#define USB3_DP_QSERDES_QSERDES_RXA_RX_ADAPTOR_CNTRL 0x15F4
#define USB3_DP_QSERDES_RXA_SIGDET_CAL_TRIM 0x15F8
#define USB3_DP_QSERDES_RXA_CAL_POST_WRAP 0x15FC
/* Module: USB3_DP_PHY_USB3_QSERDES_TXB_USB3_QSERDES_TXB_USB3_DP_QMP_TX */
#define USB3_DP_QSERDES_TXB_BIST_MODE_LANENO 0x1600
#define USB3_DP_QSERDES_TXB_BIST_INVERT 0x1604
#define USB3_DP_QSERDES_TXB_CLKBUF_ENABLE 0x1608
#define USB3_DP_QSERDES_TXB_TX_EMP_POST1_LVL 0x160C
#define USB3_DP_QSERDES_TXB_TX_IDLE_LVL_LARGE_AMP 0x1610
#define USB3_DP_QSERDES_TXB_TX_DRV_LVL 0x1614
#define USB3_DP_QSERDES_TXB_TX_DRV_LVL_OFFSET 0x1618
#define USB3_DP_QSERDES_TXB_RESET_TSYNC_EN 0x161C
#define USB3_DP_QSERDES_TXB_PRE_STALL_LDO_BOOST_EN 0x1620
#define USB3_DP_QSERDES_TXB_TX_BAND 0x1624
#define USB3_DP_QSERDES_TXB_SLEW_CNTL 0x1628
#define USB3_DP_QSERDES_TXB_INTERFACE_SELECT 0x162C
#define USB3_DP_QSERDES_TXB_LPB_EN 0x1630
#define USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x1634
#define USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x1638
#define USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x163C
#define USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x1640
#define USB3_DP_QSERDES_TXB_PERL_LENGTH1 0x1644
#define USB3_DP_QSERDES_TXB_PERL_LENGTH2 0x1648
#define USB3_DP_QSERDES_TXB_SERDES_BYP_EN_OUT 0x164C
#define USB3_DP_QSERDES_TXB_DEBUG_BUS_SEL 0x1650
#define USB3_DP_QSERDES_TXB_TRANSCEIVER_BIAS_EN 0x1654
#define USB3_DP_QSERDES_TXB_HIGHZ_DRVR_EN 0x1658
#define USB3_DP_QSERDES_TXB_TX_POL_INV 0x165C
#define USB3_DP_QSERDES_TXB_PARRATE_REC_DETECT_IDLE_EN 0x1660
#define USB3_DP_QSERDES_TXB_BIST_PATTERN1 0x1664
#define USB3_DP_QSERDES_TXB_BIST_PATTERN2 0x1668
#define USB3_DP_QSERDES_TXB_BIST_PATTERN3 0x166C
#define USB3_DP_QSERDES_TXB_BIST_PATTERN4 0x1670
#define USB3_DP_QSERDES_TXB_BIST_PATTERN5 0x1674
#define USB3_DP_QSERDES_TXB_BIST_PATTERN6 0x1678
#define USB3_DP_QSERDES_TXB_BIST_PATTERN7 0x167C
#define USB3_DP_QSERDES_TXB_BIST_PATTERN8 0x1680
#define USB3_DP_QSERDES_TXB_LANE_MODE_1 0x1684
#define USB3_DP_QSERDES_TXB_LANE_MODE_2 0x1688
#define USB3_DP_QSERDES_TXB_LANE_MODE_3 0x168C
#define USB3_DP_QSERDES_TXB_LANE_MODE_4 0x1690
#define USB3_DP_QSERDES_TXB_LANE_MODE_5 0x1694
#define USB3_DP_QSERDES_TXB_ATB_SEL1 0x1698
#define USB3_DP_QSERDES_TXB_ATB_SEL2 0x169C
#define USB3_DP_QSERDES_TXB_RCV_DETECT_LVL 0x16A0
#define USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x16A4
#define USB3_DP_QSERDES_TXB_PRBS_SEED1 0x16A8
#define USB3_DP_QSERDES_TXB_PRBS_SEED2 0x16AC
#define USB3_DP_QSERDES_TXB_PRBS_SEED3 0x16B0
#define USB3_DP_QSERDES_TXB_PRBS_SEED4 0x16B4
#define USB3_DP_QSERDES_TXB_RESET_GEN 0x16B8
#define USB3_DP_QSERDES_TXB_RESET_GEN_MUXES 0x16BC
#define USB3_DP_QSERDES_TXB_TRAN_DRVR_EMP_EN 0x16C0
#define USB3_DP_QSERDES_TXB_TX_INTERFACE_MODE 0x16C4
#define USB3_DP_QSERDES_TXB_VMODE_CTRL1 0x16C8
#define USB3_DP_QSERDES_TXB_ALOG_OBSV_BUS_CTRL_1 0x16CC
#define USB3_DP_QSERDES_TXB_BIST_STATUS 0x16D0
#define USB3_DP_QSERDES_TXB_BIST_ERROR_COUNT1 0x16D4
#define USB3_DP_QSERDES_TXB_BIST_ERROR_COUNT2 0x16D8
#define USB3_DP_QSERDES_TXB_ALOG_OBSV_BUS_STATUS_1 0x16DC
#define USB3_DP_QSERDES_TXB_LANE_DIG_CONFIG 0x16E0
#define USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x16E4
#define USB3_DP_QSERDES_TXB_PRE_EMPH 0x16E8
#define USB3_DP_QSERDES_TXB_SW_RESET 0x16EC
#define USB3_DP_QSERDES_TXB_DCC_OFFSET 0x16F0
#define USB3_DP_QSERDES_TXB_DCC_CMUX_POSTCAL_OFFSET 0x16F4
#define USB3_DP_QSERDES_TXB_DCC_CMUX_CAL_CTRL1 0x16F8
#define USB3_DP_QSERDES_TXB_DCC_CMUX_CAL_CTRL2 0x16FC
#define USB3_DP_QSERDES_TXB_DIG_BKUP_CTRL 0x1700
#define USB3_DP_QSERDES_TXB_DEBUG_BUS0 0x1704
#define USB3_DP_QSERDES_TXB_DEBUG_BUS1 0x1708
#define USB3_DP_QSERDES_TXB_DEBUG_BUS2 0x170C
#define USB3_DP_QSERDES_TXB_DEBUG_BUS3 0x1710
#define USB3_DP_QSERDES_TXB_READ_EQCODE 0x1714
#define USB3_DP_QSERDES_TXB_READ_OFFSETCODE 0x1718
#define USB3_DP_QSERDES_TXB_IA_ERROR_COUNTER_LOW 0x171C
#define USB3_DP_QSERDES_TXB_IA_ERROR_COUNTER_HIGH 0x1720
#define USB3_DP_QSERDES_TXB_VGA_READ_CODE 0x1724
#define USB3_DP_QSERDES_TXB_VTH_READ_CODE 0x1728
#define USB3_DP_QSERDES_TXB_DFE_TAP1_READ_CODE 0x172C
#define USB3_DP_QSERDES_TXB_DFE_TAP2_READ_CODE 0x1730
#define USB3_DP_QSERDES_TXB_IDAC_STATUS_I 0x1734
#define USB3_DP_QSERDES_TXB_IDAC_STATUS_IBAR 0x1738
#define USB3_DP_QSERDES_TXB_IDAC_STATUS_Q 0x173C
#define USB3_DP_QSERDES_TXB_IDAC_STATUS_QBAR 0x1740
#define USB3_DP_QSERDES_TXB_IDAC_STATUS_A 0x1744
#define USB3_DP_QSERDES_TXB_IDAC_STATUS_ABAR 0x1748
#define USB3_DP_QSERDES_TXB_IDAC_STATUS_SM_ON 0x174C
#define USB3_DP_QSERDES_TXB_IDAC_STATUS_CAL_DONE 0x1750
#define USB3_DP_QSERDES_TXB_IDAC_STATUS_SIGNERROR 0x1754
#define USB3_DP_QSERDES_TXB_DCC_CAL_STATUS 0x1758
#define USB3_DP_QSERDES_TXB_DCC_READ_CODE_STATUS 0x175C
#define USB3_DP_QSERDES_TXB_SIGDET_CAL_ENGINE_STATUS 0x1760
#define USB3_DP_QSERDES_TXB_AC_JTAG_OUTP_OUTN_STATUS 0x1764
/* Module: USB3_DP_PHY_USB3_QSERDES_RXB_USB3_QSERDES_RXB_USB3_DP_QMP_RX */
#define USB3_DP_QSERDES_RXB_UCDR_FO_GAIN_HALF 0x1800
#define USB3_DP_QSERDES_RXB_UCDR_FO_GAIN_QUARTER 0x1804
#define USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x1808
#define USB3_DP_QSERDES_RXB_UCDR_SO_GAIN_HALF 0x180C
#define USB3_DP_QSERDES_RXB_UCDR_SO_GAIN_QUARTER 0x1810
#define USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x1814
#define USB3_DP_QSERDES_RXB_UCDR_SVS_FO_GAIN_HALF 0x1818
#define USB3_DP_QSERDES_RXB_UCDR_SVS_FO_GAIN_QUARTER 0x181C
#define USB3_DP_QSERDES_RXB_UCDR_SVS_FO_GAIN 0x1820
#define USB3_DP_QSERDES_RXB_UCDR_SVS_SO_GAIN_HALF 0x1824
#define USB3_DP_QSERDES_RXB_UCDR_SVS_SO_GAIN_QUARTER 0x1828
#define USB3_DP_QSERDES_RXB_UCDR_SVS_SO_GAIN 0x182C
#define USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x1830
#define USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x1834
#define USB3_DP_QSERDES_RXB_UCDR_FO_TO_SO_DELAY 0x1838
#define USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0x183C
#define USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x1840
#define USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x1844
#define USB3_DP_QSERDES_RXB_UCDR_PI_CTRL2 0x1848
#define USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x184C
#define USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x1850
#define USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x1854
#define USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x1858
#define USB3_DP_QSERDES_RXB_AUX_CONTROL 0x185C
#define USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0x1860
#define USB3_DP_QSERDES_RXB_RCLK_AUXDATA_SEL 0x1864
#define USB3_DP_QSERDES_RXB_AC_JTAG_ENABLE 0x1868
#define USB3_DP_QSERDES_RXB_AC_JTAG_INITP 0x186C
#define USB3_DP_QSERDES_RXB_AC_JTAG_INITN 0x1870
#define USB3_DP_QSERDES_RXB_AC_JTAG_LVL 0x1874
#define USB3_DP_QSERDES_RXB_AC_JTAG_MODE 0x1878
#define USB3_DP_QSERDES_RXB_AC_JTAG_RESET 0x187C
#define USB3_DP_QSERDES_RXB_RX_TERM_BW 0x1880
#define USB3_DP_QSERDES_RXB_RX_RCVR_IQ_EN 0x1884
#define USB3_DP_QSERDES_RXB_RX_IDAC_I_DC_OFFSETS 0x1888
#define USB3_DP_QSERDES_RXB_RX_IDAC_IBAR_DC_OFFSETS 0x188C
#define USB3_DP_QSERDES_RXB_RX_IDAC_Q_DC_OFFSETS 0x1890
#define USB3_DP_QSERDES_RXB_RX_IDAC_QBAR_DC_OFFSETS 0x1894
#define USB3_DP_QSERDES_RXB_RX_IDAC_A_DC_OFFSETS 0x1898
#define USB3_DP_QSERDES_RXB_RX_IDAC_ABAR_DC_OFFSETS 0x189C
#define USB3_DP_QSERDES_RXB_RX_IDAC_EN 0x18A0
#define USB3_DP_QSERDES_RXB_RX_IDAC_ENABLES 0x18A4
#define USB3_DP_QSERDES_RXB_RX_IDAC_SIGN 0x18A8
#define USB3_DP_QSERDES_RXB_RX_HIGHZ_HIGHRATE 0x18AC
#define USB3_DP_QSERDES_RXB_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x18B0
#define USB3_DP_QSERDES_RXB_DFE_1 0x18B4
#define USB3_DP_QSERDES_RXB_DFE_2 0x18B8
#define USB3_DP_QSERDES_RXB_DFE_3 0x18BC
#define USB3_DP_QSERDES_RXB_DFE_4 0x18C0
#define USB3_DP_QSERDES_RXB_TX_ADAPT_PRE_THRESH1 0x18C4
#define USB3_DP_QSERDES_RXB_TX_ADAPT_PRE_THRESH2 0x18C8
#define USB3_DP_QSERDES_RXB_TX_ADAPT_POST_THRESH 0x18CC
#define USB3_DP_QSERDES_RXB_TX_ADAPT_MAIN_THRESH 0x18D0
#define USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x18D4
#define USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x18D8
#define USB3_DP_QSERDES_RXB_GM_CAL 0x18DC
#define USB3_DP_QSERDES_RXB_RX_VGA_GAIN2_LSB 0x18E0
#define USB3_DP_QSERDES_RXB_RX_VGA_GAIN2_MSB 0x18E4
#define USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL1 0x18E8
#define USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x18EC
#define USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x18F0
#define USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x18F4
#define USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0x18F8
#define USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x18FC
#define USB3_DP_QSERDES_RXB_RX_IDAC_MEASURE_TIME 0x1900
#define USB3_DP_QSERDES_RXB_RX_IDAC_ACCUMULATOR 0x1904
#define USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_LSB 0x1908
#define USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_MSB 0x190C
#define USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1910
#define USB3_DP_QSERDES_RXB_RX_OFFSET_ADAPTOR_CNTRL2 0x1914
#define USB3_DP_QSERDES_RXB_SIGDET_ENABLES 0x1918
#define USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x191C
#define USB3_DP_QSERDES_RXB_SIGDET_LVL 0x1920
#define USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x1924
#define USB3_DP_QSERDES_RXB_RX_BAND 0x1928
#define USB3_DP_QSERDES_RXB_CDR_FREEZE_UP_DN 0x192C
#define USB3_DP_QSERDES_RXB_CDR_RESET_OVERRIDE 0x1930
#define USB3_DP_QSERDES_RXB_RX_INTERFACE_MODE 0x1934
#define USB3_DP_QSERDES_RXB_JITTER_GEN_MODE 0x1938
#define USB3_DP_QSERDES_RXB_SJ_AMP1 0x193C
#define USB3_DP_QSERDES_RXB_SJ_AMP2 0x1940
#define USB3_DP_QSERDES_RXB_SJ_PER1 0x1944
#define USB3_DP_QSERDES_RXB_SJ_PER2 0x1948
#define USB3_DP_QSERDES_RXB_PPM_OFFSET1 0x194C
#define USB3_DP_QSERDES_RXB_PPM_OFFSET2 0x1950
#define USB3_DP_QSERDES_RXB_SIGN_PPM_PERIOD1 0x1954
#define USB3_DP_QSERDES_RXB_SIGN_PPM_PERIOD2 0x1958
#define USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0x195C
#define USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0x1960
#define USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0x1964
#define USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x1968
#define USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0x196C
#define USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0x1970
#define USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0x1974
#define USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0x1978
#define USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x197C
#define USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0x1980
#define USB3_DP_QSERDES_RXB_RX_MODE_10_LOW 0x1984
#define USB3_DP_QSERDES_RXB_RX_MODE_10_HIGH 0x1988
#define USB3_DP_QSERDES_RXB_RX_MODE_10_HIGH2 0x198C
#define USB3_DP_QSERDES_RXB_RX_MODE_10_HIGH3 0x1990
#define USB3_DP_QSERDES_RXB_RX_MODE_10_HIGH4 0x1994
#define USB3_DP_QSERDES_RXB_PHPRE_CTRL 0x1998
#define USB3_DP_QSERDES_RXB_PHPRE_INITVAL 0x199C
#define USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x19A0
#define USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x19A4
#define USB3_DP_QSERDES_RXB_DCC_CTRL1 0x19A8
#define USB3_DP_QSERDES_RXB_DCC_CTRL2 0x19AC
#define USB3_DP_QSERDES_RXB_VTH_CODE 0x19B0
#define USB3_DP_QSERDES_RXB_VTH_MIN_THRESH 0x19B4
#define USB3_DP_QSERDES_RXB_VTH_MAX_THRESH 0x19B8
#define USB3_DP_QSERDES_RXB_ALOG_OBSV_BUS_CTRL_1 0x19BC
#define USB3_DP_QSERDES_RXB_PI_CTRL1 0x19C0
#define USB3_DP_QSERDES_RXB_PI_CTRL2 0x19C4
#define USB3_DP_QSERDES_RXB_PI_QUAD 0x19C8
#define USB3_DP_QSERDES_RXB_IDATA1 0x19CC
#define USB3_DP_QSERDES_RXB_IDATA2 0x19D0
#define USB3_DP_QSERDES_RXB_AUX_DATA1 0x19D4
#define USB3_DP_QSERDES_RXB_AUX_DATA2 0x19D8
#define USB3_DP_QSERDES_RXB_RX_SIGDET_AND_CDR_FALSE_LOCK_STATUS 0x19DC
#define USB3_DP_QSERDES_RXB_ALOG_OBSV_BUS_STATUS_1 0x19E0
#define USB3_DP_QSERDES_RXB_SIGDET_CAL_CTRL1 0x19E4
#define USB3_DP_QSERDES_RXB_SIGDET_CAL_CTRL2_AND_CDR_LOCK_EDGE 0x19E8
#define USB3_DP_QSERDES_RXB_CDR_LOCK_ON_EDGE_DURATION 0x19EC
#define USB3_DP_QSERDES_RXB_CDR_LOCK_ON_EDGE_THRESH 0x19F0
#define USB3_DP_QSERDES_RXB_RX_ADAPTOR_CNTRL 0x19F4
#define USB3_DP_QSERDES_RXB_SIGDET_CAL_TRIM 0x19F8
#define USB3_DP_QSERDES_RXB_CAL_POST_WRAP 0x19FC
/* Module: USB3_DP_PHY_USB3_PCS_MISC_USB3_PCS_MISC_USB3_PCS_MISC */
#define USB3_DP_PCS_MISC_TYPEC_CTRL 0x1A00
#define USB3_DP_PCS_MISC_TYPEC_PWRDN_CTRL 0x1A04
#define USB3_DP_PCS_MISC_PCS_MISC_CONFIG1 0x1A08
#define USB3_DP_PCS_MISC_CLAMP_ENABLE 0x1A0C
#define USB3_DP_PCS_MISC_TYPEC_STATUS 0x1A10
#define USB3_DP_PCS_MISC_PLACEHOLDER_STATUS 0x1A14
/* Module: USB3_DP_PHY_USB3_PCS_LN_USB3_PCS_LN_USB3_PCS_LANE */
#define USB3_DP_PCS_LN_PCS_STATUS1 0x1B00
#define USB3_DP_PCS_LN_PCS_STATUS2 0x1B04
#define USB3_DP_PCS_LN_PCS_STATUS2_CLEAR 0x1B08
#define USB3_DP_PCS_LN_PCS_STATUS3 0x1B0C
#define USB3_DP_PCS_LN_BIST_CHK_ERR_CNT_L_STATUS 0x1B10
#define USB3_DP_PCS_LN_BIST_CHK_ERR_CNT_H_STATUS 0x1B14
#define USB3_DP_PCS_LN_BIST_CHK_STATUS 0x1B18
#define USB3_DP_PCS_LN_INSIG_SW_CTRL1 0x1B1C
#define USB3_DP_PCS_LN_INSIG_MX_CTRL1 0x1B20
#define USB3_DP_PCS_LN_OUTSIG_SW_CTRL1 0x1B24
#define USB3_DP_PCS_LN_OUTSIG_MX_CTRL1 0x1B28
#define USB3_DP_PCS_LN_TEST_CONTROL1 0x1B2C
#define USB3_DP_PCS_LN_BIST_CTRL 0x1B30
#define USB3_DP_PCS_LN_PRBS_SEED0 0x1B34
#define USB3_DP_PCS_LN_PRBS_SEED1 0x1B38
#define USB3_DP_PCS_LN_FIXED_PAT_CTRL 0x1B3C
#define USB3_DP_PCS_LN_EQ_CONFIG 0x1B40
#define USB3_DP_PCS_LN_TEST_CONTROL2 0x1B44
#define USB3_DP_PCS_LN_TEST_CONTROL3 0x1B48
/* Module: USB3_DP_PHY_USB3_PCS_USB3_PCS_USB3_PCS */
#define USB3_DP_PCS_SW_RESET 0x1C00
#define USB3_DP_PCS_REVISION_ID0 0x1C04
#define USB3_DP_PCS_REVISION_ID1 0x1C08
#define USB3_DP_PCS_REVISION_ID2 0x1C0C
#define USB3_DP_PCS_REVISION_ID3 0x1C10
#define USB3_DP_PCS_PCS_STATUS1 0x1C14
#define USB3_DP_PCS_PCS_STATUS2 0x1C18
#define USB3_DP_PCS_PCS_STATUS3 0x1C1C
#define USB3_DP_PCS_PCS_STATUS4 0x1C20
#define USB3_DP_PCS_PCS_STATUS5 0x1C24
#define USB3_DP_PCS_PCS_STATUS6 0x1C28
#define USB3_DP_PCS_PCS_STATUS7 0x1C2C
#define USB3_DP_PCS_DEBUG_BUS_0_STATUS 0x1C30
#define USB3_DP_PCS_DEBUG_BUS_1_STATUS 0x1C34
#define USB3_DP_PCS_DEBUG_BUS_2_STATUS 0x1C38
#define USB3_DP_PCS_DEBUG_BUS_3_STATUS 0x1C3C
#define USB3_DP_PCS_POWER_DOWN_CONTROL 0x1C40
#define USB3_DP_PCS_START_CONTROL 0x1C44
#define USB3_DP_PCS_INSIG_SW_CTRL1 0x1C48
#define USB3_DP_PCS_INSIG_SW_CTRL2 0x1C4C
#define USB3_DP_PCS_INSIG_SW_CTRL3 0x1C50
#define USB3_DP_PCS_INSIG_SW_CTRL4 0x1C54
#define USB3_DP_PCS_INSIG_SW_CTRL5 0x1C58
#define USB3_DP_PCS_INSIG_SW_CTRL6 0x1C5C
#define USB3_DP_PCS_INSIG_SW_CTRL7 0x1C60
#define USB3_DP_PCS_INSIG_SW_CTRL8 0x1C64
#define USB3_DP_PCS_INSIG_MX_CTRL1 0x1C68
#define USB3_DP_PCS_INSIG_MX_CTRL2 0x1C6C
#define USB3_DP_PCS_INSIG_MX_CTRL3 0x1C70
#define USB3_DP_PCS_INSIG_MX_CTRL4 0x1C74
#define USB3_DP_PCS_INSIG_MX_CTRL5 0x1C78
#define USB3_DP_PCS_INSIG_MX_CTRL7 0x1C7C
#define USB3_DP_PCS_INSIG_MX_CTRL8 0x1C80
#define USB3_DP_PCS_OUTSIG_SW_CTRL1 0x1C84
#define USB3_DP_PCS_OUTSIG_MX_CTRL1 0x1C88
#define USB3_DP_PCS_CLAMP_ENABLE 0x1C8C
#define USB3_DP_PCS_POWER_STATE_CONFIG1 0x1C90
#define USB3_DP_PCS_POWER_STATE_CONFIG2 0x1C94
#define USB3_DP_PCS_FLL_CNTRL1 0x1C98
#define USB3_DP_PCS_FLL_CNTRL2 0x1C9C
#define USB3_DP_PCS_FLL_CNT_VAL_L 0x1CA0
#define USB3_DP_PCS_FLL_CNT_VAL_H_TOL 0x1CA4
#define USB3_DP_PCS_FLL_MAN_CODE 0x1CA8
#define USB3_DP_PCS_TEST_CONTROL1 0x1CAC
#define USB3_DP_PCS_TEST_CONTROL2 0x1CB0
#define USB3_DP_PCS_TEST_CONTROL3 0x1CB4
#define USB3_DP_PCS_TEST_CONTROL4 0x1CB8
#define USB3_DP_PCS_TEST_CONTROL5 0x1CBC
#define USB3_DP_PCS_TEST_CONTROL6 0x1CC0
#define USB3_DP_PCS_LOCK_DETECT_CONFIG1 0x1CC4
#define USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x1CC8
#define USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x1CCC
#define USB3_DP_PCS_LOCK_DETECT_CONFIG4 0x1CD0
#define USB3_DP_PCS_LOCK_DETECT_CONFIG5 0x1CD4
#define USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x1CD8
#define USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x1CDC
#define USB3_DP_PCS_REFGEN_REQ_CONFIG2 0x1CE0
#define USB3_DP_PCS_REFGEN_REQ_CONFIG3 0x1CE4
#define USB3_DP_PCS_BIST_CTRL 0x1CE8
#define USB3_DP_PCS_PRBS_POLY0 0x1CEC
#define USB3_DP_PCS_PRBS_POLY1 0x1CF0
#define USB3_DP_PCS_FIXED_PAT0 0x1CF4
#define USB3_DP_PCS_FIXED_PAT1 0x1CF8
#define USB3_DP_PCS_FIXED_PAT2 0x1CFC
#define USB3_DP_PCS_FIXED_PAT3 0x1D00
#define USB3_DP_PCS_FIXED_PAT4 0x1D04
#define USB3_DP_PCS_FIXED_PAT5 0x1D08
#define USB3_DP_PCS_FIXED_PAT6 0x1D0C
#define USB3_DP_PCS_FIXED_PAT7 0x1D10
#define USB3_DP_PCS_FIXED_PAT8 0x1D14
#define USB3_DP_PCS_FIXED_PAT9 0x1D18
#define USB3_DP_PCS_FIXED_PAT10 0x1D1C
#define USB3_DP_PCS_FIXED_PAT11 0x1D20
#define USB3_DP_PCS_FIXED_PAT12 0x1D24
#define USB3_DP_PCS_FIXED_PAT13 0x1D28
#define USB3_DP_PCS_FIXED_PAT14 0x1D2C
#define USB3_DP_PCS_FIXED_PAT15 0x1D30
#define USB3_DP_PCS_TXMGN_CONFIG 0x1D34
#define USB3_DP_PCS_G12S1_TXMGN_V0 0x1D38
#define USB3_DP_PCS_G12S1_TXMGN_V1 0x1D3C
#define USB3_DP_PCS_G12S1_TXMGN_V2 0x1D40
#define USB3_DP_PCS_G12S1_TXMGN_V3 0x1D44
#define USB3_DP_PCS_G12S1_TXMGN_V4 0x1D48
#define USB3_DP_PCS_G12S1_TXMGN_V0_RS 0x1D4C
#define USB3_DP_PCS_G12S1_TXMGN_V1_RS 0x1D50
#define USB3_DP_PCS_G12S1_TXMGN_V2_RS 0x1D54
#define USB3_DP_PCS_G12S1_TXMGN_V3_RS 0x1D58
#define USB3_DP_PCS_G12S1_TXMGN_V4_RS 0x1D5C
#define USB3_DP_PCS_G3S2_TXMGN_MAIN 0x1D60
#define USB3_DP_PCS_G3S2_TXMGN_MAIN_RS 0x1D64
#define USB3_DP_PCS_G12S1_TXDEEMPH_M6DB 0x1D68
#define USB3_DP_PCS_G12S1_TXDEEMPH_M3P5DB 0x1D6C
#define USB3_DP_PCS_G3S2_PRE_GAIN 0x1D70
#define USB3_DP_PCS_G3S2_POST_GAIN 0x1D74
#define USB3_DP_PCS_G3S2_PRE_POST_OFFSET 0x1D78
#define USB3_DP_PCS_G3S2_PRE_GAIN_RS 0x1D7C
#define USB3_DP_PCS_G3S2_POST_GAIN_RS 0x1D80
#define USB3_DP_PCS_G3S2_PRE_POST_OFFSET_RS 0x1D84
#define USB3_DP_PCS_RX_SIGDET_LVL 0x1D88
#define USB3_DP_PCS_RX_SIGDET_DTCT_CNTRL 0x1D8C
#define USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_L 0x1D90
#define USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_H 0x1D94
#define USB3_DP_PCS_RATE_SLEW_CNTRL1 0x1D98
#define USB3_DP_PCS_RATE_SLEW_CNTRL2 0x1D9C
#define USB3_DP_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1DA0
#define USB3_DP_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1DA4
#define USB3_DP_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1DA8
#define USB3_DP_PCS_TSYNC_RSYNC_TIME 0x1DAC
#define USB3_DP_PCS_CDR_RESET_TIME 0x1DB0
#define USB3_DP_PCS_TSYNC_DLY_TIME 0x1DB4
#define USB3_DP_PCS_ELECIDLE_DLY_SEL 0x1DB8
#define USB3_DP_PCS_CMN_ACK_OUT_SEL 0x1DBC
#define USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x1DC0
#define USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x1DC4
#define USB3_DP_PCS_ALIGN_DETECT_CONFIG3 0x1DC8
#define USB3_DP_PCS_ALIGN_DETECT_CONFIG4 0x1DCC
#define USB3_DP_PCS_PCS_TX_RX_CONFIG 0x1DD0
#define USB3_DP_PCS_RX_IDLE_DTCT_CNTRL 0x1DD4
#define USB3_DP_PCS_RX_DCC_CAL_CONFIG 0x1DD8
#define USB3_DP_PCS_EQ_CONFIG1 0x1DDC
#define USB3_DP_PCS_EQ_CONFIG2 0x1DE0
#define USB3_DP_PCS_EQ_CONFIG3 0x1DE4
#define USB3_DP_PCS_EQ_CONFIG4 0x1DE8
#define USB3_DP_PCS_EQ_CONFIG5 0x1DEC
/* Module: USB3_DP_PHY_USB3_PCS_AON_USB3_PCS_AON_USB3_PCS_AON */
#define USB3_DP_PCS_AON_CLAMP_ENABLE 0x1E00
/* Module: USB3_DP_PHY_USB3_PCS_USB3_USB3_PCS_USB3_USB3_PCS_USB3 */
#define USB3_DP_PCS_USB3_POWER_STATE_CONFIG1 0x1F00
#define USB3_DP_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x1F04
#define USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x1F08
#define USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x1F0C
#define USB3_DP_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x1F10
#define USB3_DP_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x1F14
#define USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x1F18
#define USB3_DP_PCS_USB3_LFPS_TX_ECSTART 0x1F1C
#define USB3_DP_PCS_USB3_LFPS_PER_TIMER_VAL 0x1F20
#define USB3_DP_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x1F24
#define USB3_DP_PCS_USB3_LFPS_CONFIG1 0x1F28
#define USB3_DP_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x1F2C
#define USB3_DP_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x1F30
#define USB3_DP_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x1F34
#define USB3_DP_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x1F38
#define USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x1F3C
#define USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x1F40
#define USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x1F44
#define USB3_DP_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x1F48
#define USB3_DP_PCS_USB3_ARCVR_DTCT_CM_DLY 0x1F4C
#define USB3_DP_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x1F50
#define USB3_DP_PCS_USB3_ALFPS_DEGLITCH_VAL 0x1F54
#define USB3_DP_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x1F58
#define USB3_DP_PCS_USB3_TEST_CONTROL 0x1F5C
#define USB3_DP_PCS_USB3_RXTERMINATION_DLY_SEL 0x1F60
#endif /* _DT_BINDINGS_PHY_QCOM_4NM_QMP_COMBO_USB_H */

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_PHY_QCOM_4NM_QMP_UNI_USB_H
#define _DT_BINDINGS_PHY_QCOM_4NM_QMP_UNI_USB_H
/* USB3 Uni PHY register offsets */
/* Module: USB3_UNI_PHY_QSERDES_COM_QSERDES_COM_PCIE_USB3_UNI_QMP_PLL */
#define QSERDES_COM_SSC_STEP_SIZE1_MODE1 (0x0 + 0x0)
#define QSERDES_COM_SSC_STEP_SIZE2_MODE1 (0x0 + 0x4)
#define QSERDES_COM_SSC_STEP_SIZE3_MODE1 (0x0 + 0x8)
#define QSERDES_COM_CLK_EP_DIV_MODE1 (0x0 + 0xc)
#define QSERDES_COM_CP_CTRL_MODE1 (0x0 + 0x10)
#define QSERDES_COM_PLL_RCTRL_MODE1 (0x0 + 0x14)
#define QSERDES_COM_PLL_CCTRL_MODE1 (0x0 + 0x18)
#define QSERDES_COM_CORECLK_DIV_MODE1 (0x0 + 0x1c)
#define QSERDES_COM_LOCK_CMP1_MODE1 (0x0 + 0x20)
#define QSERDES_COM_LOCK_CMP2_MODE1 (0x0 + 0x24)
#define QSERDES_COM_DEC_START_MODE1 (0x0 + 0x28)
#define QSERDES_COM_DEC_START_MSB_MODE1 (0x0 + 0x2c)
#define QSERDES_COM_DIV_FRAC_START1_MODE1 (0x0 + 0x30)
#define QSERDES_COM_DIV_FRAC_START2_MODE1 (0x0 + 0x34)
#define QSERDES_COM_DIV_FRAC_START3_MODE1 (0x0 + 0x38)
#define QSERDES_COM_HSCLK_SEL_1 (0x0 + 0x3c)
#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 (0x0 + 0x40)
#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 (0x0 + 0x44)
#define QSERDES_COM_VCO_TUNE1_MODE1 (0x0 + 0x48)
#define QSERDES_COM_VCO_TUNE2_MODE1 (0x0 + 0x4c)
#define QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 (0x0 + 0x50)
#define QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 (0x0 + 0x54)
#define QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 (0x0 + 0x58)
#define QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 (0x0 + 0x5c)
#define QSERDES_COM_SSC_STEP_SIZE1_MODE0 (0x0 + 0x60)
#define QSERDES_COM_SSC_STEP_SIZE2_MODE0 (0x0 + 0x64)
#define QSERDES_COM_SSC_STEP_SIZE3_MODE0 (0x0 + 0x68)
#define QSERDES_COM_CLK_EP_DIV_MODE0 (0x0 + 0x6c)
#define QSERDES_COM_CP_CTRL_MODE0 (0x0 + 0x70)
#define QSERDES_COM_PLL_RCTRL_MODE0 (0x0 + 0x74)
#define QSERDES_COM_PLL_CCTRL_MODE0 (0x0 + 0x78)
#define QSERDES_COM_CORECLK_DIV_MODE0 (0x0 + 0x7c)
#define QSERDES_COM_LOCK_CMP1_MODE0 (0x0 + 0x80)
#define QSERDES_COM_LOCK_CMP2_MODE0 (0x0 + 0x84)
#define QSERDES_COM_DEC_START_MODE0 (0x0 + 0x88)
#define QSERDES_COM_DEC_START_MSB_MODE0 (0x0 + 0x8c)
#define QSERDES_COM_DIV_FRAC_START1_MODE0 (0x0 + 0x90)
#define QSERDES_COM_DIV_FRAC_START2_MODE0 (0x0 + 0x94)
#define QSERDES_COM_DIV_FRAC_START3_MODE0 (0x0 + 0x98)
#define QSERDES_COM_HSCLK_HS_SWITCH_SEL_1 (0x0 + 0x9c)
#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 (0x0 + 0xa0)
#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 (0x0 + 0xa4)
#define QSERDES_COM_VCO_TUNE1_MODE0 (0x0 + 0xa8)
#define QSERDES_COM_VCO_TUNE2_MODE0 (0x0 + 0xac)
#define QSERDES_COM_ATB_SEL1 (0x0 + 0xb0)
#define QSERDES_COM_ATB_SEL2 (0x0 + 0xb4)
#define QSERDES_COM_FREQ_UPDATE (0x0 + 0xb8)
#define QSERDES_COM_BG_TIMER (0x0 + 0xbc)
#define QSERDES_COM_SSC_EN_CENTER (0x0 + 0xc0)
#define QSERDES_COM_SSC_ADJ_PER1 (0x0 + 0xc4)
#define QSERDES_COM_SSC_ADJ_PER2 (0x0 + 0xc8)
#define QSERDES_COM_SSC_PER1 (0x0 + 0xcc)
#define QSERDES_COM_SSC_PER2 (0x0 + 0xd0)
#define QSERDES_COM_POST_DIV (0x0 + 0xd4)
#define QSERDES_COM_POST_DIV_MUX (0x0 + 0xd8)
#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN (0x0 + 0xdc)
#define QSERDES_COM_CLK_ENABLE1 (0x0 + 0xe0)
#define QSERDES_COM_SYS_CLK_CTRL (0x0 + 0xe4)
#define QSERDES_COM_SYSCLK_BUF_ENABLE (0x0 + 0xe8)
#define QSERDES_COM_PLL_EN (0x0 + 0xec)
#define QSERDES_COM_DEBUG_BUS_OVRD (0x0 + 0xf0)
#define QSERDES_COM_PLL_IVCO (0x0 + 0xf4)
#define QSERDES_COM_PLL_IVCO_MODE1 (0x0 + 0xf8)
#define QSERDES_COM_CMN_IETRIM (0x0 + 0xfc)
#define QSERDES_COM_CMN_IPTRIM (0x0 + 0x100)
#define QSERDES_COM_EP_CLOCK_DETECT_CTRL (0x0 + 0x104)
#define QSERDES_COM_PLL_CNTRL (0x0 + 0x108)
#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM (0x0 + 0x10c)
#define QSERDES_COM_SYSCLK_EN_SEL (0x0 + 0x110)
#define QSERDES_COM_CML_SYSCLK_SEL (0x0 + 0x114)
#define QSERDES_COM_RESETSM_CNTRL (0x0 + 0x118)
#define QSERDES_COM_RESETSM_CNTRL2 (0x0 + 0x11c)
#define QSERDES_COM_LOCK_CMP_EN (0x0 + 0x120)
#define QSERDES_COM_LOCK_CMP_CFG (0x0 + 0x124)
#define QSERDES_COM_INTEGLOOP_INITVAL (0x0 + 0x128)
#define QSERDES_COM_INTEGLOOP_EN (0x0 + 0x12c)
#define QSERDES_COM_INTEGLOOP_P_PATH_GAIN0 (0x0 + 0x130)
#define QSERDES_COM_INTEGLOOP_P_PATH_GAIN1 (0x0 + 0x134)
#define QSERDES_COM_VCOCAL_DEADMAN_CTRL (0x0 + 0x138)
#define QSERDES_COM_VCO_TUNE_CTRL (0x0 + 0x13c)
#define QSERDES_COM_VCO_TUNE_MAP (0x0 + 0x140)
#define QSERDES_COM_VCO_TUNE_INITVAL1 (0x0 + 0x144)
#define QSERDES_COM_VCO_TUNE_INITVAL2 (0x0 + 0x148)
#define QSERDES_COM_VCO_TUNE_MINVAL1 (0x0 + 0x14c)
#define QSERDES_COM_VCO_TUNE_MINVAL2 (0x0 + 0x150)
#define QSERDES_COM_VCO_TUNE_MAXVAL1 (0x0 + 0x154)
#define QSERDES_COM_VCO_TUNE_MAXVAL2 (0x0 + 0x158)
#define QSERDES_COM_VCO_TUNE_TIMER1 (0x0 + 0x15c)
#define QSERDES_COM_VCO_TUNE_TIMER2 (0x0 + 0x160)
#define QSERDES_COM_CLK_SELECT (0x0 + 0x164)
#define QSERDES_COM_PLL_ANALOG (0x0 + 0x168)
#define QSERDES_COM_SW_RESET (0x0 + 0x16c)
#define QSERDES_COM_CORE_CLK_EN (0x0 + 0x170)
#define QSERDES_COM_CMN_CONFIG_1 (0x0 + 0x174)
#define QSERDES_COM_CMN_RATE_OVERRIDE (0x0 + 0x178)
#define QSERDES_COM_SVS_MODE_CLK_SEL (0x0 + 0x17c)
#define QSERDES_COM_DEBUG_BUS_SEL (0x0 + 0x180)
#define QSERDES_COM_CMN_MISC1 (0x0 + 0x184)
#define QSERDES_COM_CMN_MODE (0x0 + 0x188)
#define QSERDES_COM_CMN_MODE_CONTD (0x0 + 0x18c)
#define QSERDES_COM_CMN_MODE_CONTD1 (0x0 + 0x190)
#define QSERDES_COM_CMN_MODE_CONTD2 (0x0 + 0x194)
#define QSERDES_COM_VCO_DC_LEVEL_CTRL (0x0 + 0x198)
#define QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_1 (0x0 + 0x19c)
#define QSERDES_COM_ADDITIONAL_CTRL_1 (0x0 + 0x1a0)
#define QSERDES_COM_AUTO_GAIN_ADJ_CTRL_1 (0x0 + 0x1a4)
#define QSERDES_COM_AUTO_GAIN_ADJ_CTRL_2 (0x0 + 0x1a8)
#define QSERDES_COM_AUTO_GAIN_ADJ_CTRL_3 (0x0 + 0x1ac)
#define QSERDES_COM_AUTO_GAIN_ADJ_CTRL_4 (0x0 + 0x1b0)
#define QSERDES_COM_ADDITIONAL_MISC (0x0 + 0x1b4)
#define QSERDES_COM_ADDITIONAL_MISC_2 (0x0 + 0x1b8)
#define QSERDES_COM_ADDITIONAL_MISC_3 (0x0 + 0x1bc)
#define QSERDES_COM_ADDITIONAL_MISC_4 (0x0 + 0x1c0)
#define QSERDES_COM_ADDITIONAL_MISC_5 (0x0 + 0x1c4)
#define QSERDES_COM_MODE_OPERATION_STATUS (0x0 + 0x1c8)
#define QSERDES_COM_SYSCLK_DET_COMP_STATUS (0x0 + 0x1cc)
#define QSERDES_COM_CMN_STATUS (0x0 + 0x1d0)
#define QSERDES_COM_RESET_SM_STATUS (0x0 + 0x1d4)
#define QSERDES_COM_RESTRIM_CODE_STATUS (0x0 + 0x1d8)
#define QSERDES_COM_PLLCAL_CODE1_STATUS (0x0 + 0x1dc)
#define QSERDES_COM_PLLCAL_CODE2_STATUS (0x0 + 0x1e0)
#define QSERDES_COM_INTEGLOOP_BINCODE_STATUS (0x0 + 0x1e4)
#define QSERDES_COM_DEBUG_BUS0 (0x0 + 0x1e8)
#define QSERDES_COM_DEBUG_BUS1 (0x0 + 0x1ec)
#define QSERDES_COM_DEBUG_BUS2 (0x0 + 0x1f0)
#define QSERDES_COM_DEBUG_BUS3 (0x0 + 0x1f4)
#define QSERDES_COM_C_READY_STATUS (0x0 + 0x1f8)
#define QSERDES_COM_READ_DUMMY_1 (0x0 + 0x1fc)
/* Module: USB3_UNI_PHY_PCIE_USB3_UNI_PCS_PCIE_USB3_UNI_PCS_PCIE_USB3_UNI_PCS */
#define PCIE_USB3_UNI_PCS_SW_RESET (0x200 + 0x0)
#define PCIE_USB3_UNI_PCS_REVISION_ID0 (0x200 + 0x4)
#define PCIE_USB3_UNI_PCS_REVISION_ID1 (0x200 + 0x8)
#define PCIE_USB3_UNI_PCS_REVISION_ID2 (0x200 + 0xc)
#define PCIE_USB3_UNI_PCS_REVISION_ID3 (0x200 + 0x10)
#define PCIE_USB3_UNI_PCS_PCS_STATUS1 (0x200 + 0x14)
#define PCIE_USB3_UNI_PCS_PCS_STATUS2 (0x200 + 0x18)
#define PCIE_USB3_UNI_PCS_PCS_STATUS3 (0x200 + 0x1c)
#define PCIE_USB3_UNI_PCS_PCS_STATUS4 (0x200 + 0x20)
#define PCIE_USB3_UNI_PCS_PCS_STATUS5 (0x200 + 0x24)
#define PCIE_USB3_UNI_PCS_PCS_STATUS6 (0x200 + 0x28)
#define PCIE_USB3_UNI_PCS_PCS_STATUS7 (0x200 + 0x2c)
#define PCIE_USB3_UNI_PCS_DEBUG_BUS_0_STATUS (0x200 + 0x30)
#define PCIE_USB3_UNI_PCS_DEBUG_BUS_1_STATUS (0x200 + 0x34)
#define PCIE_USB3_UNI_PCS_DEBUG_BUS_2_STATUS (0x200 + 0x38)
#define PCIE_USB3_UNI_PCS_DEBUG_BUS_3_STATUS (0x200 + 0x3c)
#define PCIE_USB3_UNI_PCS_POWER_DOWN_CONTROL (0x200 + 0x40)
#define PCIE_USB3_UNI_PCS_START_CONTROL (0x200 + 0x44)
#define PCIE_USB3_UNI_PCS_INSIG_SW_CTRL1 (0x200 + 0x48)
#define PCIE_USB3_UNI_PCS_INSIG_SW_CTRL2 (0x200 + 0x4c)
#define PCIE_USB3_UNI_PCS_INSIG_SW_CTRL3 (0x200 + 0x50)
#define PCIE_USB3_UNI_PCS_INSIG_SW_CTRL4 (0x200 + 0x54)
#define PCIE_USB3_UNI_PCS_INSIG_SW_CTRL5 (0x200 + 0x58)
#define PCIE_USB3_UNI_PCS_INSIG_SW_CTRL6 (0x200 + 0x5c)
#define PCIE_USB3_UNI_PCS_INSIG_SW_CTRL7 (0x200 + 0x60)
#define PCIE_USB3_UNI_PCS_INSIG_SW_CTRL8 (0x200 + 0x64)
#define PCIE_USB3_UNI_PCS_INSIG_MX_CTRL1 (0x200 + 0x68)
#define PCIE_USB3_UNI_PCS_INSIG_MX_CTRL2 (0x200 + 0x6c)
#define PCIE_USB3_UNI_PCS_INSIG_MX_CTRL3 (0x200 + 0x70)
#define PCIE_USB3_UNI_PCS_INSIG_MX_CTRL4 (0x200 + 0x74)
#define PCIE_USB3_UNI_PCS_INSIG_MX_CTRL5 (0x200 + 0x78)
#define PCIE_USB3_UNI_PCS_INSIG_MX_CTRL7 (0x200 + 0x7c)
#define PCIE_USB3_UNI_PCS_INSIG_MX_CTRL8 (0x200 + 0x80)
#define PCIE_USB3_UNI_PCS_OUTSIG_SW_CTRL1 (0x200 + 0x84)
#define PCIE_USB3_UNI_PCS_OUTSIG_MX_CTRL1 (0x200 + 0x88)
#define PCIE_USB3_UNI_PCS_CLAMP_ENABLE (0x200 + 0x8c)
#define PCIE_USB3_UNI_PCS_POWER_STATE_CONFIG1 (0x200 + 0x90)
#define PCIE_USB3_UNI_PCS_POWER_STATE_CONFIG2 (0x200 + 0x94)
#define PCIE_USB3_UNI_PCS_FLL_CNTRL1 (0x200 + 0x98)
#define PCIE_USB3_UNI_PCS_FLL_CNTRL2 (0x200 + 0x9c)
#define PCIE_USB3_UNI_PCS_FLL_CNT_VAL_L (0x200 + 0xa0)
#define PCIE_USB3_UNI_PCS_FLL_CNT_VAL_H_TOL (0x200 + 0xa4)
#define PCIE_USB3_UNI_PCS_FLL_MAN_CODE (0x200 + 0xa8)
#define PCIE_USB3_UNI_PCS_TEST_CONTROL1 (0x200 + 0xac)
#define PCIE_USB3_UNI_PCS_TEST_CONTROL2 (0x200 + 0xb0)
#define PCIE_USB3_UNI_PCS_TEST_CONTROL3 (0x200 + 0xb4)
#define PCIE_USB3_UNI_PCS_TEST_CONTROL4 (0x200 + 0xb8)
#define PCIE_USB3_UNI_PCS_TEST_CONTROL5 (0x200 + 0xbc)
#define PCIE_USB3_UNI_PCS_TEST_CONTROL6 (0x200 + 0xc0)
#define PCIE_USB3_UNI_PCS_LOCK_DETECT_CONFIG1 (0x200 + 0xc4)
#define PCIE_USB3_UNI_PCS_LOCK_DETECT_CONFIG2 (0x200 + 0xc8)
#define PCIE_USB3_UNI_PCS_LOCK_DETECT_CONFIG3 (0x200 + 0xcc)
#define PCIE_USB3_UNI_PCS_LOCK_DETECT_CONFIG4 (0x200 + 0xd0)
#define PCIE_USB3_UNI_PCS_LOCK_DETECT_CONFIG5 (0x200 + 0xd4)
#define PCIE_USB3_UNI_PCS_LOCK_DETECT_CONFIG6 (0x200 + 0xd8)
#define PCIE_USB3_UNI_PCS_REFGEN_REQ_CONFIG1 (0x200 + 0xdc)
#define PCIE_USB3_UNI_PCS_REFGEN_REQ_CONFIG2 (0x200 + 0xe0)
#define PCIE_USB3_UNI_PCS_REFGEN_REQ_CONFIG3 (0x200 + 0xe4)
#define PCIE_USB3_UNI_PCS_BIST_CTRL (0x200 + 0xe8)
#define PCIE_USB3_UNI_PCS_PRBS_POLY0 (0x200 + 0xec)
#define PCIE_USB3_UNI_PCS_PRBS_POLY1 (0x200 + 0xf0)
#define PCIE_USB3_UNI_PCS_FIXED_PAT0 (0x200 + 0xf4)
#define PCIE_USB3_UNI_PCS_FIXED_PAT1 (0x200 + 0xf8)
#define PCIE_USB3_UNI_PCS_FIXED_PAT2 (0x200 + 0xfc)
#define PCIE_USB3_UNI_PCS_FIXED_PAT3 (0x200 + 0x100)
#define PCIE_USB3_UNI_PCS_FIXED_PAT4 (0x200 + 0x104)
#define PCIE_USB3_UNI_PCS_FIXED_PAT5 (0x200 + 0x108)
#define PCIE_USB3_UNI_PCS_FIXED_PAT6 (0x200 + 0x10c)
#define PCIE_USB3_UNI_PCS_FIXED_PAT7 (0x200 + 0x110)
#define PCIE_USB3_UNI_PCS_FIXED_PAT8 (0x200 + 0x114)
#define PCIE_USB3_UNI_PCS_FIXED_PAT9 (0x200 + 0x118)
#define PCIE_USB3_UNI_PCS_FIXED_PAT10 (0x200 + 0x11c)
#define PCIE_USB3_UNI_PCS_FIXED_PAT11 (0x200 + 0x120)
#define PCIE_USB3_UNI_PCS_FIXED_PAT12 (0x200 + 0x124)
#define PCIE_USB3_UNI_PCS_FIXED_PAT13 (0x200 + 0x128)
#define PCIE_USB3_UNI_PCS_FIXED_PAT14 (0x200 + 0x12c)
#define PCIE_USB3_UNI_PCS_FIXED_PAT15 (0x200 + 0x130)
#define PCIE_USB3_UNI_PCS_TXMGN_CONFIG (0x200 + 0x134)
#define PCIE_USB3_UNI_PCS_G12S1_TXMGN_V0 (0x200 + 0x138)
#define PCIE_USB3_UNI_PCS_G12S1_TXMGN_V1 (0x200 + 0x13c)
#define PCIE_USB3_UNI_PCS_G12S1_TXMGN_V2 (0x200 + 0x140)
#define PCIE_USB3_UNI_PCS_G12S1_TXMGN_V3 (0x200 + 0x144)
#define PCIE_USB3_UNI_PCS_G12S1_TXMGN_V4 (0x200 + 0x148)
#define PCIE_USB3_UNI_PCS_G12S1_TXMGN_V0_RS (0x200 + 0x14c)
#define PCIE_USB3_UNI_PCS_G12S1_TXMGN_V1_RS (0x200 + 0x150)
#define PCIE_USB3_UNI_PCS_G12S1_TXMGN_V2_RS (0x200 + 0x154)
#define PCIE_USB3_UNI_PCS_G12S1_TXMGN_V3_RS (0x200 + 0x158)
#define PCIE_USB3_UNI_PCS_G12S1_TXMGN_V4_RS (0x200 + 0x15c)
#define PCIE_USB3_UNI_PCS_G3S2_TXMGN_MAIN (0x200 + 0x160)
#define PCIE_USB3_UNI_PCS_G3S2_TXMGN_MAIN_RS (0x200 + 0x164)
#define PCIE_USB3_UNI_PCS_G12S1_TXDEEMPH_M6DB (0x200 + 0x168)
#define PCIE_USB3_UNI_PCS_G12S1_TXDEEMPH_M3P5DB (0x200 + 0x16c)
#define PCIE_USB3_UNI_PCS_G3S2_PRE_GAIN (0x200 + 0x170)
#define PCIE_USB3_UNI_PCS_G3S2_POST_GAIN (0x200 + 0x174)
#define PCIE_USB3_UNI_PCS_G3S2_PRE_POST_OFFSET (0x200 + 0x178)
#define PCIE_USB3_UNI_PCS_G3S2_PRE_GAIN_RS (0x200 + 0x17c)
#define PCIE_USB3_UNI_PCS_G3S2_POST_GAIN_RS (0x200 + 0x180)
#define PCIE_USB3_UNI_PCS_G3S2_PRE_POST_OFFSET_RS (0x200 + 0x184)
#define PCIE_USB3_UNI_PCS_RX_SIGDET_LVL (0x200 + 0x188)
#define PCIE_USB3_UNI_PCS_RX_SIGDET_DTCT_CNTRL (0x200 + 0x18c)
#define PCIE_USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L (0x200 + 0x190)
#define PCIE_USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H (0x200 + 0x194)
#define PCIE_USB3_UNI_PCS_RATE_SLEW_CNTRL1 (0x200 + 0x198)
#define PCIE_USB3_UNI_PCS_RATE_SLEW_CNTRL2 (0x200 + 0x19c)
#define PCIE_USB3_UNI_PCS_PWRUP_RESET_DLY_TIME_AUXCLK (0x200 + 0x1a0)
#define PCIE_USB3_UNI_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L (0x200 + 0x1a4)
#define PCIE_USB3_UNI_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H (0x200 + 0x1a8)
#define PCIE_USB3_UNI_PCS_TSYNC_RSYNC_TIME (0x200 + 0x1ac)
#define PCIE_USB3_UNI_PCS_CDR_RESET_TIME (0x200 + 0x1b0)
#define PCIE_USB3_UNI_PCS_TSYNC_DLY_TIME (0x200 + 0x1b4)
#define PCIE_USB3_UNI_PCS_ELECIDLE_DLY_SEL (0x200 + 0x1b8)
#define PCIE_USB3_UNI_PCS_CMN_ACK_OUT_SEL (0x200 + 0x1bc)
#define PCIE_USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 (0x200 + 0x1c0)
#define PCIE_USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 (0x200 + 0x1c4)
#define PCIE_USB3_UNI_PCS_ALIGN_DETECT_CONFIG3 (0x200 + 0x1c8)
#define PCIE_USB3_UNI_PCS_ALIGN_DETECT_CONFIG4 (0x200 + 0x1cc)
#define PCIE_USB3_UNI_PCS_PCS_TX_RX_CONFIG (0x200 + 0x1d0)
#define PCIE_USB3_UNI_PCS_RX_IDLE_DTCT_CNTRL (0x200 + 0x1d4)
#define PCIE_USB3_UNI_PCS_RX_DCC_CAL_CONFIG (0x200 + 0x1d8)
#define PCIE_USB3_UNI_PCS_EQ_CONFIG1 (0x200 + 0x1dc)
#define PCIE_USB3_UNI_PCS_EQ_CONFIG2 (0x200 + 0x1e0)
#define PCIE_USB3_UNI_PCS_EQ_CONFIG3 (0x200 + 0x1e4)
#define PCIE_USB3_UNI_PCS_EQ_CONFIG4 (0x200 + 0x1e8)
#define PCIE_USB3_UNI_PCS_EQ_CONFIG5 (0x200 + 0x1ec)
/* Module: USB3_UNI_PHY_PCIE_USB3_UNI_PCS_PCIE_PCIE_USB3_UNI_PCS_PCIE_PCIE_USB3_UNI_PCS_PCIE */
#define PCIE_USB3_UNI_PCS_PCIE_INT_AUX_CLK_STATUS (0x600 + 0x0)
#define PCIE_USB3_UNI_PCS_PCIE_OSC_DTCT_STATUS (0x600 + 0x4)
#define PCIE_USB3_UNI_PCS_PCIE_POWER_STATE_CONFIG1 (0x600 + 0x8)
#define PCIE_USB3_UNI_PCS_PCIE_POWER_STATE_CONFIG2 (0x600 + 0xc)
#define PCIE_USB3_UNI_PCS_PCIE_POWER_STATE_CONFIG3 (0x600 + 0x10)
#define PCIE_USB3_UNI_PCS_PCIE_POWER_STATE_CONFIG4 (0x600 + 0x14)
#define PCIE_USB3_UNI_PCS_PCIE_POWER_STATE_CONFIG5 (0x600 + 0x18)
#define PCIE_USB3_UNI_PCS_PCIE_PCS_TX_RX_CONFIG (0x600 + 0x1c)
#define PCIE_USB3_UNI_PCS_PCIE_ENDPOINT_REFCLK_DRIVE (0x600 + 0x20)
#define PCIE_USB3_UNI_PCS_PCIE_ENDPOINT_REFCLK_CNTRL (0x600 + 0x24)
#define PCIE_USB3_UNI_PCS_PCIE_EPCLK_PRE_PLL_LOCK_DLY_AUXCLK (0x600 + 0x28)
#define PCIE_USB3_UNI_PCS_PCIE_EPCLK_DLY_COUNT_VAL_L (0x600 + 0x2c)
#define PCIE_USB3_UNI_PCS_PCIE_EPCLK_DLY_COUNT_VAL_H (0x600 + 0x30)
#define PCIE_USB3_UNI_PCS_PCIE_RX_IDLE_DTCT_CNTRL1 (0x600 + 0x34)
#define PCIE_USB3_UNI_PCS_PCIE_RX_IDLE_DTCT_CNTRL2 (0x600 + 0x38)
#define PCIE_USB3_UNI_PCS_PCIE_SIGDET_CNTRL (0x600 + 0x3c)
#define PCIE_USB3_UNI_PCS_PCIE_SIGDET_LOW_2_IDLE_TIME (0x600 + 0x40)
#define PCIE_USB3_UNI_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L (0x600 + 0x44)
#define PCIE_USB3_UNI_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H (0x600 + 0x48)
#define PCIE_USB3_UNI_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L (0x600 + 0x4c)
#define PCIE_USB3_UNI_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H (0x600 + 0x50)
#define PCIE_USB3_UNI_PCS_PCIE_INT_AUX_CLK_CONFIG1 (0x600 + 0x54)
#define PCIE_USB3_UNI_PCS_PCIE_INT_AUX_CLK_CONFIG2 (0x600 + 0x58)
#define PCIE_USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG1 (0x600 + 0x5c)
#define PCIE_USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG2 (0x600 + 0x60)
#define PCIE_USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG3 (0x600 + 0x64)
#define PCIE_USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG4 (0x600 + 0x68)
#define PCIE_USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG5 (0x600 + 0x6c)
#define PCIE_USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG6 (0x600 + 0x70)
#define PCIE_USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG7 (0x600 + 0x74)
#define PCIE_USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG1 (0x600 + 0x78)
#define PCIE_USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 (0x600 + 0x7c)
#define PCIE_USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG3 (0x600 + 0x80)
#define PCIE_USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 (0x600 + 0x84)
#define PCIE_USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 (0x600 + 0x88)
#define PCIE_USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6 (0x600 + 0x8c)
#define PCIE_USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG7 (0x600 + 0x90)
#define PCIE_USB3_UNI_PCS_PCIE_OSC_DTCT_ACTIONS (0x600 + 0x94)
#define PCIE_USB3_UNI_PCS_PCIE_LOCAL_FS (0x600 + 0x98)
#define PCIE_USB3_UNI_PCS_PCIE_LOCAL_LF (0x600 + 0x9c)
#define PCIE_USB3_UNI_PCS_PCIE_LOCAL_FS_RS (0x600 + 0xa0)
#define PCIE_USB3_UNI_PCS_PCIE_EQ_CONFIG1 (0x600 + 0xa4)
#define PCIE_USB3_UNI_PCS_PCIE_EQ_CONFIG2 (0x600 + 0xa8)
#define PCIE_USB3_UNI_PCS_PCIE_PRESET_P0_P1_PRE (0x600 + 0xac)
#define PCIE_USB3_UNI_PCS_PCIE_PRESET_P2_P3_PRE (0x600 + 0xb0)
#define PCIE_USB3_UNI_PCS_PCIE_PRESET_P4_P5_PRE (0x600 + 0xb4)
#define PCIE_USB3_UNI_PCS_PCIE_PRESET_P6_P7_PRE (0x600 + 0xb8)
#define PCIE_USB3_UNI_PCS_PCIE_PRESET_P8_P9_PRE (0x600 + 0xbc)
#define PCIE_USB3_UNI_PCS_PCIE_PRESET_P10_PRE (0x600 + 0xc0)
#define PCIE_USB3_UNI_PCS_PCIE_PRESET_P1_P3_PRE_RS (0x600 + 0xc4)
#define PCIE_USB3_UNI_PCS_PCIE_PRESET_P4_P5_PRE_RS (0x600 + 0xc8)
#define PCIE_USB3_UNI_PCS_PCIE_PRESET_P6_P9_PRE_RS (0x600 + 0xcc)
#define PCIE_USB3_UNI_PCS_PCIE_PRESET_P0_P1_POST (0x600 + 0xd0)
#define PCIE_USB3_UNI_PCS_PCIE_PRESET_P2_P3_POST (0x600 + 0xd4)
#define PCIE_USB3_UNI_PCS_PCIE_PRESET_P4_P5_POST (0x600 + 0xd8)
#define PCIE_USB3_UNI_PCS_PCIE_PRESET_P6_P7_POST (0x600 + 0xdc)
#define PCIE_USB3_UNI_PCS_PCIE_PRESET_P8_P9_POST (0x600 + 0xe0)
#define PCIE_USB3_UNI_PCS_PCIE_PRESET_P10_POST (0x600 + 0xe4)
#define PCIE_USB3_UNI_PCS_PCIE_PRESET_P1_P3_POST_RS (0x600 + 0xe8)
#define PCIE_USB3_UNI_PCS_PCIE_PRESET_P4_P5_POST_RS (0x600 + 0xec)
#define PCIE_USB3_UNI_PCS_PCIE_PRESET_P6_P9_POST_RS (0x600 + 0xf0)
#define PCIE_USB3_UNI_PCS_PCIE_RXEQEVAL_TIME (0x600 + 0xf4)
/* Module:
* USB3_UNI_PHY_PCIE_USB3_UNI_PCS_INTGEN_PCIE_USB3_UNI_PCS_INTGEN_PCIE_USB3_UNI_PCS_DEBUG_INTGEN
*/
#define PCIE_USB3_UNI_PCS_INTGEN_INTGEN_STATUS1 (0x800 + 0x0)
#define PCIE_USB3_UNI_PCS_INTGEN_INTGEN_STATUS2 (0x800 + 0x4)
#define PCIE_USB3_UNI_PCS_INTGEN_CONFIG1 (0x800 + 0x8)
#define PCIE_USB3_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG1 (0x800 + 0xc)
#define PCIE_USB3_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG2 (0x800 + 0x10)
#define PCIE_USB3_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG3 (0x800 + 0x14)
#define PCIE_USB3_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG4 (0x800 + 0x18)
#define PCIE_USB3_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG5 (0x800 + 0x1c)
#define PCIE_USB3_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG1 (0x800 + 0x20)
#define PCIE_USB3_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG2 (0x800 + 0x24)
#define PCIE_USB3_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG3 (0x800 + 0x28)
#define PCIE_USB3_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG4 (0x800 + 0x2c)
#define PCIE_USB3_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG5 (0x800 + 0x30)
#define PCIE_USB3_UNI_PCS_INTGEN_STRINGBLK1_CONFIG1 (0x800 + 0x34)
#define PCIE_USB3_UNI_PCS_INTGEN_STRINGBLK1_CONFIG2 (0x800 + 0x38)
#define PCIE_USB3_UNI_PCS_INTGEN_STRINGBLK1_CONFIG3 (0x800 + 0x3c)
#define PCIE_USB3_UNI_PCS_INTGEN_STRINGBLK1_CONFIG4 (0x800 + 0x40)
#define PCIE_USB3_UNI_PCS_INTGEN_STRINGBLK1_CONFIG5 (0x800 + 0x44)
#define PCIE_USB3_UNI_PCS_INTGEN_STRINGBLK2_CONFIG1 (0x800 + 0x48)
#define PCIE_USB3_UNI_PCS_INTGEN_STRINGBLK2_CONFIG2 (0x800 + 0x4c)
#define PCIE_USB3_UNI_PCS_INTGEN_STRINGBLK2_CONFIG3 (0x800 + 0x50)
#define PCIE_USB3_UNI_PCS_INTGEN_STRINGBLK2_CONFIG4 (0x800 + 0x54)
#define PCIE_USB3_UNI_PCS_INTGEN_STRINGBLK2_CONFIG5 (0x800 + 0x58)
/* Module: USB3_UNI_PHY_PCIE_USB3_UNI_PCS_LN_PCIE_USB3_UNI_PCS_LN_PCIE_USB3_UNI_PCS_LANE */
#define PCIE_USB3_UNI_PCS_LN_PCS_STATUS1 (0xa00 + 0x0)
#define PCIE_USB3_UNI_PCS_LN_PCS_STATUS2 (0xa00 + 0x4)
#define PCIE_USB3_UNI_PCS_LN_PCS_STATUS2_CLEAR (0xa00 + 0x8)
#define PCIE_USB3_UNI_PCS_LN_PCS_STATUS3 (0xa00 + 0xc)
#define PCIE_USB3_UNI_PCS_LN_BIST_CHK_ERR_CNT_L_STATUS (0xa00 + 0x10)
#define PCIE_USB3_UNI_PCS_LN_BIST_CHK_ERR_CNT_H_STATUS (0xa00 + 0x14)
#define PCIE_USB3_UNI_PCS_LN_BIST_CHK_STATUS (0xa00 + 0x18)
#define PCIE_USB3_UNI_PCS_LN_INSIG_SW_CTRL1 (0xa00 + 0x1c)
#define PCIE_USB3_UNI_PCS_LN_INSIG_MX_CTRL1 (0xa00 + 0x20)
#define PCIE_USB3_UNI_PCS_LN_OUTSIG_SW_CTRL1 (0xa00 + 0x24)
#define PCIE_USB3_UNI_PCS_LN_OUTSIG_MX_CTRL1 (0xa00 + 0x28)
#define PCIE_USB3_UNI_PCS_LN_TEST_CONTROL1 (0xa00 + 0x2c)
#define PCIE_USB3_UNI_PCS_LN_BIST_CTRL (0xa00 + 0x30)
#define PCIE_USB3_UNI_PCS_LN_PRBS_SEED0 (0xa00 + 0x34)
#define PCIE_USB3_UNI_PCS_LN_PRBS_SEED1 (0xa00 + 0x38)
#define PCIE_USB3_UNI_PCS_LN_FIXED_PAT_CTRL (0xa00 + 0x3c)
#define PCIE_USB3_UNI_PCS_LN_EQ_CONFIG (0xa00 + 0x40)
#define PCIE_USB3_UNI_PCS_LN_TEST_CONTROL2 (0xa00 + 0x44)
#define PCIE_USB3_UNI_PCS_LN_TEST_CONTROL3 (0xa00 + 0x48)
/* Module:
* USB3_UNI_PHY_PCIE_USB3_UNI_PCS_PCIE_LN_PCIE_USB3_UNI_PCS_PCIE_LN_PCIE_USB3_UNI_PCS_PCIE_LANE
*/
#define PCIE_USB3_UNI_PCS_PCIE_LN_PRESET_OVERRIDE_PRE_POST (0xc00 + 0x0)
#define PCIE_USB3_UNI_PCS_PCIE_LN_PRESET_OVERRIDE_PRE_POST_RS (0xc00 + 0x4)
#define PCIE_USB3_UNI_PCS_PCIE_LN_PRESET_OVERRIDE_EN (0xc00 + 0x8)
#define PCIE_USB3_UNI_PCS_PCIE_LN_PRESET_DSBL_L (0xc00 + 0xc)
#define PCIE_USB3_UNI_PCS_PCIE_LN_PRESET_DSBL_H (0xc00 + 0x10)
#define PCIE_USB3_UNI_PCS_PCIE_LN_LANE_OFF_CONFIG (0xc00 + 0x14)
#define PCIE_USB3_UNI_PCS_PCIE_LN_RXEQ_DONE_CONFIG1 (0xc00 + 0x18)
#define PCIE_USB3_UNI_PCS_PCIE_LN_RXEQ_DONE_CONFIG2 (0xc00 + 0x1c)
#define PCIE_USB3_UNI_PCS_PCIE_LN_PCIE_PCS_STATUS (0xc00 + 0x20)
#define PCIE_USB3_UNI_PCS_PCIE_LN_INSIG_SW_CTRL2 (0xc00 + 0x24)
#define PCIE_USB3_UNI_PCS_PCIE_LN_INSIG_MX_CTRL2 (0xc00 + 0x28)
/* Module: USB3_UNI_PHY_QSERDES_TX_QSERDES_TX_PCIE_USB3_UNI_QMP_TX */
#define QSERDES_TX_BIST_MODE_LANENO (0xe00 + 0x0)
#define QSERDES_TX_BIST_INVERT (0xe00 + 0x4)
#define QSERDES_TX_CLKBUF_ENABLE (0xe00 + 0x8)
#define QSERDES_TX_TX_EMP_POST1_LVL (0xe00 + 0xc)
#define QSERDES_TX_TX_IDLE_LVL_LARGE_AMP (0xe00 + 0x10)
#define QSERDES_TX_TX_DRV_LVL (0xe00 + 0x14)
#define QSERDES_TX_TX_DRV_LVL_OFFSET (0xe00 + 0x18)
#define QSERDES_TX_RESET_TSYNC_EN (0xe00 + 0x1c)
#define QSERDES_TX_PRE_STALL_LDO_BOOST_EN (0xe00 + 0x20)
#define QSERDES_TX_TX_BAND (0xe00 + 0x24)
#define QSERDES_TX_SLEW_CNTL (0xe00 + 0x28)
#define QSERDES_TX_INTERFACE_SELECT (0xe00 + 0x2c)
#define QSERDES_TX_LPB_EN (0xe00 + 0x30)
#define QSERDES_TX_RES_CODE_LANE_TX (0xe00 + 0x34)
#define QSERDES_TX_RES_CODE_LANE_RX (0xe00 + 0x38)
#define QSERDES_TX_RES_CODE_LANE_OFFSET_TX (0xe00 + 0x3c)
#define QSERDES_TX_RES_CODE_LANE_OFFSET_RX (0xe00 + 0x40)
#define QSERDES_TX_PERL_LENGTH1 (0xe00 + 0x44)
#define QSERDES_TX_PERL_LENGTH2 (0xe00 + 0x48)
#define QSERDES_TX_SERDES_BYP_EN_OUT (0xe00 + 0x4c)
#define QSERDES_TX_DEBUG_BUS_SEL (0xe00 + 0x50)
#define QSERDES_TX_TRANSCEIVER_BIAS_EN (0xe00 + 0x54)
#define QSERDES_TX_HIGHZ_DRVR_EN (0xe00 + 0x58)
#define QSERDES_TX_TX_POL_INV (0xe00 + 0x5c)
#define QSERDES_TX_PARRATE_REC_DETECT_IDLE_EN (0xe00 + 0x60)
#define QSERDES_TX_BIST_PATTERN1 (0xe00 + 0x64)
#define QSERDES_TX_BIST_PATTERN2 (0xe00 + 0x68)
#define QSERDES_TX_BIST_PATTERN3 (0xe00 + 0x6c)
#define QSERDES_TX_BIST_PATTERN4 (0xe00 + 0x70)
#define QSERDES_TX_BIST_PATTERN5 (0xe00 + 0x74)
#define QSERDES_TX_BIST_PATTERN6 (0xe00 + 0x78)
#define QSERDES_TX_BIST_PATTERN7 (0xe00 + 0x7c)
#define QSERDES_TX_BIST_PATTERN8 (0xe00 + 0x80)
#define QSERDES_TX_LANE_MODE_1 (0xe00 + 0x84)
#define QSERDES_TX_LANE_MODE_2 (0xe00 + 0x88)
#define QSERDES_TX_LANE_MODE_3 (0xe00 + 0x8c)
#define QSERDES_TX_LANE_MODE_4 (0xe00 + 0x90)
#define QSERDES_TX_LANE_MODE_5 (0xe00 + 0x94)
#define QSERDES_TX_ATB_SEL1 (0xe00 + 0x98)
#define QSERDES_TX_ATB_SEL2 (0xe00 + 0x9c)
#define QSERDES_TX_RCV_DETECT_LVL (0xe00 + 0xa0)
#define QSERDES_TX_RCV_DETECT_LVL_2 (0xe00 + 0xa4)
#define QSERDES_TX_PRBS_SEED1 (0xe00 + 0xa8)
#define QSERDES_TX_PRBS_SEED2 (0xe00 + 0xac)
#define QSERDES_TX_PRBS_SEED3 (0xe00 + 0xb0)
#define QSERDES_TX_PRBS_SEED4 (0xe00 + 0xb4)
#define QSERDES_TX_RESET_GEN (0xe00 + 0xb8)
#define QSERDES_TX_RESET_GEN_MUXES (0xe00 + 0xbc)
#define QSERDES_TX_TRAN_DRVR_EMP_EN (0xe00 + 0xc0)
#define QSERDES_TX_TX_INTERFACE_MODE (0xe00 + 0xc4)
#define QSERDES_TX_VMODE_CTRL1 (0xe00 + 0xc8)
#define QSERDES_TX_ALOG_OBSV_BUS_CTRL_1 (0xe00 + 0xcc)
#define QSERDES_TX_BIST_STATUS (0xe00 + 0xd0)
#define QSERDES_TX_BIST_ERROR_COUNT1 (0xe00 + 0xd4)
#define QSERDES_TX_BIST_ERROR_COUNT2 (0xe00 + 0xd8)
#define QSERDES_TX_ALOG_OBSV_BUS_STATUS_1 (0xe00 + 0xdc)
#define QSERDES_TX_LANE_DIG_CONFIG (0xe00 + 0xe0)
#define QSERDES_TX_PI_QEC_CTRL (0xe00 + 0xe4)
#define QSERDES_TX_PRE_EMPH (0xe00 + 0xe8)
#define QSERDES_TX_SW_RESET (0xe00 + 0xec)
#define QSERDES_TX_DCC_OFFSET (0xe00 + 0xf0)
#define QSERDES_TX_DCC_CMUX_POSTCAL_OFFSET (0xe00 + 0xf4)
#define QSERDES_TX_DCC_CMUX_CAL_CTRL1 (0xe00 + 0xf8)
#define QSERDES_TX_DCC_CMUX_CAL_CTRL2 (0xe00 + 0xfc)
#define QSERDES_TX_DIG_BKUP_CTRL (0xe00 + 0x100)
#define QSERDES_TX_DEBUG_BUS0 (0xe00 + 0x104)
#define QSERDES_TX_DEBUG_BUS1 (0xe00 + 0x108)
#define QSERDES_TX_DEBUG_BUS2 (0xe00 + 0x10c)
#define QSERDES_TX_DEBUG_BUS3 (0xe00 + 0x110)
#define QSERDES_TX_READ_EQCODE (0xe00 + 0x114)
#define QSERDES_TX_READ_OFFSETCODE (0xe00 + 0x118)
#define QSERDES_TX_IA_ERROR_COUNTER_LOW (0xe00 + 0x11c)
#define QSERDES_TX_IA_ERROR_COUNTER_HIGH (0xe00 + 0x120)
#define QSERDES_TX_VGA_READ_CODE (0xe00 + 0x124)
#define QSERDES_TX_VTH_READ_CODE (0xe00 + 0x128)
#define QSERDES_TX_DFE_TAP1_READ_CODE (0xe00 + 0x12c)
#define QSERDES_TX_DFE_TAP2_READ_CODE (0xe00 + 0x130)
#define QSERDES_TX_IDAC_STATUS_I (0xe00 + 0x134)
#define QSERDES_TX_IDAC_STATUS_IBAR (0xe00 + 0x138)
#define QSERDES_TX_IDAC_STATUS_Q (0xe00 + 0x13c)
#define QSERDES_TX_IDAC_STATUS_QBAR (0xe00 + 0x140)
#define QSERDES_TX_IDAC_STATUS_A (0xe00 + 0x144)
#define QSERDES_TX_IDAC_STATUS_ABAR (0xe00 + 0x148)
#define QSERDES_TX_IDAC_STATUS_SM_ON (0xe00 + 0x14c)
#define QSERDES_TX_IDAC_STATUS_CAL_DONE (0xe00 + 0x150)
#define QSERDES_TX_IDAC_STATUS_SIGNERROR (0xe00 + 0x154)
#define QSERDES_TX_DCC_CAL_STATUS (0xe00 + 0x158)
#define QSERDES_TX_DCC_READ_CODE_STATUS (0xe00 + 0x15c)
#define QSERDES_TX_SIGDET_CAL_ENGINE_STATUS (0xe00 + 0x160)
#define QSERDES_TX_AC_JTAG_OUTP_OUTN_STATUS (0xe00 + 0x164)
/* Module: USB3_UNI_PHY_QSERDES_RX_QSERDES_RX_PCIE_USB3_UNI_QMP_RX */
#define QSERDES_RX_UCDR_FO_GAIN_HALF (0x1000 + 0x0)
#define QSERDES_RX_UCDR_FO_GAIN_QUARTER (0x1000 + 0x4)
#define QSERDES_RX_UCDR_FO_GAIN (0x1000 + 0x8)
#define QSERDES_RX_UCDR_SO_GAIN_HALF (0x1000 + 0xc)
#define QSERDES_RX_UCDR_SO_GAIN_QUARTER (0x1000 + 0x10)
#define QSERDES_RX_UCDR_SO_GAIN (0x1000 + 0x14)
#define QSERDES_RX_UCDR_SVS_FO_GAIN_HALF (0x1000 + 0x18)
#define QSERDES_RX_UCDR_SVS_FO_GAIN_QUARTER (0x1000 + 0x1c)
#define QSERDES_RX_UCDR_SVS_FO_GAIN (0x1000 + 0x20)
#define QSERDES_RX_UCDR_SVS_SO_GAIN_HALF (0x1000 + 0x24)
#define QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER (0x1000 + 0x28)
#define QSERDES_RX_UCDR_SVS_SO_GAIN (0x1000 + 0x2c)
#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN (0x1000 + 0x30)
#define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE (0x1000 + 0x34)
#define QSERDES_RX_UCDR_FO_TO_SO_DELAY (0x1000 + 0x38)
#define QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW (0x1000 + 0x3c)
#define QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH (0x1000 + 0x40)
#define QSERDES_RX_UCDR_PI_CONTROLS (0x1000 + 0x44)
#define QSERDES_RX_UCDR_PI_CTRL2 (0x1000 + 0x48)
#define QSERDES_RX_UCDR_SB2_THRESH1 (0x1000 + 0x4c)
#define QSERDES_RX_UCDR_SB2_THRESH2 (0x1000 + 0x50)
#define QSERDES_RX_UCDR_SB2_GAIN1 (0x1000 + 0x54)
#define QSERDES_RX_UCDR_SB2_GAIN2 (0x1000 + 0x58)
#define QSERDES_RX_AUX_CONTROL (0x1000 + 0x5c)
#define QSERDES_RX_AUX_DATA_TCOARSE_TFINE (0x1000 + 0x60)
#define QSERDES_RX_RCLK_AUXDATA_SEL (0x1000 + 0x64)
#define QSERDES_RX_AC_JTAG_ENABLE (0x1000 + 0x68)
#define QSERDES_RX_AC_JTAG_INITP (0x1000 + 0x6c)
#define QSERDES_RX_AC_JTAG_INITN (0x1000 + 0x70)
#define QSERDES_RX_AC_JTAG_LVL (0x1000 + 0x74)
#define QSERDES_RX_AC_JTAG_MODE (0x1000 + 0x78)
#define QSERDES_RX_AC_JTAG_RESET (0x1000 + 0x7c)
#define QSERDES_RX_RX_TERM_BW (0x1000 + 0x80)
#define QSERDES_RX_RX_RCVR_IQ_EN (0x1000 + 0x84)
#define QSERDES_RX_RX_IDAC_I_DC_OFFSETS (0x1000 + 0x88)
#define QSERDES_RX_RX_IDAC_IBAR_DC_OFFSETS (0x1000 + 0x8c)
#define QSERDES_RX_RX_IDAC_Q_DC_OFFSETS (0x1000 + 0x90)
#define QSERDES_RX_RX_IDAC_QBAR_DC_OFFSETS (0x1000 + 0x94)
#define QSERDES_RX_RX_IDAC_A_DC_OFFSETS (0x1000 + 0x98)
#define QSERDES_RX_RX_IDAC_ABAR_DC_OFFSETS (0x1000 + 0x9c)
#define QSERDES_RX_RX_IDAC_EN (0x1000 + 0xa0)
#define QSERDES_RX_RX_IDAC_ENABLES (0x1000 + 0xa4)
#define QSERDES_RX_RX_IDAC_SIGN (0x1000 + 0xa8)
#define QSERDES_RX_RX_HIGHZ_HIGHRATE (0x1000 + 0xac)
#define QSERDES_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET (0x1000 + 0xb0)
#define QSERDES_RX_DFE_1 (0x1000 + 0xb4)
#define QSERDES_RX_DFE_2 (0x1000 + 0xb8)
#define QSERDES_RX_DFE_3 (0x1000 + 0xbc)
#define QSERDES_RX_DFE_4 (0x1000 + 0xc0)
#define QSERDES_RX_TX_ADAPT_PRE_THRESH1 (0x1000 + 0xc4)
#define QSERDES_RX_TX_ADAPT_PRE_THRESH2 (0x1000 + 0xc8)
#define QSERDES_RX_TX_ADAPT_POST_THRESH (0x1000 + 0xcc)
#define QSERDES_RX_TX_ADAPT_MAIN_THRESH (0x1000 + 0xd0)
#define QSERDES_RX_VGA_CAL_CNTRL1 (0x1000 + 0xd4)
#define QSERDES_RX_VGA_CAL_CNTRL2 (0x1000 + 0xd8)
#define QSERDES_RX_GM_CAL (0x1000 + 0xdc)
#define QSERDES_RX_RX_VGA_GAIN2_LSB (0x1000 + 0xe0)
#define QSERDES_RX_RX_VGA_GAIN2_MSB (0x1000 + 0xe4)
#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL1 (0x1000 + 0xe8)
#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 (0x1000 + 0xec)
#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 (0x1000 + 0xf0)
#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 (0x1000 + 0xf4)
#define QSERDES_RX_RX_IDAC_TSETTLE_LOW (0x1000 + 0xf8)
#define QSERDES_RX_RX_IDAC_TSETTLE_HIGH (0x1000 + 0xfc)
#define QSERDES_RX_RX_IDAC_MEASURE_TIME (0x1000 + 0x100)
#define QSERDES_RX_RX_IDAC_ACCUMULATOR (0x1000 + 0x104)
#define QSERDES_RX_RX_EQ_OFFSET_LSB (0x1000 + 0x108)
#define QSERDES_RX_RX_EQ_OFFSET_MSB (0x1000 + 0x10c)
#define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 (0x1000 + 0x110)
#define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 (0x1000 + 0x114)
#define QSERDES_RX_SIGDET_ENABLES (0x1000 + 0x118)
#define QSERDES_RX_SIGDET_CNTRL (0x1000 + 0x11c)
#define QSERDES_RX_SIGDET_LVL (0x1000 + 0x120)
#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL (0x1000 + 0x124)
#define QSERDES_RX_RX_BAND (0x1000 + 0x128)
#define QSERDES_RX_CDR_FREEZE_UP_DN (0x1000 + 0x12c)
#define QSERDES_RX_CDR_RESET_OVERRIDE (0x1000 + 0x130)
#define QSERDES_RX_RX_INTERFACE_MODE (0x1000 + 0x134)
#define QSERDES_RX_JITTER_GEN_MODE (0x1000 + 0x138)
#define QSERDES_RX_SJ_AMP1 (0x1000 + 0x13c)
#define QSERDES_RX_SJ_AMP2 (0x1000 + 0x140)
#define QSERDES_RX_SJ_PER1 (0x1000 + 0x144)
#define QSERDES_RX_SJ_PER2 (0x1000 + 0x148)
#define QSERDES_RX_PPM_OFFSET1 (0x1000 + 0x14c)
#define QSERDES_RX_PPM_OFFSET2 (0x1000 + 0x150)
#define QSERDES_RX_SIGN_PPM_PERIOD1 (0x1000 + 0x154)
#define QSERDES_RX_SIGN_PPM_PERIOD2 (0x1000 + 0x158)
#define QSERDES_RX_RX_MODE_00_LOW (0x1000 + 0x15c)
#define QSERDES_RX_RX_MODE_00_HIGH (0x1000 + 0x160)
#define QSERDES_RX_RX_MODE_00_HIGH2 (0x1000 + 0x164)
#define QSERDES_RX_RX_MODE_00_HIGH3 (0x1000 + 0x168)
#define QSERDES_RX_RX_MODE_00_HIGH4 (0x1000 + 0x16c)
#define QSERDES_RX_RX_MODE_01_LOW (0x1000 + 0x170)
#define QSERDES_RX_RX_MODE_01_HIGH (0x1000 + 0x174)
#define QSERDES_RX_RX_MODE_01_HIGH2 (0x1000 + 0x178)
#define QSERDES_RX_RX_MODE_01_HIGH3 (0x1000 + 0x17c)
#define QSERDES_RX_RX_MODE_01_HIGH4 (0x1000 + 0x180)
#define QSERDES_RX_RX_MODE_10_LOW (0x1000 + 0x184)
#define QSERDES_RX_RX_MODE_10_HIGH (0x1000 + 0x188)
#define QSERDES_RX_RX_MODE_10_HIGH2 (0x1000 + 0x18c)
#define QSERDES_RX_RX_MODE_10_HIGH3 (0x1000 + 0x190)
#define QSERDES_RX_RX_MODE_10_HIGH4 (0x1000 + 0x194)
#define QSERDES_RX_PHPRE_CTRL (0x1000 + 0x198)
#define QSERDES_RX_PHPRE_INITVAL (0x1000 + 0x19c)
#define QSERDES_RX_DFE_EN_TIMER (0x1000 + 0x1a0)
#define QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET (0x1000 + 0x1a4)
#define QSERDES_RX_DCC_CTRL1 (0x1000 + 0x1a8)
#define QSERDES_RX_DCC_CTRL2 (0x1000 + 0x1ac)
#define QSERDES_RX_VTH_CODE (0x1000 + 0x1b0)
#define QSERDES_RX_VTH_MIN_THRESH (0x1000 + 0x1b4)
#define QSERDES_RX_VTH_MAX_THRESH (0x1000 + 0x1b8)
#define QSERDES_RX_ALOG_OBSV_BUS_CTRL_1 (0x1000 + 0x1bc)
#define QSERDES_RX_PI_CTRL1 (0x1000 + 0x1c0)
#define QSERDES_RX_PI_CTRL2 (0x1000 + 0x1c4)
#define QSERDES_RX_PI_QUAD (0x1000 + 0x1c8)
#define QSERDES_RX_IDATA1 (0x1000 + 0x1cc)
#define QSERDES_RX_IDATA2 (0x1000 + 0x1d0)
#define QSERDES_RX_AUX_DATA1 (0x1000 + 0x1d4)
#define QSERDES_RX_AUX_DATA2 (0x1000 + 0x1d8)
#define QSERDES_RX_RX_SIGDET_AND_CDR_FALSE_LOCK_STATUS (0x1000 + 0x1dc)
#define QSERDES_RX_ALOG_OBSV_BUS_STATUS_1 (0x1000 + 0x1e0)
#define QSERDES_RX_SIGDET_CAL_CTRL1 (0x1000 + 0x1e4)
#define QSERDES_RX_SIGDET_CAL_CTRL2_AND_CDR_LOCK_EDGE (0x1000 + 0x1e8)
#define QSERDES_RX_CDR_LOCK_ON_EDGE_DURATION (0x1000 + 0x1ec)
#define QSERDES_RX_CDR_LOCK_ON_EDGE_THRESH (0x1000 + 0x1f0)
#define QSERDES_RX_RX_ADAPTOR_CNTRL (0x1000 + 0x1f4)
#define QSERDES_RX_SIGDET_CAL_TRIM (0x1000 + 0x1f8)
#define QSERDES_RX_CAL_POST_WRAP (0x1000 + 0x1fc)
/* Module: USB3_UNI_PHY_PCIE_USB3_UNI_PCS_USB3_PCIE_USB3_UNI_PCS_USB3_PCIE_USB3_UNI_PCS_USB3 */
#define PCIE_USB3_UNI_PCS_USB3_POWER_STATE_CONFIG1 (0x1200 + 0x0)
#define PCIE_USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_STATUS (0x1200 + 0x4)
#define PCIE_USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL (0x1200 + 0x8)
#define PCIE_USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL2 (0x1200 + 0xc)
#define PCIE_USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS (0x1200 + 0x10)
#define PCIE_USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR (0x1200 + 0x14)
#define PCIE_USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL (0x1200 + 0x18)
#define PCIE_USB3_UNI_PCS_USB3_LFPS_TX_ECSTART (0x1200 + 0x1c)
#define PCIE_USB3_UNI_PCS_USB3_LFPS_PER_TIMER_VAL (0x1200 + 0x20)
#define PCIE_USB3_UNI_PCS_USB3_LFPS_TX_END_CNT_U3_START (0x1200 + 0x24)
#define PCIE_USB3_UNI_PCS_USB3_LFPS_CONFIG1 (0x1200 + 0x28)
#define PCIE_USB3_UNI_PCS_USB3_RXEQTRAINING_LOCK_TIME (0x1200 + 0x2c)
#define PCIE_USB3_UNI_PCS_USB3_RXEQTRAINING_WAIT_TIME (0x1200 + 0x30)
#define PCIE_USB3_UNI_PCS_USB3_RXEQTRAINING_CTLE_TIME (0x1200 + 0x34)
#define PCIE_USB3_UNI_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 (0x1200 + 0x38)
#define PCIE_USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 (0x1200 + 0x3c)
#define PCIE_USB3_UNI_PCS_USB3_RCVR_DTCT_DLY_U3_L (0x1200 + 0x40)
#define PCIE_USB3_UNI_PCS_USB3_RCVR_DTCT_DLY_U3_H (0x1200 + 0x44)
#define PCIE_USB3_UNI_PCS_USB3_ARCVR_DTCT_EN_PERIOD (0x1200 + 0x48)
#define PCIE_USB3_UNI_PCS_USB3_ARCVR_DTCT_CM_DLY (0x1200 + 0x4c)
#define PCIE_USB3_UNI_PCS_USB3_TXONESZEROS_RUN_LENGTH (0x1200 + 0x50)
#define PCIE_USB3_UNI_PCS_USB3_ALFPS_DEGLITCH_VAL (0x1200 + 0x54)
#define PCIE_USB3_UNI_PCS_USB3_SIGDET_STARTUP_TIMER_VAL (0x1200 + 0x58)
#define PCIE_USB3_UNI_PCS_USB3_TEST_CONTROL (0x1200 + 0x5c)
#define PCIE_USB3_UNI_PCS_USB3_RXTERMINATION_DLY_SEL (0x1200 + 0x60)
#define PCIE_USB3_UNI_PCS_USB3_POWER_STATE_CONFIG2 (0x1200 + 0x64)
#define PCIE_USB3_UNI_PCS_USB3_POWER_STATE_CONFIG3 (0x1200 + 0x68)
#define PCIE_USB3_UNI_PCS_USB3_POWER_STATE_CONFIG4 (0x1200 + 0x6c)
#endif /* _DT_BINDINGS_PHY_QCOM_4NM_QMP_UNI_USB_H */

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_PHY_QCOM_5NM_QMP_COMBO_USB_H
#define _DT_BINDINGS_PHY_QCOM_5NM_QMP_COMBO_USB_H
/* USB3-DP Combo PHY register offsets */
/* Module: USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM */
#define USB3_DP_COM_PHY_MODE_CTRL 0x0000
#define USB3_DP_COM_SW_RESET 0x0004
#define USB3_DP_COM_POWER_DOWN_CTRL 0x0008
#define USB3_DP_COM_SWI_CTRL 0x000C
#define USB3_DP_COM_TYPEC_CTRL 0x0010
#define USB3_DP_COM_TYPEC_PWRDN_CTRL 0x0014
#define USB3_DP_COM_DP_BIST_CFG_0 0x0018
#define USB3_DP_COM_RESET_OVRD_CTRL 0x001C
#define USB3_DP_COM_DBG_CLK_MUX_CTRL 0x0020
#define USB3_DP_COM_TYPEC_STATUS 0x0024
#define USB3_DP_COM_PLACEHOLDER_STATUS 0x0028
#define USB3_DP_COM_REVISION_ID0 0x002C
#define USB3_DP_COM_REVISION_ID1 0x0030
#define USB3_DP_COM_REVISION_ID2 0x0034
#define USB3_DP_COM_REVISION_ID3 0x0038
/* Module: USB3_DP_PHY_USB3_DP_DBGINT_USB3_DP_DBGINT_USB3_PCS_DEBUG_INT */
#define USB3_DP_DBGINT_INTGEN_STATUS1 0x0200
#define USB3_DP_DBGINT_INTGEN_STATUS2 0x0204
#define USB3_DP_DBGINT_CONFIG1 0x0208
#define USB3_DP_DBGINT_SIGNALBLK1_CONFIG1 0x020C
#define USB3_DP_DBGINT_SIGNALBLK1_CONFIG2 0x0210
#define USB3_DP_DBGINT_SIGNALBLK1_CONFIG3 0x0214
#define USB3_DP_DBGINT_SIGNALBLK1_CONFIG4 0x0218
#define USB3_DP_DBGINT_SIGNALBLK1_CONFIG5 0x021C
#define USB3_DP_DBGINT_SIGNALBLK2_CONFIG1 0x0220
#define USB3_DP_DBGINT_SIGNALBLK2_CONFIG2 0x0224
#define USB3_DP_DBGINT_SIGNALBLK2_CONFIG3 0x0228
#define USB3_DP_DBGINT_SIGNALBLK2_CONFIG4 0x022C
#define USB3_DP_DBGINT_SIGNALBLK2_CONFIG5 0x0230
#define USB3_DP_DBGINT_STRINGBLK1_CONFIG1 0x0234
#define USB3_DP_DBGINT_STRINGBLK1_CONFIG2 0x0238
#define USB3_DP_DBGINT_STRINGBLK1_CONFIG3 0x023C
#define USB3_DP_DBGINT_STRINGBLK1_CONFIG4 0x0240
#define USB3_DP_DBGINT_STRINGBLK1_CONFIG5 0x0244
#define USB3_DP_DBGINT_STRINGBLK2_CONFIG1 0x0248
#define USB3_DP_DBGINT_STRINGBLK2_CONFIG2 0x024C
#define USB3_DP_DBGINT_STRINGBLK2_CONFIG3 0x0250
#define USB3_DP_DBGINT_STRINGBLK2_CONFIG4 0x0254
#define USB3_DP_DBGINT_STRINGBLK2_CONFIG5 0x0258
/* Module: USB3_DP_PHY_USB3_QSERDES_COM_USB3_QSERDES_COM_USB3_DP_QMP_PLL */
#define USB3_DP_QSERDES_COM_ATB_SEL1 0x1000
#define USB3_DP_QSERDES_COM_ATB_SEL2 0x1004
#define USB3_DP_QSERDES_COM_FREQ_UPDATE 0x1008
#define USB3_DP_QSERDES_COM_BG_TIMER 0x100C
#define USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x1010
#define USB3_DP_QSERDES_COM_SSC_ADJ_PER1 0x1014
#define USB3_DP_QSERDES_COM_SSC_ADJ_PER2 0x1018
#define USB3_DP_QSERDES_COM_SSC_PER1 0x101C
#define USB3_DP_QSERDES_COM_SSC_PER2 0x1020
#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0x1024
#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x1028
#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE0 0x102C
#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0x1030
#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x1034
#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE1 0x1038
#define USB3_DP_QSERDES_COM_POST_DIV 0x103C
#define USB3_DP_QSERDES_COM_POST_DIV_MUX 0x1040
#define USB3_DP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x1044
#define USB3_DP_QSERDES_COM_CLK_ENABLE1 0x1048
#define USB3_DP_QSERDES_COM_SYS_CLK_CTRL 0x104C
#define USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x1050
#define USB3_DP_QSERDES_COM_PLL_EN 0x1054
#define USB3_DP_QSERDES_COM_PLL_IVCO 0x1058
#define USB3_DP_QSERDES_COM_CMN_IETRIM 0x105C
#define USB3_DP_QSERDES_COM_CMN_IPTRIM 0x1060
#define USB3_DP_QSERDES_COM_EP_CLOCK_DETECT_CTRL 0x1064
#define USB3_DP_QSERDES_COM_SYSCLK_DET_COMP_STATUS 0x1068
#define USB3_DP_QSERDES_COM_CLK_EP_DIV_MODE0 0x106C
#define USB3_DP_QSERDES_COM_CLK_EP_DIV_MODE1 0x1070
#define USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x1074
#define USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x1078
#define USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x107C
#define USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x1080
#define USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x1084
#define USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x1088
#define USB3_DP_QSERDES_COM_PLL_CNTRL 0x108C
#define USB3_DP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x1090
#define USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1094
#define USB3_DP_QSERDES_COM_CML_SYSCLK_SEL 0x1098
#define USB3_DP_QSERDES_COM_RESETSM_CNTRL 0x109C
#define USB3_DP_QSERDES_COM_RESETSM_CNTRL2 0x10A0
#define USB3_DP_QSERDES_COM_LOCK_CMP_EN 0x10A4
#define USB3_DP_QSERDES_COM_LOCK_CMP_CFG 0x10A8
#define USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x10AC
#define USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x10B0
#define USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x10B4
#define USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x10B8
#define USB3_DP_QSERDES_COM_DEC_START_MODE0 0x10BC
#define USB3_DP_QSERDES_COM_DEC_START_MSB_MODE0 0x10C0
#define USB3_DP_QSERDES_COM_DEC_START_MODE1 0x10C4
#define USB3_DP_QSERDES_COM_DEC_START_MSB_MODE1 0x10C8
#define USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0x10CC
#define USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0x10D0
#define USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x10D4
#define USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0x10D8
#define USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0x10DC
#define USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x10E0
#define USB3_DP_QSERDES_COM_INTEGLOOP_INITVAL 0x10E4
#define USB3_DP_QSERDES_COM_INTEGLOOP_EN 0x10E8
#define USB3_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x10EC
#define USB3_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10F0
#define USB3_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x10F4
#define USB3_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x10F8
#define USB3_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0 0x10FC
#define USB3_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1 0x1100
#define USB3_DP_QSERDES_COM_VCOCAL_DEADMAN_CTRL 0x1104
#define USB3_DP_QSERDES_COM_VCO_TUNE_CTRL 0x1108
#define USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x110C
#define USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x1110
#define USB3_DP_QSERDES_COM_VCO_TUNE2_MODE0 0x1114
#define USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x1118
#define USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x111C
#define USB3_DP_QSERDES_COM_VCO_TUNE_INITVAL1 0x1120
#define USB3_DP_QSERDES_COM_VCO_TUNE_INITVAL2 0x1124
#define USB3_DP_QSERDES_COM_VCO_TUNE_MINVAL1 0x1128
#define USB3_DP_QSERDES_COM_VCO_TUNE_MINVAL2 0x112C
#define USB3_DP_QSERDES_COM_VCO_TUNE_MAXVAL1 0x1130
#define USB3_DP_QSERDES_COM_VCO_TUNE_MAXVAL2 0x1134
#define USB3_DP_QSERDES_COM_VCO_TUNE_TIMER1 0x1138
#define USB3_DP_QSERDES_COM_VCO_TUNE_TIMER2 0x113C
#define USB3_DP_QSERDES_COM_CMN_STATUS 0x1140
#define USB3_DP_QSERDES_COM_RESET_SM_STATUS 0x1144
#define USB3_DP_QSERDES_COM_RESTRIM_CODE_STATUS 0x1148
#define USB3_DP_QSERDES_COM_PLLCAL_CODE1_STATUS 0x114C
#define USB3_DP_QSERDES_COM_PLLCAL_CODE2_STATUS 0x1150
#define USB3_DP_QSERDES_COM_CLK_SELECT 0x1154
#define USB3_DP_QSERDES_COM_HSCLK_SEL 0x1158
#define USB3_DP_QSERDES_COM_HSCLK_HS_SWITCH_SEL 0x115C
#define USB3_DP_QSERDES_COM_INTEGLOOP_BINCODE_STATUS 0x1160
#define USB3_DP_QSERDES_COM_PLL_ANALOG 0x1164
#define USB3_DP_QSERDES_COM_CORECLK_DIV_MODE0 0x1168
#define USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x116C
#define USB3_DP_QSERDES_COM_SW_RESET 0x1170
#define USB3_DP_QSERDES_COM_CORE_CLK_EN 0x1174
#define USB3_DP_QSERDES_COM_C_READY_STATUS 0x1178
#define USB3_DP_QSERDES_COM_CMN_CONFIG 0x117C
#define USB3_DP_QSERDES_COM_CMN_RATE_OVERRIDE 0x1180
#define USB3_DP_QSERDES_COM_SVS_MODE_CLK_SEL 0x1184
#define USB3_DP_QSERDES_COM_DEBUG_BUS0 0x1188
#define USB3_DP_QSERDES_COM_DEBUG_BUS1 0x118C
#define USB3_DP_QSERDES_COM_DEBUG_BUS2 0x1190
#define USB3_DP_QSERDES_COM_DEBUG_BUS3 0x1194
#define USB3_DP_QSERDES_COM_DEBUG_BUS_SEL 0x1198
#define USB3_DP_QSERDES_COM_CMN_MISC1 0x119C
#define USB3_DP_QSERDES_COM_CMN_MODE 0x11A0
#define USB3_DP_QSERDES_COM_CMN_MODE_CONTD 0x11A4
#define USB3_DP_QSERDES_COM_VCO_DC_LEVEL_CTRL 0x11A8
#define USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x11AC
#define USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x11B0
#define USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x11B4
#define USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x11B8
#define USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11BC
#define USB3_DP_QSERDES_COM_RESERVED_1 0x11C0
#define USB3_DP_QSERDES_COM_MODE_OPERATION_STATUS 0x11C4
/* Module: USB3_DP_PHY_USB3_QSERDES_TXA_USB3_QSERDES_TXA_USB3_DP_QMP_TX */
#define USB3_DP_QSERDES_TXA_BIST_MODE_LANENO 0x1200
#define USB3_DP_QSERDES_TXA_BIST_INVERT 0x1204
#define USB3_DP_QSERDES_TXA_CLKBUF_ENABLE 0x1208
#define USB3_DP_QSERDES_TXA_TX_EMP_POST1_LVL 0x120C
#define USB3_DP_QSERDES_TXA_TX_IDLE_LVL_LARGE_AMP 0x1210
#define USB3_DP_QSERDES_TXA_TX_DRV_LVL 0x1214
#define USB3_DP_QSERDES_TXA_TX_DRV_LVL_OFFSET 0x1218
#define USB3_DP_QSERDES_TXA_RESET_TSYNC_EN 0x121C
#define USB3_DP_QSERDES_TXA_PRE_STALL_LDO_BOOST_EN 0x1220
#define USB3_DP_QSERDES_TXA_TX_BAND 0x1224
#define USB3_DP_QSERDES_TXA_SLEW_CNTL 0x1228
#define USB3_DP_QSERDES_TXA_INTERFACE_SELECT 0x122C
#define USB3_DP_QSERDES_TXA_LPB_EN 0x1230
#define USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x1234
#define USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x1238
#define USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x123C
#define USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x1240
#define USB3_DP_QSERDES_TXA_PERL_LENGTH1 0x1244
#define USB3_DP_QSERDES_TXA_PERL_LENGTH2 0x1248
#define USB3_DP_QSERDES_TXA_SERDES_BYP_EN_OUT 0x124C
#define USB3_DP_QSERDES_TXA_DEBUG_BUS_SEL 0x1250
#define USB3_DP_QSERDES_TXA_TRANSCEIVER_BIAS_EN 0x1254
#define USB3_DP_QSERDES_TXA_HIGHZ_DRVR_EN 0x1258
#define USB3_DP_QSERDES_TXA_TX_POL_INV 0x125C
#define USB3_DP_QSERDES_TXA_PARRATE_REC_DETECT_IDLE_EN 0x1260
#define USB3_DP_QSERDES_TXA_BIST_PATTERN1 0x1264
#define USB3_DP_QSERDES_TXA_BIST_PATTERN2 0x1268
#define USB3_DP_QSERDES_TXA_BIST_PATTERN3 0x126C
#define USB3_DP_QSERDES_TXA_BIST_PATTERN4 0x1270
#define USB3_DP_QSERDES_TXA_BIST_PATTERN5 0x1274
#define USB3_DP_QSERDES_TXA_BIST_PATTERN6 0x1278
#define USB3_DP_QSERDES_TXA_BIST_PATTERN7 0x127C
#define USB3_DP_QSERDES_TXA_BIST_PATTERN8 0x1280
#define USB3_DP_QSERDES_TXA_LANE_MODE_1 0x1284
#define USB3_DP_QSERDES_TXA_LANE_MODE_2 0x1288
#define USB3_DP_QSERDES_TXA_LANE_MODE_3 0x128C
#define USB3_DP_QSERDES_TXA_LANE_MODE_4 0x1290
#define USB3_DP_QSERDES_TXA_LANE_MODE_5 0x1294
#define USB3_DP_QSERDES_TXA_ATB_SEL1 0x1298
#define USB3_DP_QSERDES_TXA_ATB_SEL2 0x129C
#define USB3_DP_QSERDES_TXA_RCV_DETECT_LVL 0x12A0
#define USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12A4
#define USB3_DP_QSERDES_TXA_PRBS_SEED1 0x12A8
#define USB3_DP_QSERDES_TXA_PRBS_SEED2 0x12AC
#define USB3_DP_QSERDES_TXA_PRBS_SEED3 0x12B0
#define USB3_DP_QSERDES_TXA_PRBS_SEED4 0x12B4
#define USB3_DP_QSERDES_TXA_RESET_GEN 0x12B8
#define USB3_DP_QSERDES_TXA_RESET_GEN_MUXES 0x12BC
#define USB3_DP_QSERDES_TXA_TRAN_DRVR_EMP_EN 0x12C0
#define USB3_DP_QSERDES_TXA_TX_INTERFACE_MODE 0x12C4
#define USB3_DP_QSERDES_TXA_VMODE_CTRL1 0x12C8
#define USB3_DP_QSERDES_TXA_ALOG_OBSV_BUS_CTRL_1 0x12CC
#define USB3_DP_QSERDES_TXA_BIST_STATUS 0x12D0
#define USB3_DP_QSERDES_TXA_BIST_ERROR_COUNT1 0x12D4
#define USB3_DP_QSERDES_TXA_BIST_ERROR_COUNT2 0x12D8
#define USB3_DP_QSERDES_TXA_ALOG_OBSV_BUS_STATUS_1 0x12DC
#define USB3_DP_QSERDES_TXA_LANE_DIG_CONFIG 0x12E0
#define USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x12E4
#define USB3_DP_QSERDES_TXA_PRE_EMPH 0x12E8
#define USB3_DP_QSERDES_TXA_SW_RESET 0x12EC
#define USB3_DP_QSERDES_TXA_DCC_OFFSET 0x12F0
#define USB3_DP_QSERDES_TXA_DCC_CMUX_POSTCAL_OFFSET 0x12F4
#define USB3_DP_QSERDES_TXA_DCC_CMUX_CAL_CTRL1 0x12F8
#define USB3_DP_QSERDES_TXA_DCC_CMUX_CAL_CTRL2 0x12FC
#define USB3_DP_QSERDES_TXA_DIG_BKUP_CTRL 0x1300
#define USB3_DP_QSERDES_TXA_DEBUG_BUS0 0x1304
#define USB3_DP_QSERDES_TXA_DEBUG_BUS1 0x1308
#define USB3_DP_QSERDES_TXA_DEBUG_BUS2 0x130C
#define USB3_DP_QSERDES_TXA_DEBUG_BUS3 0x1310
#define USB3_DP_QSERDES_TXA_READ_EQCODE 0x1314
#define USB3_DP_QSERDES_TXA_READ_OFFSETCODE 0x1318
#define USB3_DP_QSERDES_TXA_IA_ERROR_COUNTER_LOW 0x131C
#define USB3_DP_QSERDES_TXA_IA_ERROR_COUNTER_HIGH 0x1320
#define USB3_DP_QSERDES_TXA_VGA_READ_CODE 0x1324
#define USB3_DP_QSERDES_TXA_VTH_READ_CODE 0x1328
#define USB3_DP_QSERDES_TXA_DFE_TAP1_READ_CODE 0x132C
#define USB3_DP_QSERDES_TXA_DFE_TAP2_READ_CODE 0x1330
#define USB3_DP_QSERDES_TXA_IDAC_STATUS_I 0x1334
#define USB3_DP_QSERDES_TXA_IDAC_STATUS_IBAR 0x1338
#define USB3_DP_QSERDES_TXA_IDAC_STATUS_Q 0x133C
#define USB3_DP_QSERDES_TXA_IDAC_STATUS_QBAR 0x1340
#define USB3_DP_QSERDES_TXA_IDAC_STATUS_A 0x1344
#define USB3_DP_QSERDES_TXA_IDAC_STATUS_ABAR 0x1348
#define USB3_DP_QSERDES_TXA_IDAC_STATUS_SM_ON 0x134C
#define USB3_DP_QSERDES_TXA_IDAC_STATUS_CAL_DONE 0x1350
#define USB3_DP_QSERDES_TXA_IDAC_STATUS_SIGNERROR 0x1354
#define USB3_DP_QSERDES_TXA_DCC_CAL_STATUS 0x1358
#define USB3_DP_QSERDES_TXA_DCC_READ_CODE_STATUS 0x135C
/* Module: USB3_DP_PHY_USB3_QSERDES_RXA_USB3_QSERDES_RXA_USB3_DP_QMP_RX */
#define USB3_DP_QSERDES_RXA_UCDR_FO_GAIN_HALF 0x1400
#define USB3_DP_QSERDES_RXA_UCDR_FO_GAIN_QUARTER 0x1404
#define USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x1408
#define USB3_DP_QSERDES_RXA_UCDR_SO_GAIN_HALF 0x140C
#define USB3_DP_QSERDES_RXA_UCDR_SO_GAIN_QUARTER 0x1410
#define USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x1414
#define USB3_DP_QSERDES_RXA_UCDR_SVS_FO_GAIN_HALF 0x1418
#define USB3_DP_QSERDES_RXA_UCDR_SVS_FO_GAIN_QUARTER 0x141C
#define USB3_DP_QSERDES_RXA_UCDR_SVS_FO_GAIN 0x1420
#define USB3_DP_QSERDES_RXA_UCDR_SVS_SO_GAIN_HALF 0x1424
#define USB3_DP_QSERDES_RXA_UCDR_SVS_SO_GAIN_QUARTER 0x1428
#define USB3_DP_QSERDES_RXA_UCDR_SVS_SO_GAIN 0x142C
#define USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x1430
#define USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x1434
#define USB3_DP_QSERDES_RXA_UCDR_FO_TO_SO_DELAY 0x1438
#define USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0x143C
#define USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x1440
#define USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x1444
#define USB3_DP_QSERDES_RXA_UCDR_PI_CTRL2 0x1448
#define USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x144C
#define USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x1450
#define USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x1454
#define USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x1458
#define USB3_DP_QSERDES_RXA_AUX_CONTROL 0x145C
#define USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0x1460
#define USB3_DP_QSERDES_RXA_RCLK_AUXDATA_SEL 0x1464
#define USB3_DP_QSERDES_RXA_AC_JTAG_ENABLE 0x1468
#define USB3_DP_QSERDES_RXA_AC_JTAG_INITP 0x146C
#define USB3_DP_QSERDES_RXA_AC_JTAG_INITN 0x1470
#define USB3_DP_QSERDES_RXA_AC_JTAG_LVL 0x1474
#define USB3_DP_QSERDES_RXA_AC_JTAG_MODE 0x1478
#define USB3_DP_QSERDES_RXA_AC_JTAG_RESET 0x147C
#define USB3_DP_QSERDES_RXA_RX_TERM_BW 0x1480
#define USB3_DP_QSERDES_RXA_RX_RCVR_IQ_EN 0x1484
#define USB3_DP_QSERDES_RXA_RX_IDAC_I_DC_OFFSETS 0x1488
#define USB3_DP_QSERDES_RXA_RX_IDAC_IBAR_DC_OFFSETS 0x148C
#define USB3_DP_QSERDES_RXA_RX_IDAC_Q_DC_OFFSETS 0x1490
#define USB3_DP_QSERDES_RXA_RX_IDAC_QBAR_DC_OFFSETS 0x1494
#define USB3_DP_QSERDES_RXA_RX_IDAC_A_DC_OFFSETS 0x1498
#define USB3_DP_QSERDES_RXA_RX_IDAC_ABAR_DC_OFFSETS 0x149C
#define USB3_DP_QSERDES_RXA_RX_IDAC_EN 0x14A0
#define USB3_DP_QSERDES_RXA_RX_IDAC_ENABLES 0x14A4
#define USB3_DP_QSERDES_RXA_RX_IDAC_SIGN 0x14A8
#define USB3_DP_QSERDES_RXA_RX_HIGHZ_HIGHRATE 0x14AC
#define USB3_DP_QSERDES_RXA_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x14B0
#define USB3_DP_QSERDES_RXA_DFE_1 0x14B4
#define USB3_DP_QSERDES_RXA_DFE_2 0x14B8
#define USB3_DP_QSERDES_RXA_DFE_3 0x14BC
#define USB3_DP_QSERDES_RXA_DFE_4 0x14C0
#define USB3_DP_QSERDES_RXA_TX_ADAPT_PRE_THRESH1 0x14C4
#define USB3_DP_QSERDES_RXA_TX_ADAPT_PRE_THRESH2 0x14C8
#define USB3_DP_QSERDES_RXA_TX_ADAPT_POST_THRESH 0x14CC
#define USB3_DP_QSERDES_RXA_TX_ADAPT_MAIN_THRESH 0x14D0
#define USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x14D4
#define USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x14D8
#define USB3_DP_QSERDES_RXA_GM_CAL 0x14DC
#define USB3_DP_QSERDES_RXA_RX_VGA_GAIN2_LSB 0x14E0
#define USB3_DP_QSERDES_RXA_RX_VGA_GAIN2_MSB 0x14E4
#define USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL1 0x14E8
#define USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x14EC
#define USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x14F0
#define USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x14F4
#define USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0x14F8
#define USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x14FC
#define USB3_DP_QSERDES_RXA_RX_IDAC_MEASURE_TIME 0x1500
#define USB3_DP_QSERDES_RXA_RX_IDAC_ACCUMULATOR 0x1504
#define USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_LSB 0x1508
#define USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_MSB 0x150C
#define USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1510
#define USB3_DP_QSERDES_RXA_RX_OFFSET_ADAPTOR_CNTRL2 0x1514
#define USB3_DP_QSERDES_RXA_SIGDET_ENABLES 0x1518
#define USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x151C
#define USB3_DP_QSERDES_RXA_SIGDET_LVL 0x1520
#define USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x1524
#define USB3_DP_QSERDES_RXA_RX_BAND 0x1528
#define USB3_DP_QSERDES_RXA_CDR_FREEZE_UP_DN 0x152C
#define USB3_DP_QSERDES_RXA_CDR_RESET_OVERRIDE 0x1530
#define USB3_DP_QSERDES_RXA_RX_INTERFACE_MODE 0x1534
#define USB3_DP_QSERDES_RXA_JITTER_GEN_MODE 0x1538
#define USB3_DP_QSERDES_RXA_SJ_AMP1 0x153C
#define USB3_DP_QSERDES_RXA_SJ_AMP2 0x1540
#define USB3_DP_QSERDES_RXA_SJ_PER1 0x1544
#define USB3_DP_QSERDES_RXA_SJ_PER2 0x1548
#define USB3_DP_QSERDES_RXA_PPM_OFFSET1 0x154C
#define USB3_DP_QSERDES_RXA_PPM_OFFSET2 0x1550
#define USB3_DP_QSERDES_RXA_SIGN_PPM_PERIOD1 0x1554
#define USB3_DP_QSERDES_RXA_SIGN_PPM_PERIOD2 0x1558
#define USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0x155C
#define USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x1560
#define USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0x1564
#define USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x1568
#define USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0x156C
#define USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0x1570
#define USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0x1574
#define USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0x1578
#define USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x157C
#define USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0x1580
#define USB3_DP_QSERDES_RXA_RX_MODE_10_LOW 0x1584
#define USB3_DP_QSERDES_RXA_RX_MODE_10_HIGH 0x1588
#define USB3_DP_QSERDES_RXA_RX_MODE_10_HIGH2 0x158C
#define USB3_DP_QSERDES_RXA_RX_MODE_10_HIGH3 0x1590
#define USB3_DP_QSERDES_RXA_RX_MODE_10_HIGH4 0x1594
#define USB3_DP_QSERDES_RXA_PHPRE_CTRL 0x1598
#define USB3_DP_QSERDES_RXA_PHPRE_INITVAL 0x159C
#define USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x15A0
#define USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x15A4
#define USB3_DP_QSERDES_RXA_DCC_CTRL1 0x15A8
#define USB3_DP_QSERDES_RXA_DCC_CTRL2 0x15AC
#define USB3_DP_QSERDES_RXA_VTH_CODE 0x15B0
#define USB3_DP_QSERDES_RXA_VTH_MIN_THRESH 0x15B4
#define USB3_DP_QSERDES_RXA_VTH_MAX_THRESH 0x15B8
#define USB3_DP_QSERDES_RXA_ALOG_OBSV_BUS_CTRL_1 0x15BC
#define USB3_DP_QSERDES_RXA_PI_CTRL1 0x15C0
#define USB3_DP_QSERDES_RXA_PI_CTRL2 0x15C4
#define USB3_DP_QSERDES_RXA_PI_QUAD 0x15C8
#define USB3_DP_QSERDES_RXA_IDATA1 0x15CC
#define USB3_DP_QSERDES_RXA_IDATA2 0x15D0
#define USB3_DP_QSERDES_RXA_AUX_DATA1 0x15D4
#define USB3_DP_QSERDES_RXA_AUX_DATA2 0x15D8
#define USB3_DP_QSERDES_RXA_AC_JTAG_OUTP 0x15DC
#define USB3_DP_QSERDES_RXA_AC_JTAG_OUTN 0x15E0
#define USB3_DP_QSERDES_RXA_RX_SIGDET 0x15E4
#define USB3_DP_QSERDES_RXA_ALOG_OBSV_BUS_STATUS_1 0x15E8
/* Module: USB3_DP_PHY_USB3_QSERDES_TXB_USB3_QSERDES_TXB_USB3_DP_QMP_TX */
#define USB3_DP_QSERDES_TXB_BIST_MODE_LANENO 0x1600
#define USB3_DP_QSERDES_TXB_BIST_INVERT 0x1604
#define USB3_DP_QSERDES_TXB_CLKBUF_ENABLE 0x1608
#define USB3_DP_QSERDES_TXB_TX_EMP_POST1_LVL 0x160C
#define USB3_DP_QSERDES_TXB_TX_IDLE_LVL_LARGE_AMP 0x1610
#define USB3_DP_QSERDES_TXB_TX_DRV_LVL 0x1614
#define USB3_DP_QSERDES_TXB_TX_DRV_LVL_OFFSET 0x1618
#define USB3_DP_QSERDES_TXB_RESET_TSYNC_EN 0x161C
#define USB3_DP_QSERDES_TXB_PRE_STALL_LDO_BOOST_EN 0x1620
#define USB3_DP_QSERDES_TXB_TX_BAND 0x1624
#define USB3_DP_QSERDES_TXB_SLEW_CNTL 0x1628
#define USB3_DP_QSERDES_TXB_INTERFACE_SELECT 0x162C
#define USB3_DP_QSERDES_TXB_LPB_EN 0x1630
#define USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x1634
#define USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x1638
#define USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x163C
#define USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x1640
#define USB3_DP_QSERDES_TXB_PERL_LENGTH1 0x1644
#define USB3_DP_QSERDES_TXB_PERL_LENGTH2 0x1648
#define USB3_DP_QSERDES_TXB_SERDES_BYP_EN_OUT 0x164C
#define USB3_DP_QSERDES_TXB_DEBUG_BUS_SEL 0x1650
#define USB3_DP_QSERDES_TXB_TRANSCEIVER_BIAS_EN 0x1654
#define USB3_DP_QSERDES_TXB_HIGHZ_DRVR_EN 0x1658
#define USB3_DP_QSERDES_TXB_TX_POL_INV 0x165C
#define USB3_DP_QSERDES_TXB_PARRATE_REC_DETECT_IDLE_EN 0x1660
#define USB3_DP_QSERDES_TXB_BIST_PATTERN1 0x1664
#define USB3_DP_QSERDES_TXB_BIST_PATTERN2 0x1668
#define USB3_DP_QSERDES_TXB_BIST_PATTERN3 0x166C
#define USB3_DP_QSERDES_TXB_BIST_PATTERN4 0x1670
#define USB3_DP_QSERDES_TXB_BIST_PATTERN5 0x1674
#define USB3_DP_QSERDES_TXB_BIST_PATTERN6 0x1678
#define USB3_DP_QSERDES_TXB_BIST_PATTERN7 0x167C
#define USB3_DP_QSERDES_TXB_BIST_PATTERN8 0x1680
#define USB3_DP_QSERDES_TXB_LANE_MODE_1 0x1684
#define USB3_DP_QSERDES_TXB_LANE_MODE_2 0x1688
#define USB3_DP_QSERDES_TXB_LANE_MODE_3 0x168C
#define USB3_DP_QSERDES_TXB_LANE_MODE_4 0x1690
#define USB3_DP_QSERDES_TXB_LANE_MODE_5 0x1694
#define USB3_DP_QSERDES_TXB_ATB_SEL1 0x1698
#define USB3_DP_QSERDES_TXB_ATB_SEL2 0x169C
#define USB3_DP_QSERDES_TXB_RCV_DETECT_LVL 0x16A0
#define USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x16A4
#define USB3_DP_QSERDES_TXB_PRBS_SEED1 0x16A8
#define USB3_DP_QSERDES_TXB_PRBS_SEED2 0x16AC
#define USB3_DP_QSERDES_TXB_PRBS_SEED3 0x16B0
#define USB3_DP_QSERDES_TXB_PRBS_SEED4 0x16B4
#define USB3_DP_QSERDES_TXB_RESET_GEN 0x16B8
#define USB3_DP_QSERDES_TXB_RESET_GEN_MUXES 0x16BC
#define USB3_DP_QSERDES_TXB_TRAN_DRVR_EMP_EN 0x16C0
#define USB3_DP_QSERDES_TXB_TX_INTERFACE_MODE 0x16C4
#define USB3_DP_QSERDES_TXB_VMODE_CTRL1 0x16C8
#define USB3_DP_QSERDES_TXB_ALOG_OBSV_BUS_CTRL_1 0x16CC
#define USB3_DP_QSERDES_TXB_BIST_STATUS 0x16D0
#define USB3_DP_QSERDES_TXB_BIST_ERROR_COUNT1 0x16D4
#define USB3_DP_QSERDES_TXB_BIST_ERROR_COUNT2 0x16D8
#define USB3_DP_QSERDES_TXB_ALOG_OBSV_BUS_STATUS_1 0x16DC
#define USB3_DP_QSERDES_TXB_LANE_DIG_CONFIG 0x16E0
#define USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x16E4
#define USB3_DP_QSERDES_TXB_PRE_EMPH 0x16E8
#define USB3_DP_QSERDES_TXB_SW_RESET 0x16EC
#define USB3_DP_QSERDES_TXB_DCC_OFFSET 0x16F0
#define USB3_DP_QSERDES_TXB_DCC_CMUX_POSTCAL_OFFSET 0x16F4
#define USB3_DP_QSERDES_TXB_DCC_CMUX_CAL_CTRL1 0x16F8
#define USB3_DP_QSERDES_TXB_DCC_CMUX_CAL_CTRL2 0x16FC
#define USB3_DP_QSERDES_TXB_DIG_BKUP_CTRL 0x1700
#define USB3_DP_QSERDES_TXB_DEBUG_BUS0 0x1704
#define USB3_DP_QSERDES_TXB_DEBUG_BUS1 0x1708
#define USB3_DP_QSERDES_TXB_DEBUG_BUS2 0x170C
#define USB3_DP_QSERDES_TXB_DEBUG_BUS3 0x1710
#define USB3_DP_QSERDES_TXB_READ_EQCODE 0x1714
#define USB3_DP_QSERDES_TXB_READ_OFFSETCODE 0x1718
#define USB3_DP_QSERDES_TXB_IA_ERROR_COUNTER_LOW 0x171C
#define USB3_DP_QSERDES_TXB_IA_ERROR_COUNTER_HIGH 0x1720
#define USB3_DP_QSERDES_TXB_VGA_READ_CODE 0x1724
#define USB3_DP_QSERDES_TXB_VTH_READ_CODE 0x1728
#define USB3_DP_QSERDES_TXB_DFE_TAP1_READ_CODE 0x172C
#define USB3_DP_QSERDES_TXB_DFE_TAP2_READ_CODE 0x1730
#define USB3_DP_QSERDES_TXB_IDAC_STATUS_I 0x1734
#define USB3_DP_QSERDES_TXB_IDAC_STATUS_IBAR 0x1738
#define USB3_DP_QSERDES_TXB_IDAC_STATUS_Q 0x173C
#define USB3_DP_QSERDES_TXB_IDAC_STATUS_QBAR 0x1740
#define USB3_DP_QSERDES_TXB_IDAC_STATUS_A 0x1744
#define USB3_DP_QSERDES_TXB_IDAC_STATUS_ABAR 0x1748
#define USB3_DP_QSERDES_TXB_IDAC_STATUS_SM_ON 0x174C
#define USB3_DP_QSERDES_TXB_IDAC_STATUS_CAL_DONE 0x1750
#define USB3_DP_QSERDES_TXB_IDAC_STATUS_SIGNERROR 0x1754
#define USB3_DP_QSERDES_TXB_DCC_CAL_STATUS 0x1758
#define USB3_DP_QSERDES_TXB_DCC_READ_CODE_STATUS 0x175C
/* Module: USB3_DP_PHY_USB3_QSERDES_RXB_USB3_QSERDES_RXB_USB3_DP_QMP_RX */
#define USB3_DP_QSERDES_RXB_UCDR_FO_GAIN_HALF 0x1800
#define USB3_DP_QSERDES_RXB_UCDR_FO_GAIN_QUARTER 0x1804
#define USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x1808
#define USB3_DP_QSERDES_RXB_UCDR_SO_GAIN_HALF 0x180C
#define USB3_DP_QSERDES_RXB_UCDR_SO_GAIN_QUARTER 0x1810
#define USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x1814
#define USB3_DP_QSERDES_RXB_UCDR_SVS_FO_GAIN_HALF 0x1818
#define USB3_DP_QSERDES_RXB_UCDR_SVS_FO_GAIN_QUARTER 0x181C
#define USB3_DP_QSERDES_RXB_UCDR_SVS_FO_GAIN 0x1820
#define USB3_DP_QSERDES_RXB_UCDR_SVS_SO_GAIN_HALF 0x1824
#define USB3_DP_QSERDES_RXB_UCDR_SVS_SO_GAIN_QUARTER 0x1828
#define USB3_DP_QSERDES_RXB_UCDR_SVS_SO_GAIN 0x182C
#define USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x1830
#define USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x1834
#define USB3_DP_QSERDES_RXB_UCDR_FO_TO_SO_DELAY 0x1838
#define USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0x183C
#define USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x1840
#define USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x1844
#define USB3_DP_QSERDES_RXB_UCDR_PI_CTRL2 0x1848
#define USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x184C
#define USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x1850
#define USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x1854
#define USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x1858
#define USB3_DP_QSERDES_RXB_AUX_CONTROL 0x185C
#define USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0x1860
#define USB3_DP_QSERDES_RXB_RCLK_AUXDATA_SEL 0x1864
#define USB3_DP_QSERDES_RXB_AC_JTAG_ENABLE 0x1868
#define USB3_DP_QSERDES_RXB_AC_JTAG_INITP 0x186C
#define USB3_DP_QSERDES_RXB_AC_JTAG_INITN 0x1870
#define USB3_DP_QSERDES_RXB_AC_JTAG_LVL 0x1874
#define USB3_DP_QSERDES_RXB_AC_JTAG_MODE 0x1878
#define USB3_DP_QSERDES_RXB_AC_JTAG_RESET 0x187C
#define USB3_DP_QSERDES_RXB_RX_TERM_BW 0x1880
#define USB3_DP_QSERDES_RXB_RX_RCVR_IQ_EN 0x1884
#define USB3_DP_QSERDES_RXB_RX_IDAC_I_DC_OFFSETS 0x1888
#define USB3_DP_QSERDES_RXB_RX_IDAC_IBAR_DC_OFFSETS 0x188C
#define USB3_DP_QSERDES_RXB_RX_IDAC_Q_DC_OFFSETS 0x1890
#define USB3_DP_QSERDES_RXB_RX_IDAC_QBAR_DC_OFFSETS 0x1894
#define USB3_DP_QSERDES_RXB_RX_IDAC_A_DC_OFFSETS 0x1898
#define USB3_DP_QSERDES_RXB_RX_IDAC_ABAR_DC_OFFSETS 0x189C
#define USB3_DP_QSERDES_RXB_RX_IDAC_EN 0x18A0
#define USB3_DP_QSERDES_RXB_RX_IDAC_ENABLES 0x18A4
#define USB3_DP_QSERDES_RXB_RX_IDAC_SIGN 0x18A8
#define USB3_DP_QSERDES_RXB_RX_HIGHZ_HIGHRATE 0x18AC
#define USB3_DP_QSERDES_RXB_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x18B0
#define USB3_DP_QSERDES_RXB_DFE_1 0x18B4
#define USB3_DP_QSERDES_RXB_DFE_2 0x18B8
#define USB3_DP_QSERDES_RXB_DFE_3 0x18BC
#define USB3_DP_QSERDES_RXB_DFE_4 0x18C0
#define USB3_DP_QSERDES_RXB_TX_ADAPT_PRE_THRESH1 0x18C4
#define USB3_DP_QSERDES_RXB_TX_ADAPT_PRE_THRESH2 0x18C8
#define USB3_DP_QSERDES_RXB_TX_ADAPT_POST_THRESH 0x18CC
#define USB3_DP_QSERDES_RXB_TX_ADAPT_MAIN_THRESH 0x18D0
#define USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x18D4
#define USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x18D8
#define USB3_DP_QSERDES_RXB_GM_CAL 0x18DC
#define USB3_DP_QSERDES_RXB_RX_VGA_GAIN2_LSB 0x18E0
#define USB3_DP_QSERDES_RXB_RX_VGA_GAIN2_MSB 0x18E4
#define USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL1 0x18E8
#define USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x18EC
#define USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x18F0
#define USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x18F4
#define USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0x18F8
#define USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x18FC
#define USB3_DP_QSERDES_RXB_RX_IDAC_MEASURE_TIME 0x1900
#define USB3_DP_QSERDES_RXB_RX_IDAC_ACCUMULATOR 0x1904
#define USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_LSB 0x1908
#define USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_MSB 0x190C
#define USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1910
#define USB3_DP_QSERDES_RXB_RX_OFFSET_ADAPTOR_CNTRL2 0x1914
#define USB3_DP_QSERDES_RXB_SIGDET_ENABLES 0x1918
#define USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x191C
#define USB3_DP_QSERDES_RXB_SIGDET_LVL 0x1920
#define USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x1924
#define USB3_DP_QSERDES_RXB_RX_BAND 0x1928
#define USB3_DP_QSERDES_RXB_CDR_FREEZE_UP_DN 0x192C
#define USB3_DP_QSERDES_RXB_CDR_RESET_OVERRIDE 0x1930
#define USB3_DP_QSERDES_RXB_RX_INTERFACE_MODE 0x1934
#define USB3_DP_QSERDES_RXB_JITTER_GEN_MODE 0x1938
#define USB3_DP_QSERDES_RXB_SJ_AMP1 0x193C
#define USB3_DP_QSERDES_RXB_SJ_AMP2 0x1940
#define USB3_DP_QSERDES_RXB_SJ_PER1 0x1944
#define USB3_DP_QSERDES_RXB_SJ_PER2 0x1948
#define USB3_DP_QSERDES_RXB_PPM_OFFSET1 0x194C
#define USB3_DP_QSERDES_RXB_PPM_OFFSET2 0x1950
#define USB3_DP_QSERDES_RXB_SIGN_PPM_PERIOD1 0x1954
#define USB3_DP_QSERDES_RXB_SIGN_PPM_PERIOD2 0x1958
#define USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0x195C
#define USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0x1960
#define USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0x1964
#define USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x1968
#define USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0x196C
#define USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0x1970
#define USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0x1974
#define USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0x1978
#define USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x197C
#define USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0x1980
#define USB3_DP_QSERDES_RXB_RX_MODE_10_LOW 0x1984
#define USB3_DP_QSERDES_RXB_RX_MODE_10_HIGH 0x1988
#define USB3_DP_QSERDES_RXB_RX_MODE_10_HIGH2 0x198C
#define USB3_DP_QSERDES_RXB_RX_MODE_10_HIGH3 0x1990
#define USB3_DP_QSERDES_RXB_RX_MODE_10_HIGH4 0x1994
#define USB3_DP_QSERDES_RXB_PHPRE_CTRL 0x1998
#define USB3_DP_QSERDES_RXB_PHPRE_INITVAL 0x199C
#define USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x19A0
#define USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x19A4
#define USB3_DP_QSERDES_RXB_DCC_CTRL1 0x19A8
#define USB3_DP_QSERDES_RXB_DCC_CTRL2 0x19AC
#define USB3_DP_QSERDES_RXB_VTH_CODE 0x19B0
#define USB3_DP_QSERDES_RXB_VTH_MIN_THRESH 0x19B4
#define USB3_DP_QSERDES_RXB_VTH_MAX_THRESH 0x19B8
#define USB3_DP_QSERDES_RXB_ALOG_OBSV_BUS_CTRL_1 0x19BC
#define USB3_DP_QSERDES_RXB_PI_CTRL1 0x19C0
#define USB3_DP_QSERDES_RXB_PI_CTRL2 0x19C4
#define USB3_DP_QSERDES_RXB_PI_QUAD 0x19C8
#define USB3_DP_QSERDES_RXB_IDATA1 0x19CC
#define USB3_DP_QSERDES_RXB_IDATA2 0x19D0
#define USB3_DP_QSERDES_RXB_AUX_DATA1 0x19D4
#define USB3_DP_QSERDES_RXB_AUX_DATA2 0x19D8
#define USB3_DP_QSERDES_RXB_AC_JTAG_OUTP 0x19DC
#define USB3_DP_QSERDES_RXB_AC_JTAG_OUTN 0x19E0
#define USB3_DP_QSERDES_RXB_RX_SIGDET 0x19E4
#define USB3_DP_QSERDES_RXB_ALOG_OBSV_BUS_STATUS_1 0x19E8
/* Module: USB3_DP_PHY_USB3_PCS_MISC_USB3_PCS_MISC_USB3_PCS_MISC */
#define USB3_DP_PCS_MISC_TYPEC_CTRL 0x1A00
#define USB3_DP_PCS_MISC_TYPEC_PWRDN_CTRL 0x1A04
#define USB3_DP_PCS_MISC_PCS_MISC_CONFIG1 0x1A08
#define USB3_DP_PCS_MISC_CLAMP_ENABLE 0x1A0C
#define USB3_DP_PCS_MISC_TYPEC_STATUS 0x1A10
#define USB3_DP_PCS_MISC_PLACEHOLDER_STATUS 0x1A14
/* Module: USB3_DP_PHY_USB3_PCS_LN_USB3_PCS_LN_USB3_PCS_LANE */
#define USB3_DP_PCS_LN_PCS_STATUS1 0x1B00
#define USB3_DP_PCS_LN_PCS_STATUS2 0x1B04
#define USB3_DP_PCS_LN_PCS_STATUS2_CLEAR 0x1B08
#define USB3_DP_PCS_LN_PCS_STATUS3 0x1B0C
#define USB3_DP_PCS_LN_BIST_CHK_ERR_CNT_L_STATUS 0x1B10
#define USB3_DP_PCS_LN_BIST_CHK_ERR_CNT_H_STATUS 0x1B14
#define USB3_DP_PCS_LN_BIST_CHK_STATUS 0x1B18
#define USB3_DP_PCS_LN_INSIG_SW_CTRL1 0x1B1C
#define USB3_DP_PCS_LN_INSIG_MX_CTRL1 0x1B20
#define USB3_DP_PCS_LN_OUTSIG_SW_CTRL1 0x1B24
#define USB3_DP_PCS_LN_OUTSIG_MX_CTRL1 0x1B28
#define USB3_DP_PCS_LN_TEST_CONTROL1 0x1B2C
#define USB3_DP_PCS_LN_BIST_CTRL 0x1B30
#define USB3_DP_PCS_LN_PRBS_SEED0 0x1B34
#define USB3_DP_PCS_LN_PRBS_SEED1 0x1B38
#define USB3_DP_PCS_LN_FIXED_PAT_CTRL 0x1B3C
#define USB3_DP_PCS_LN_EQ_CONFIG 0x1B40
#define USB3_DP_PCS_LN_TEST_CONTROL2 0x1B44
#define USB3_DP_PCS_LN_TEST_CONTROL3 0x1B48
/* Module: USB3_DP_PHY_USB3_PCS_USB3_PCS_USB3_PCS */
#define USB3_DP_PCS_SW_RESET 0x1C00
#define USB3_DP_PCS_REVISION_ID0 0x1C04
#define USB3_DP_PCS_REVISION_ID1 0x1C08
#define USB3_DP_PCS_REVISION_ID2 0x1C0C
#define USB3_DP_PCS_REVISION_ID3 0x1C10
#define USB3_DP_PCS_PCS_STATUS1 0x1C14
#define USB3_DP_PCS_PCS_STATUS2 0x1C18
#define USB3_DP_PCS_PCS_STATUS3 0x1C1C
#define USB3_DP_PCS_PCS_STATUS4 0x1C20
#define USB3_DP_PCS_PCS_STATUS5 0x1C24
#define USB3_DP_PCS_PCS_STATUS6 0x1C28
#define USB3_DP_PCS_PCS_STATUS7 0x1C2C
#define USB3_DP_PCS_DEBUG_BUS_0_STATUS 0x1C30
#define USB3_DP_PCS_DEBUG_BUS_1_STATUS 0x1C34
#define USB3_DP_PCS_DEBUG_BUS_2_STATUS 0x1C38
#define USB3_DP_PCS_DEBUG_BUS_3_STATUS 0x1C3C
#define USB3_DP_PCS_POWER_DOWN_CONTROL 0x1C40
#define USB3_DP_PCS_START_CONTROL 0x1C44
#define USB3_DP_PCS_INSIG_SW_CTRL1 0x1C48
#define USB3_DP_PCS_INSIG_SW_CTRL2 0x1C4C
#define USB3_DP_PCS_INSIG_SW_CTRL3 0x1C50
#define USB3_DP_PCS_INSIG_SW_CTRL4 0x1C54
#define USB3_DP_PCS_INSIG_SW_CTRL5 0x1C58
#define USB3_DP_PCS_INSIG_SW_CTRL6 0x1C5C
#define USB3_DP_PCS_INSIG_SW_CTRL7 0x1C60
#define USB3_DP_PCS_INSIG_SW_CTRL8 0x1C64
#define USB3_DP_PCS_INSIG_MX_CTRL1 0x1C68
#define USB3_DP_PCS_INSIG_MX_CTRL2 0x1C6C
#define USB3_DP_PCS_INSIG_MX_CTRL3 0x1C70
#define USB3_DP_PCS_INSIG_MX_CTRL4 0x1C74
#define USB3_DP_PCS_INSIG_MX_CTRL5 0x1C78
#define USB3_DP_PCS_INSIG_MX_CTRL7 0x1C7C
#define USB3_DP_PCS_INSIG_MX_CTRL8 0x1C80
#define USB3_DP_PCS_OUTSIG_SW_CTRL1 0x1C84
#define USB3_DP_PCS_OUTSIG_MX_CTRL1 0x1C88
#define USB3_DP_PCS_CLAMP_ENABLE 0x1C8C
#define USB3_DP_PCS_POWER_STATE_CONFIG1 0x1C90
#define USB3_DP_PCS_POWER_STATE_CONFIG2 0x1C94
#define USB3_DP_PCS_FLL_CNTRL1 0x1C98
#define USB3_DP_PCS_FLL_CNTRL2 0x1C9C
#define USB3_DP_PCS_FLL_CNT_VAL_L 0x1CA0
#define USB3_DP_PCS_FLL_CNT_VAL_H_TOL 0x1CA4
#define USB3_DP_PCS_FLL_MAN_CODE 0x1CA8
#define USB3_DP_PCS_TEST_CONTROL1 0x1CAC
#define USB3_DP_PCS_TEST_CONTROL2 0x1CB0
#define USB3_DP_PCS_TEST_CONTROL3 0x1CB4
#define USB3_DP_PCS_TEST_CONTROL4 0x1CB8
#define USB3_DP_PCS_TEST_CONTROL5 0x1CBC
#define USB3_DP_PCS_TEST_CONTROL6 0x1CC0
#define USB3_DP_PCS_LOCK_DETECT_CONFIG1 0x1CC4
#define USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x1CC8
#define USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x1CCC
#define USB3_DP_PCS_LOCK_DETECT_CONFIG4 0x1CD0
#define USB3_DP_PCS_LOCK_DETECT_CONFIG5 0x1CD4
#define USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x1CD8
#define USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x1CDC
#define USB3_DP_PCS_REFGEN_REQ_CONFIG2 0x1CE0
#define USB3_DP_PCS_REFGEN_REQ_CONFIG3 0x1CE4
#define USB3_DP_PCS_BIST_CTRL 0x1CE8
#define USB3_DP_PCS_PRBS_POLY0 0x1CEC
#define USB3_DP_PCS_PRBS_POLY1 0x1CF0
#define USB3_DP_PCS_FIXED_PAT0 0x1CF4
#define USB3_DP_PCS_FIXED_PAT1 0x1CF8
#define USB3_DP_PCS_FIXED_PAT2 0x1CFC
#define USB3_DP_PCS_FIXED_PAT3 0x1D00
#define USB3_DP_PCS_FIXED_PAT4 0x1D04
#define USB3_DP_PCS_FIXED_PAT5 0x1D08
#define USB3_DP_PCS_FIXED_PAT6 0x1D0C
#define USB3_DP_PCS_FIXED_PAT7 0x1D10
#define USB3_DP_PCS_FIXED_PAT8 0x1D14
#define USB3_DP_PCS_FIXED_PAT9 0x1D18
#define USB3_DP_PCS_FIXED_PAT10 0x1D1C
#define USB3_DP_PCS_FIXED_PAT11 0x1D20
#define USB3_DP_PCS_FIXED_PAT12 0x1D24
#define USB3_DP_PCS_FIXED_PAT13 0x1D28
#define USB3_DP_PCS_FIXED_PAT14 0x1D2C
#define USB3_DP_PCS_FIXED_PAT15 0x1D30
#define USB3_DP_PCS_TXMGN_CONFIG 0x1D34
#define USB3_DP_PCS_G12S1_TXMGN_V0 0x1D38
#define USB3_DP_PCS_G12S1_TXMGN_V1 0x1D3C
#define USB3_DP_PCS_G12S1_TXMGN_V2 0x1D40
#define USB3_DP_PCS_G12S1_TXMGN_V3 0x1D44
#define USB3_DP_PCS_G12S1_TXMGN_V4 0x1D48
#define USB3_DP_PCS_G12S1_TXMGN_V0_RS 0x1D4C
#define USB3_DP_PCS_G12S1_TXMGN_V1_RS 0x1D50
#define USB3_DP_PCS_G12S1_TXMGN_V2_RS 0x1D54
#define USB3_DP_PCS_G12S1_TXMGN_V3_RS 0x1D58
#define USB3_DP_PCS_G12S1_TXMGN_V4_RS 0x1D5C
#define USB3_DP_PCS_G3S2_TXMGN_MAIN 0x1D60
#define USB3_DP_PCS_G3S2_TXMGN_MAIN_RS 0x1D64
#define USB3_DP_PCS_G12S1_TXDEEMPH_M6DB 0x1D68
#define USB3_DP_PCS_G12S1_TXDEEMPH_M3P5DB 0x1D6C
#define USB3_DP_PCS_G3S2_PRE_GAIN 0x1D70
#define USB3_DP_PCS_G3S2_POST_GAIN 0x1D74
#define USB3_DP_PCS_G3S2_PRE_POST_OFFSET 0x1D78
#define USB3_DP_PCS_G3S2_PRE_GAIN_RS 0x1D7C
#define USB3_DP_PCS_G3S2_POST_GAIN_RS 0x1D80
#define USB3_DP_PCS_G3S2_PRE_POST_OFFSET_RS 0x1D84
#define USB3_DP_PCS_RX_SIGDET_LVL 0x1D88
#define USB3_DP_PCS_RX_SIGDET_DTCT_CNTRL 0x1D8C
#define USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_L 0x1D90
#define USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_H 0x1D94
#define USB3_DP_PCS_RATE_SLEW_CNTRL1 0x1D98
#define USB3_DP_PCS_RATE_SLEW_CNTRL2 0x1D9C
#define USB3_DP_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1DA0
#define USB3_DP_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1DA4
#define USB3_DP_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1DA8
#define USB3_DP_PCS_TSYNC_RSYNC_TIME 0x1DAC
#define USB3_DP_PCS_CDR_RESET_TIME 0x1DB0
#define USB3_DP_PCS_TSYNC_DLY_TIME 0x1DB4
#define USB3_DP_PCS_ELECIDLE_DLY_SEL 0x1DB8
#define USB3_DP_PCS_CMN_ACK_OUT_SEL 0x1DBC
#define USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x1DC0
#define USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x1DC4
#define USB3_DP_PCS_ALIGN_DETECT_CONFIG3 0x1DC8
#define USB3_DP_PCS_ALIGN_DETECT_CONFIG4 0x1DCC
#define USB3_DP_PCS_PCS_TX_RX_CONFIG 0x1DD0
#define USB3_DP_PCS_RX_IDLE_DTCT_CNTRL 0x1DD4
#define USB3_DP_PCS_RX_DCC_CAL_CONFIG 0x1DD8
#define USB3_DP_PCS_EQ_CONFIG1 0x1DDC
#define USB3_DP_PCS_EQ_CONFIG2 0x1DE0
#define USB3_DP_PCS_EQ_CONFIG3 0x1DE4
#define USB3_DP_PCS_EQ_CONFIG4 0x1DE8
#define USB3_DP_PCS_EQ_CONFIG5 0x1DEC
/* Module: USB3_DP_PHY_USB3_PCS_USB3_USB3_PCS_USB3_USB3_PCS_USB3 */
#define USB3_DP_PCS_USB3_POWER_STATE_CONFIG1 0x1F00
#define USB3_DP_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x1F04
#define USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x1F08
#define USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x1F0C
#define USB3_DP_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x1F10
#define USB3_DP_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x1F14
#define USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x1F18
#define USB3_DP_PCS_USB3_LFPS_TX_ECSTART 0x1F1C
#define USB3_DP_PCS_USB3_LFPS_PER_TIMER_VAL 0x1F20
#define USB3_DP_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x1F24
#define USB3_DP_PCS_USB3_LFPS_CONFIG1 0x1F28
#define USB3_DP_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x1F2C
#define USB3_DP_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x1F30
#define USB3_DP_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x1F34
#define USB3_DP_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x1F38
#define USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x1F3C
#define USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x1F40
#define USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x1F44
#define USB3_DP_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x1F48
#define USB3_DP_PCS_USB3_ARCVR_DTCT_CM_DLY 0x1F4C
#define USB3_DP_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x1F50
#define USB3_DP_PCS_USB3_ALFPS_DEGLITCH_VAL 0x1F54
#define USB3_DP_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x1F58
#define USB3_DP_PCS_USB3_TEST_CONTROL 0x1F5C
#define USB3_DP_PCS_USB3_RXTERMINATION_DLY_SEL 0x1F60
#endif /* _DT_BINDINGS_PHY_QCOM_5NM_QMP_COMBO_USB_H */

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include/dt-bindings/power/qcom-aoss-qmp.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2018, Linaro Ltd.
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __DT_BINDINGS_POWER_QCOM_AOSS_QMP_H
#define __DT_BINDINGS_POWER_QCOM_AOSS_QMP_H
#define AOSS_QMP_LS_CDSP 0
#define AOSS_QMP_LS_LPASS 1
#define AOSS_QMP_LS_MODEM 2
#define AOSS_QMP_LS_SLPI 3
#define AOSS_QMP_LS_SPSS 4
#define AOSS_QMP_LS_VENUS 5
#endif

28
include/dt-bindings/regulator/qcom,rpm-smd-regulator.h Normal file
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@@ -0,0 +1,28 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/* Copyright (c) 2015, 2017, 2019-2020, The Linux Foundation. All rights reserved. */
/* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */
#ifndef __QCOM_RPM_SMD_REGULATOR_H
#define __QCOM_RPM_SMD_REGULATOR_H
#define RPM_SMD_REGULATOR_LEVEL_NONE 0
#define RPM_SMD_REGULATOR_LEVEL_RETENTION 16
#define RPM_SMD_REGULATOR_LEVEL_RETENTION_PLUS 32
#define RPM_SMD_REGULATOR_LEVEL_MIN_SVS 48
#define RPM_SMD_REGULATOR_LEVEL_LOW_SVS 64
#define RPM_SMD_REGULATOR_LEVEL_SVS 128
#define RPM_SMD_REGULATOR_LEVEL_SVS_PLUS 192
#define RPM_SMD_REGULATOR_LEVEL_NOM 256
#define RPM_SMD_REGULATOR_LEVEL_NOM_PLUS 320
#define RPM_SMD_REGULATOR_LEVEL_TURBO 384
#define RPM_SMD_REGULATOR_LEVEL_TURBO_NO_CPR 416
#define RPM_SMD_REGULATOR_LEVEL_SUPER_TURBO 464
#define RPM_SMD_REGULATOR_LEVEL_BINNING 512
#define RPM_SMD_REGULATOR_MODE_PASS 0
#define RPM_SMD_REGULATOR_MODE_RET 1
#define RPM_SMD_REGULATOR_MODE_LPM 2
#define RPM_SMD_REGULATOR_MODE_AUTO 3
#define RPM_SMD_REGULATOR_MODE_HPM 4
#endif

81
include/dt-bindings/regulator/qcom,rpmh-regulator-levels.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __QCOM_RPMH_REGULATOR_LEVELS_H
#define __QCOM_RPMH_REGULATOR_LEVELS_H
/* These levels may be used for ARC type RPMh regulators. */
#define RPMH_REGULATOR_LEVEL_RETENTION 16
#define RPMH_REGULATOR_LEVEL_MIN_SVS 48
#define RPMH_REGULATOR_LEVEL_LOW_SVS_D3 50
#define RPMH_REGULATOR_LEVEL_LOW_SVS_D2 52
#define RPMH_REGULATOR_LEVEL_LOW_SVS_D1 56
#define RPMH_REGULATOR_LEVEL_LOW_SVS_D0 60
#define RPMH_REGULATOR_LEVEL_LOW_SVS 64
#define RPMH_REGULATOR_LEVEL_LOW_SVS_P1 72
#define RPMH_REGULATOR_LEVEL_LOW_SVS_L1 80
#define RPMH_REGULATOR_LEVEL_LOW_SVS_L2 96
#define RPMH_REGULATOR_LEVEL_SVS 128
#define RPMH_REGULATOR_LEVEL_SVS_L0 144
#define RPMH_REGULATOR_LEVEL_SVS_L1 192
#define RPMH_REGULATOR_LEVEL_SVS_L2 224
#define RPMH_REGULATOR_LEVEL_NOM 256
#define RPMH_REGULATOR_LEVEL_NOM_L0 288
#define RPMH_REGULATOR_LEVEL_NOM_L1 320
#define RPMH_REGULATOR_LEVEL_NOM_L2 336
#define RPMH_REGULATOR_LEVEL_TURBO 384
#define RPMH_REGULATOR_LEVEL_TURBO_L0 400
#define RPMH_REGULATOR_LEVEL_TURBO_L1 416
#define RPMH_REGULATOR_LEVEL_TURBO_L2 432
#define RPMH_REGULATOR_LEVEL_TURBO_L3 448
#define RPMH_REGULATOR_LEVEL_TURBO_L4 452
#define RPMH_REGULATOR_LEVEL_TURBO_L5 456
#define RPMH_REGULATOR_LEVEL_SUPER_TURBO 464
#define RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR 480
#define RPMH_REGULATOR_LEVEL_MAX 65535
/*
* These set constants may be used as the value for qcom,set of an RPMh
* resource device.
*/
#define RPMH_REGULATOR_SET_ACTIVE 1
#define RPMH_REGULATOR_SET_SLEEP 2
#define RPMH_REGULATOR_SET_ALL 3
/*
* These mode constants may be used for qcom,supported-modes and qcom,init-mode
* properties of an RPMh resource. Each type of regulator supports a subset of
* the possible modes.
*
* %RPMH_REGULATOR_MODE_PASS: Pass-through mode in which output is directly
* tied to input. This mode is only supported by
* BOB type regulators.
* %RPMH_REGULATOR_MODE_RET: Retention mode in which only an extremely small
* load current is allowed. This mode is supported
* by LDO and SMPS type regulators.
* %RPMH_REGULATOR_MODE_LPM: Low power mode in which a small load current is
* allowed. This mode corresponds to PFM for SMPS
* and BOB type regulators. This mode is supported
* by LDO, HFSMPS, BOB, and PMIC4 FTSMPS type
* regulators.
* %RPMH_REGULATOR_MODE_AUTO: Auto mode in which the regulator hardware
* automatically switches between LPM and HPM based
* upon the real-time load current. This mode is
* supported by HFSMPS, BOB, and PMIC4 FTSMPS type
* regulators.
* %RPMH_REGULATOR_MODE_HPM: High power mode in which the full rated current
* of the regulator is allowed. This mode
* corresponds to PWM for SMPS and BOB type
* regulators. This mode is supported by all types
* of regulators.
*/
#define RPMH_REGULATOR_MODE_PASS 0
#define RPMH_REGULATOR_MODE_RET 1
#define RPMH_REGULATOR_MODE_LPM 2
#define RPMH_REGULATOR_MODE_AUTO 3
#define RPMH_REGULATOR_MODE_HPM 4
#endif

7
include/dt-bindings/samsung/debug/qcom/sec_qc_irq_exit_log.h Normal file
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#ifndef __DT_BINDINGS__SEC_QC_IRQ_EXIT_LOG_H__
#define __DT_BINDINGS__SEC_QC_IRQ_EXIT_LOG_H__
/* crc32 <(echo -n "SEC_QC_IRQ_EXIT_LOG_MAGIC") | tr '[a-z]' '[A-Z]' */
#define SEC_QC_IRQ_EXIT_LOG_MAGIC 0xCD0BD0E1
#endif /* __DT_BINDINGS__SEC_QC_IRQ_EXIT_LOG_H__ */

7
include/dt-bindings/samsung/debug/qcom/sec_qc_irq_log.h Normal file
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#ifndef __DT_BINDINGS__SEC_QC_IRQ_LOG_H__
#define __DT_BINDINGS__SEC_QC_IRQ_LOG_H__
/* crc32 <(echo -n "SEC_QC_IRQ_LOG_MAGIC") | tr '[a-z]' '[A-Z]' */
#define SEC_QC_IRQ_LOG_MAGIC 0x811E64D7
#endif /* __DT_BINDINGS__SEC_QC_IRQ_LOG_H__ */

7
include/dt-bindings/samsung/debug/qcom/sec_qc_sched_log.h Normal file
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#ifndef __DT_BINDINGS__SEC_QC_SCHED_LOG_H__
#define __DT_BINDINGS__SEC_QC_SCHED_LOG_H__
/* crc32 <(echo -n "SEC_QC_SCHED_LOG_MAGIC") | tr '[a-z]' '[A-Z]' */
#define SEC_QC_SCHED_LOG_MAGIC 0x705E7C9E
#endif /* __DT_BINDINGS__SEC_QC_SCHED_LOG_H__ */

7
include/dt-bindings/samsung/debug/sec_arm64_vh_ipi_stop.h Normal file
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#ifndef __DT_BINDINGS__SEC_ARM64_VH_IPI_STOP_H__
#define __DT_BINDINGS__SEC_ARM64_VH_IPI_STOP_H__
/* crc32 <(echo -n "SEC_ARM64_VH_IPI_STOP_MAGIC") | tr '[a-z]' '[A-Z]' */
#define SEC_ARM64_VH_IPI_STOP_MAGIC 0x86655958
#endif /* __DT_BINDINGS__SEC_ARM64_VH_IPI_STOP_H__ */

12
include/dt-bindings/samsung/debug/sec_crashkey.h Normal file
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#ifndef __DT_BINDINGS__SEC_CRASHKEY_H__
#define __DT_BINDINGS__SEC_CRASHKEY_H__
#define EVENT_KEY_PRESS(__keycode) \
<__keycode 1>
#define EVENT_KEY_RELEASE(__keycode) \
<__keycode 0>
#define EVENT_KEY_PRESS_AND_RELEASE(__keycode) \
EVENT_KEY_PRESS(__keycode), \
EVENT_KEY_RELEASE(__keycode)
#endif /* __DT_BINDINGS__SEC_CRASHKEY_H__ */

8
include/dt-bindings/samsung/debug/sec_debug.h Normal file
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#ifndef __DT_BINDINGS__SEC_DEBUG_H__
#define __DT_BINDINGS__SEC_DEBUG_H__
#define SEC_DEBUG_LEVEL_LOW 0x4F4C
#define SEC_DEBUG_LEVEL_MID 0x494D
#define SEC_DEBUG_LEVEL_HIGH 0x4948
#endif /* __DT_BINDINGS__SEC_DEBUG_H__ */

11
include/dt-bindings/samsung/debug/sec_log_buf.h Normal file
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#ifndef __DT_BINDINGS__SEC_LOG_BUF_H__
#define __DT_BINDINGS__SEC_LOG_BUF_H__
#define SEC_LOG_BUF_STRATEGY_BUILTIN 0
#define SEC_LOG_BUF_STRATEGY_KPROBE 1
#define SEC_LOG_BUF_STRATEGY_CONSOLE 2
#define SEC_LOG_BUF_STRATEGY_TP_CONSOLE 3
#define SEC_LOG_BUF_STRATEGY_VH_LOGBUF 4
#define SEC_LOG_BUF_NR_STRATEGIES (SEC_LOG_BUF_STRATEGY_VH_LOGBUF + 1)
#endif /* __DT_BINDINGS__SEC_LOG_BUF_H__ */

7
include/dt-bindings/samsung/debug/sec_riscv64_vh_ipi_stop.h Normal file
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#ifndef __DT_BINDINGS__SEC_RISCV64_VH_IPI_STOP_H__
#define __DT_BINDINGS__SEC_RISCV64_VH_IPI_STOP_H__
/* crc32 <(echo -n "SEC_RISCV64_VH_IPI_STOP_MAGIC") | tr '[a-z]' '[A-Z]' */
#define SEC_RISCV64_VH_IPI_STOP_MAGIC 0x699BB6F4
#endif /* __DT_BINDINGS__SEC_RISCV64_VH_IPI_STOP_H__ */

15
include/dt-bindings/soc/qcom,dcc_v2.h Normal file
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@@ -0,0 +1,15 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2017-2019,2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __DT_BINDINGS_QCOM_DCC_V2_H
#define __DT_BINDINGS_QCOM_DCC_V2_H
#define DCC_READ 0
#define DCC_WRITE 1
#define DCC_LOOP 2
#define DCC_READ_WRITE 3
#endif

44
include/dt-bindings/soc/qcom,ipcc.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __DT_BINDINGS_QCOM_IPCC_H
#define __DT_BINDINGS_QCOM_IPCC_H
/* Signal IDs for MPROC protocol */
#define IPCC_MPROC_SIGNAL_GLINK_QMP 0
#define IPCC_MPROC_SIGNAL_TZ 1
#define IPCC_MPROC_SIGNAL_SMP2P 2
#define IPCC_MPROC_SIGNAL_PING 3
#define IPCC_MPROC_SIGNAL_MAX 4 /* Used by driver only */
#define IPCC_COMPUTE_L0_SIGNAL_MAX 32 /* Used by driver only */
#define IPCC_COMPUTE_L1_SIGNAL_MAX 32 /* Used by driver only */
/* Client IDs */
#define IPCC_CLIENT_AOP 0
#define IPCC_CLIENT_TZ 1
#define IPCC_CLIENT_MPSS 2
#define IPCC_CLIENT_LPASS 3
#define IPCC_CLIENT_SLPI 4
#define IPCC_CLIENT_SDC 5
#define IPCC_CLIENT_CDSP 6
#define IPCC_CLIENT_NPU 7
#define IPCC_CLIENT_APSS 8
#define IPCC_CLIENT_GPU 9
#define IPCC_CLIENT_CVP 10
#define IPCC_CLIENT_CAM 11
#define IPCC_CLIENT_VPU 12
#define IPCC_CLIENT_PCIE0 13
#define IPCC_CLIENT_PCIE1 14
#define IPCC_CLIENT_PCIE2 15
#define IPCC_CLIENT_SPSS 16
#define IPCC_CLIENT_TME 23
#define IPCC_CLIENT_WPSS 24
#define IPCC_CLIENT_SOCCP 46
#define IPCC_CLIENT_BROADCAST 0xF000
#define IPCC_CLIENT_MAX 47 /* Used by driver only */
#endif

3
include/dt-bindings/soc/qcom,rpmh-rsc.h
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@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
* Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
*/
#ifndef __DT_QCOM_RPMH_RSC_H__
@@ -10,5 +10,6 @@
#define WAKE_TCS 1
#define ACTIVE_TCS 2
#define CONTROL_TCS 3
#define FAST_PATH_TCS 4
#endif /* __DT_QCOM_RPMH_RSC_H__ */

105
include/dt-bindings/thermal/thermal_qti.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/thermal/thermal.h>
#ifndef _DT_BINDINGS_QTI_THERMAL_H
#define _DT_BINDINGS_QTI_THERMAL_H
#define THERMAL_MAX_LIMIT (THERMAL_NO_LIMIT - 1)
#define AGGREGATE_COEFF_VALUE 0
#define AGGREGATE_MAX_VALUE 1
#define AGGREGATE_MIN_VALUE 2
#define QMI_PA 0
#define QMI_PA_1 1
#define QMI_PA_2 2
#define QMI_QFE_PA_0 3
#define QMI_QFE_WTR_0 4
#define QMI_MODEM_TSENS 5
#define QMI_QFE_MMW_0 6
#define QMI_QFE_MMW_1 7
#define QMI_QFE_MMW_2 8
#define QMI_QFE_MMW_3 9
#define QMI_XO_THERM 10
#define QMI_QFE_PA_MDM 11
#define QMI_QFE_PA_WTR 12
#define QMI_QFE_MMW_STREAMER_0 13
#define QMI_QFE_MMW_0_MOD 14
#define QMI_QFE_MMW_1_MOD 15
#define QMI_QFE_MMW_2_MOD 16
#define QMI_QFE_MMW_3_MOD 17
#define QMI_QFE_RET_PA_0 18
#define QMI_QFE_WTR_PA_0 19
#define QMI_QFE_WTR_PA_1 20
#define QMI_QFE_WTR_PA_2 21
#define QMI_QFE_WTR_PA_3 22
#define QMI_SYS_THERM_1 23
#define QMI_SYS_THERM_2 24
#define QMI_MODEM_TSENS_1 25
#define QMI_MMW_PA1 26
#define QMI_MMW_PA2 27
#define QMI_MMW_PA3 28
#define QMI_SDR_MMW 29
#define QMI_QTM_THERM 30
#define QMI_BCL_WARN 31
#define QMI_SDR0_PA0 32
#define QMI_SDR0_PA1 33
#define QMI_SDR0_PA2 34
#define QMI_SDR0_PA3 35
#define QMI_SDR0_PA4 36
#define QMI_SDR0_PA5 37
#define QMI_SDR0 38
#define QMI_SDR1_PA0 39
#define QMI_SDR1_PA1 40
#define QMI_SDR1_PA2 41
#define QMI_SDR1_PA3 42
#define QMI_SDR1_PA4 43
#define QMI_SDR1_PA5 44
#define QMI_SDR1 45
#define QMI_MMW0 46
#define QMI_MMW1 47
#define QMI_MMW2 48
#define QMI_MMW3 49
#define QMI_MMW_IFIC0 50
#define QMI_SUB1_MODEM_CFG 51
#define QMI_SUB1_LTE_CC 52
#define QMI_SUB1_MCG_FR1_CC 53
#define QMI_SUB1_MCG_FR2_CC 54
#define QMI_SUB1_SCG_FR1_CC 55
#define QMI_SUB1_SCG_FR2_CC 56
#define QMI_SUB2_MODEM_CFG 57
#define QMI_SUB2_LTE_CC 58
#define QMI_SUB2_MCG_FR1_CC 59
#define QMI_SUB2_MCG_FR2_CC 60
#define QMI_SUB2_SCG_FR1_CC 61
#define QMI_SUB2_SCG_FR2_CC 62
#define QMI_NSP_ISENSE_TRIM 63
#define QMI_EPM0 64
#define QMI_EPM1 65
#define QMI_EPM2 66
#define QMI_EPM3 67
#define QMI_EPM4 68
#define QMI_EPM5 69
#define QMI_EPM6 70
#define QMI_EPM7 71
#define QMI_SDR0_PA 72
#define QMI_SDR1_PA 73
#define QMI_SUB0_SDR0_PA 74
#define QMI_SUB1_SDR0_PA 75
#define QMI_SYS_THERM_3 76
#define QMI_SYS_THERM_4 77
#define QMI_SYS_THERM_5 78
#define QMI_SYS_THERM_6 79
#define QMI_RF_CAL 86
#define QMI_MODEM_INST_ID 0x0
#define QMI_ADSP_INST_ID 0x1
#define QMI_CDSP_INST_ID 0x43
#define QMI_SLPI_INST_ID 0x53
#define QMI_MODEM_NR_INST_ID 0x64
#endif

94
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* C++ stream style string formatter and printer used in KUnit for outputting
* KUnit messages.
*
* Copyright (C) 2020, Google LLC.
* Author: Brendan Higgins <brendanhiggins@google.com>
*/
#ifndef _KUNIT_KUNIT_STREAM_H
#define _KUNIT_KUNIT_STREAM_H
#include <linux/types.h>
#include <kunit/string-stream.h>
struct kunit;
/**
* struct kunit_stream - a std::stream style string builder.
*
* A std::stream style string builder. Allows messages to be built up and
* printed all at once. Note that the intention is to only use
* &struct kunit_stream to communicate with a user of KUnit, most often to
* communicate something about an expectation or an assertion to the user. If
* you want a similar interface, but aren't sure if this is the right class for
* you to use, you probably want to use the related string_stream class, which
* is allowed for generic string construction in a similar manner. This class is
* really only for the KUnit library to communicate certain kinds of information
* to KUnit users and should not be used by anyone else.
*
* A note on &struct kunit_stream's usage: a kunit_stream will generally
* accompany *one* expectation or assertion. Multiple expectations/assertions
* may be validated concurrently at any given time, even within a single test
* case, so sharing a kunit_stream between expectations/assertions may result in
* unintended consequences.
*/
struct kunit_stream {
/* private: internal use only. */
struct kunit *test;
struct string_stream *internal_stream;
};
/**
* alloc_kunit_stream() - constructs a new &struct kunit_stream.
* @test: The test context object.
* @gfp: The GFP flags to use for internal allocations.
*
* Constructs a new test managed &struct kunit_stream.
*/
struct kunit_stream *alloc_kunit_stream(struct kunit *test,
gfp_t gfp);
/**
* kunit_stream_add(): adds the formatted input to the internal buffer.
* @kstream: the stream being operated on.
* @fmt: printf style format string to append to stream.
*
* Appends the formatted string, @fmt, to the internal buffer.
*/
void __printf(2, 3) kunit_stream_add(struct kunit_stream *kstream,
const char *fmt, ...);
/**
* kunit_stream_append(): appends the contents of @other to @kstream.
* @kstream: the stream to which @other is appended.
* @other: the stream whose contents are appended to @kstream.
*
* Appends the contents of @other to @kstream.
*/
void kunit_stream_append(struct kunit_stream *kstream,
struct kunit_stream *other);
/**
* kunit_stream_commit(): prints out the internal buffer to the user.
* @kstream: the stream being operated on.
*
* Outputs the contents of the internal buffer as a kunit_printk formatted
* output. KUNIT_STREAM ONLY OUTPUTS ITS BUFFER TO THE USER IF COMMIT IS
* CALLED!!! The reason for this is that it allows us to construct a message
* before we know whether we want to print it out; this can be extremely handy
* if there is information you might need for a failure message that is easiest
* to collect in the steps leading up to the actual check.
*/
void kunit_stream_commit(struct kunit_stream *kstream);
/**
* kunit_stream_clear(): clears the internal buffer.
* @kstream: the stream being operated on.
*
* Clears the contents of the internal buffer.
*/
void kunit_stream_clear(struct kunit_stream *kstream);
#endif /* _KUNIT_KUNIT_STREAM_H */

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include/kunit/kunit_manager.h Normal file
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/* kunit_manager.h
*
* Driver to manage kunit
*
* Copyright (C) 2019 Samsung Electronics
*
* Sangsu Ha <sangsu.ha@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/sec_class.h>
#include <linux/device.h>
#include <linux/slab.h>
struct kunit_manager_data {
struct device *dev;
};

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305
include/kunit/params.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Macros for parsing and manipulating parameter lists needed for generating
* mocks.
*
* Copyright (C) 2020, Google LLC.
* Author: Brendan Higgins <brendanhiggins@google.com>
*/
#ifndef _KUNIT_PARAMS_H
#define _KUNIT_PARAMS_H
#define NUM_VA_ARGS_IMPL(__dummy, \
__1, \
__2, \
__3, \
__4, \
__5, \
__6, \
__7, \
__8, \
__9, \
__10, \
__11, \
__12, \
__13, \
__14, \
__15, \
__16, \
__nargs, args...) __nargs
#define NUM_VA_ARGS(args...) NUM_VA_ARGS_IMPL(__dummy, ##args, \
16, \
15, \
14, \
13, \
12, \
11, \
10, \
9, \
8, \
7, \
6, \
5, \
4, \
3, \
2, \
1, \
0)
#define CONCAT_INTERNAL(left, right) left##right
#define CONCAT(left, right) CONCAT_INTERNAL(left, right)
#define EMPTY()
/*
* Takes the name of a function style macro such as FOO() and prevents it from
* being evaluated on the current pass.
*
* This is useful when you need to write a "recursive" macro since a macro name
* becomes painted after it is pasted. If a different macro is pasted, this
* different macro won't be pasted; if we then defer the evaluation of the this
* "indirection macro", we can prevent the original definition from getting
* painted.
*
* Example:
* #define EXAMPLE EXPAND(FOO()) // FOO() is evaluated on 1st pass.
* #define EXAMPLE EXPAND(DEFER(FOO)()) // FOO() is evaluated on the second
* // pass.
*/
#define DEFER(macro_id) macro_id EMPTY()
/*
* Takes the name of a function style macro such as FOO() and prevents it from
* being evaluated on the current or following pass.
*
* This is useful when you need to DEFER inside an operation which causes an
* extra pass, like IF.
*
* Example:
* #define EXAMPLE EXPAND(FOO()) // FOO() is evaluated on 1st pass.
* #define EXAMPLE EXPAND(DEFER(FOO)()) // FOO() is evaluated on the second
* // pass.
* #define EXAMPLE EXPAND(OBSTRUCT(FOO)()) // FOO() is evaluated on the third
* // pass.
*/
#define OBSTRUCT(macro_id) macro_id DEFER(EMPTY)()
#define EXPAND_1(args...) args
#define EXPAND_2(args...) EXPAND_1(EXPAND_1(args))
#define EXPAND_4(args...) EXPAND_2(EXPAND_2(args))
#define EXPAND_8(args...) EXPAND_4(EXPAND_4(args))
#define EXPAND_16(args...) EXPAND_8(EXPAND_8(args))
/*
* Causes multiple evaluation passes of a macro.
*
* CPP is implemented as a push down automaton. It consumes a stream of tokens
* and as it comes across macros, it either evaluates them and pastes the
* result, or if the macro is a function macro, it pushes the macro to a stack,
* it evaluates the input to the function macro, pops the state from the stack
* and continues.
*
* This macro serves the function of making the cursor return to the beginging
* of a macro that requires mulitple passes to evaluate. It is most useful when
* used with DEFER(...) and OBSTRUCT(...).
*/
#define EXPAND(args...) EXPAND_16(args)
#define INC(id) INC_##id
#define INC_0 1
#define INC_1 2
#define INC_2 3
#define INC_3 4
#define INC_4 5
#define INC_5 6
#define INC_6 7
#define INC_7 8
#define INC_8 9
#define INC_9 10
#define INC_10 11
#define INC_11 12
#define INC_12 13
#define INC_13 14
#define INC_14 15
#define INC_15 16
#define INC_16 17
#define DEC(id) DEC_##id
#define DEC_1 0
#define DEC_2 1
#define DEC_3 2
#define DEC_4 3
#define DEC_5 4
#define DEC_6 5
#define DEC_7 6
#define DEC_8 7
#define DEC_9 8
#define DEC_10 9
#define DEC_11 10
#define DEC_12 11
#define DEC_13 12
#define DEC_14 13
#define DEC_15 14
#define DEC_16 15
#define DROP_FIRST_ARG_INTERNAL(dropped, x, args...) x
#define DROP_FIRST_ARG(args...) DROP_FIRST_ARG_INTERNAL(args)
#define EQUAL(left, right) EQUAL_##left##_##right
#define EQUAL_0_0 dropped, 1
#define EQUAL_1_1 dropped, 1
#define EQUAL_2_2 dropped, 1
#define EQUAL_3_3 dropped, 1
#define EQUAL_4_4 dropped, 1
#define EQUAL_5_5 dropped, 1
#define EQUAL_6_6 dropped, 1
#define EQUAL_7_7 dropped, 1
#define EQUAL_8_8 dropped, 1
#define EQUAL_9_9 dropped, 1
#define EQUAL_10_10 dropped, 1
#define EQUAL_11_11 dropped, 1
#define EQUAL_12_12 dropped, 1
#define EQUAL_13_13 dropped, 1
#define EQUAL_14_14 dropped, 1
#define EQUAL_15_15 dropped, 1
#define EQUAL_16_16 dropped, 1
#define IS_EQUAL(left, right) DROP_FIRST_ARG(EQUAL(left, right), 0)
#define NOT_INTERNAL(condition) NOT_##condition
#define NOT(condition) NOT_INTERNAL(condition)
#define NOT_0 1
#define NOT_1 0
#define IS_NOT_EQUAL(left, right) NOT(IS_EQUAL(left, right))
#define EMPTY_IMPL(tokens) CONCAT(EMPTY_, tokens)
#define IS_EMPTY(tokens)
#define OR_INTERNAL(left, right) OR_##left##_##right
#define OR(left, right) OR_INTERNAL(left, right)
#define OR_0_0 0
#define OR_0_1 1
#define OR_1_0 1
#define OR_1_1 1
#define IF(condition) CONCAT(IF_, condition)
#define IF_0(body)
#define IF_1(body) body
#define COMMA() ,
#define APPLY_TOKENS_INTERNAL(tokens, yield_token, seen_token) \
IF(yield_token)(IF(seen_token)(COMMA()) tokens)
#define APPLY_TOKENS(tokens, yield_token, seen_token) \
APPLY_TOKENS_INTERNAL(tokens, yield_token, seen_token)
/*
* Provides the indirection to keep the PARAM_LIST_RECURSE_INTERNAL from getting
* pasted, only useful if used with DEFER(...) or OBSTRUCT(...).
*/
#define PARAM_LIST_RECURSE_INDIRECT() PARAM_LIST_RECURSE_INTERNAL
/*
* Given a starting index, a number of args, a MACRO to apply, and a list of
* types (with at least one element) this will call MACRO with the first type in
* the list and index; it will then call itself again on all remaining types, if
* any, while incrementing index, and decrementing nargs.
*
* Assumes nargs is the number of types in the list.
*/
#define PARAM_LIST_RECURSE_INTERNAL(index, \
nargs, \
MACRO, \
FILTER, \
context, \
seen_token, \
type, \
args...) \
APPLY_TOKENS(MACRO(context, type, index), \
FILTER(context, type, index), \
seen_token) \
IF(IS_NOT_EQUAL(nargs, 1)) \
(OBSTRUCT(PARAM_LIST_RECURSE_INDIRECT)() \
(INC(index), DEC(nargs), \
MACRO, FILTER, context, \
OR(seen_token, FILTER(context, type, index)), \
args))
#define PARAM_LIST_RECURSE(index, nargs, MACRO, FILTER, context, args...) \
IF(IS_NOT_EQUAL(nargs, 0)) \
(OBSTRUCT(PARAM_LIST_RECURSE_INTERNAL)(index, \
nargs, \
MACRO, \
FILTER, \
context, \
0, \
args))
#define FILTER_NONE(context, type, index) 1
#define FILTER_INDEX_INTERNAL(index_to_drop, type, index) \
IS_NOT_EQUAL(index, index_to_drop)
#define FILTER_INDEX(index_to_drop, type, index) \
FILTER_INDEX_INTERNAL(index_to_drop, type, index)
/*
* Applies a MACRO which takes a type and the index of the type and outputs a
* sequence of tokens to a list of types.
*/
#define FOR_EACH_PARAM(MACRO, FILTER, context, args...) \
EXPAND(PARAM_LIST_RECURSE(0,\
NUM_VA_ARGS(args),\
MACRO,\
FILTER,\
context,\
args))
#define PRODUCE_TYPE_AND_ARG(context, type, index) type arg##index
#define PARAM_LIST_FROM_TYPES(args...) \
FOR_EACH_PARAM(PRODUCE_TYPE_AND_ARG, \
FILTER_NONE, \
not_used, \
args)
#define PRODUCE_TYPE_NAME(context, type, index) #type
#define TYPE_NAMES_FROM_TYPES(handle_index, args...) \
FOR_EACH_PARAM(PRODUCE_TYPE_NAME, \
FILTER_INDEX, \
handle_index, \
args)
#define PRODUCE_PTR_TO_ARG(context, type, index) &arg##index
#define PTR_TO_ARG_FROM_TYPES(handle_index, args...) \
FOR_EACH_PARAM(PRODUCE_PTR_TO_ARG, \
FILTER_INDEX, \
handle_index, \
args)
#define PRODUCE_MATCHER_AND_ARG(ctrl_index, type, index) \
IF(IS_EQUAL(index, ctrl_index))(struct mock *arg##ctrl_index) \
IF(IS_NOT_EQUAL(index, ctrl_index))( \
struct mock_param_matcher *arg##index)
#define MATCHER_PARAM_LIST_FROM_TYPES(ctrl_index, args...) \
FOR_EACH_PARAM(PRODUCE_MATCHER_AND_ARG, \
FILTER_NONE, \
ctrl_index, \
args)
#define PRODUCE_ARG(context, type, index) arg##index
#define ARG_NAMES_FROM_TYPES(ctrl_index, args...) \
FOR_EACH_PARAM(PRODUCE_ARG, \
FILTER_INDEX, \
ctrl_index, \
args)
#define PRODUCE_ARRAY_ACCESSOR(context, type, index) *((type *) params[index])
#define ARRAY_ACCESSORS_FROM_TYPES(args...) \
FOR_EACH_PARAM(PRODUCE_ARRAY_ACCESSOR, \
FILTER_NONE, \
not_used, \
args)
#endif /* _KUNIT_PARAMS_H */

37
include/kunit/strerror.h Normal file
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@@ -0,0 +1,37 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* C++ stream style string formatter and printer used in KUnit for outputting
* KUnit messages.
*
* Copyright (C) 2019, Google LLC.
* Author: Mike Krinkin <krinkin@google.com>
*/
#include <linux/types.h>
/**
* strerror() - returns a string representation for the given error code.
* @errno: an error code defined in include/uapi/asm-generic/errno-base.h or
* include/uapi/asm-generic/errno.h
*
* This function returns mnemonic representation of error code (for example,
* EPERM, ENOENT, ESRCH, etc). For unsupported errors this function returns
* NULL.
*/
const char *strerror_str(int errno);
/**
* strerror_r() - returns a string representation of the given error code.
* Unlike strerror() it may use provided buffer to store the string, so in
* the case of unknown error it returns a message containing an error code
* instead of returning NULL.
* @errno: an error code defined in include/uapi/asm-generic/errno-base.h or
* include/uapi/asm-generic/errno.h
* @buf: pointer to a buffer that could be used to store the string.
* @buflen: contains the capacity of the buffer
*
* When function uses provided buffer and it's capacity is not enough to
* store the whole string the string is truncated and always contains '\0'.
* If buflen == 0, the function returns NULL pointer as there is not enough
* space to store even '\0'.
*/
const char *strerror_r(int errno, char *buf, size_t buflen);

53
include/kunit/string-stream.h Normal file
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@@ -0,0 +1,53 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* C++ stream style string builder used in KUnit for building messages.
*
* Copyright (C) 2019, Google LLC.
* Author: Brendan Higgins <brendanhiggins@google.com>
*/
#ifndef _KUNIT_STRING_STREAM_H
#define _KUNIT_STRING_STREAM_H
#include <linux/spinlock.h>
#include <linux/types.h>
#include <linux/stdarg.h>
struct string_stream_fragment {
struct kunit *test;
struct list_head node;
char *fragment;
};
struct string_stream {
size_t length;
struct list_head fragments;
/* length and fragments are protected by this lock */
spinlock_t lock;
struct kunit *test;
gfp_t gfp;
};
struct kunit;
struct string_stream *alloc_string_stream(struct kunit *test, gfp_t gfp);
int __printf(2, 3) string_stream_add(struct string_stream *stream,
const char *fmt, ...);
int string_stream_vadd(struct string_stream *stream,
const char *fmt,
va_list args);
char *string_stream_get_string(struct string_stream *stream);
int string_stream_append(struct string_stream *stream,
struct string_stream *other);
bool string_stream_is_empty(struct string_stream *stream);
void string_stream_clear(struct string_stream *stream);
void string_stream_destroy(struct string_stream *stream);
#endif /* _KUNIT_STRING_STREAM_H */

34
include/kunit/test.h
View File

@@ -10,6 +10,9 @@
#define _KUNIT_TEST_H
#include <kunit/assert.h>
#ifdef CONFIG_SEC_KUNIT
#include <kunit/kunit-stream.h>
#endif /* CONFIG_SEC_KUNIT */
#include <kunit/try-catch.h>
#include <linux/args.h>
@@ -300,7 +303,9 @@ struct kunit {
* protect it with some type of lock.
*/
struct list_head resources; /* Protected by lock. */
#ifdef CONFIG_SEC_KUNIT
struct list_head post_conditions;
#endif /* CONFIG_SEC_KUNIT */
char status_comment[KUNIT_STATUS_COMMENT_SIZE];
};
@@ -1515,7 +1520,34 @@ do { \
} \
return NULL; \
}
#ifdef CONFIG_SEC_KUNIT
/*
* for mock feature from kunit/alpha/master
*/
struct test_initcall {
struct list_head node;
int (*init)(struct test_initcall *this, struct kunit *test);
void (*exit)(struct test_initcall *this);
};
struct kunit_post_condition {
struct list_head node;
void (*validate)(struct kunit_post_condition *condition);
};
void test_install_initcall(struct test_initcall *initcall);
#define test_pure_initcall(fn) postcore_initcall(fn)
#define test_register_initcall(initcall) \
static int register_test_initcall_##initcall(void) \
{ \
test_install_initcall(&initcall); \
\
return 0; \
} \
test_pure_initcall(register_test_initcall_##initcall)
#endif /* CONFIG_SEC_KUNIT */
// TODO(dlatypov@google.com): consider eventually migrating users to explicitly
// include resource.h themselves if they need it.
#include <kunit/resource.h>

103
include/linux/adc-tm-clients.h Normal file
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@@ -0,0 +1,103 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __QCOM_ADC_TM_H_CLIENTS__
#define __QCOM_ADC_TM_H_CLIENTS__
#include <linux/err.h>
#include <linux/types.h>
struct adc_tm_chip;
struct adc5_chip;
/**
* enum adc_tm_state - This lets the client know whether the threshold
* that was crossed was high/low.
* %ADC_TM_HIGH_STATE: Client is notified of crossing the requested high
* voltage threshold.
* %ADC_TM_COOL_STATE: Client is notified of crossing the requested cool
* temperature threshold.
* %ADC_TM_LOW_STATE: Client is notified of crossing the requested low
* voltage threshold.
* %ADC_TM_WARM_STATE: Client is notified of crossing the requested high
* temperature threshold.
*/
enum adc_tm_state {
ADC_TM_HIGH_STATE = 0,
ADC_TM_COOL_STATE = ADC_TM_HIGH_STATE,
ADC_TM_LOW_STATE,
ADC_TM_WARM_STATE = ADC_TM_LOW_STATE,
ADC_TM_STATE_NUM,
};
/**
* enum adc_tm_state_request - Request to enable/disable the corresponding
* high/low voltage/temperature thresholds.
* %ADC_TM_HIGH_THR_ENABLE: Enable high voltage threshold.
* %ADC_TM_COOL_THR_ENABLE = Enables cool temperature threshold.
* %ADC_TM_LOW_THR_ENABLE: Enable low voltage/temperature threshold.
* %ADC_TM_WARM_THR_ENABLE = Enables warm temperature threshold.
* %ADC_TM_HIGH_LOW_THR_ENABLE: Enable high and low voltage/temperature
* threshold.
* %ADC_TM_HIGH_THR_DISABLE: Disable high voltage/temperature threshold.
* %ADC_TM_COOL_THR_ENABLE = Disables cool temperature threshold.
* %ADC_TM_LOW_THR_DISABLE: Disable low voltage/temperature threshold.
* %ADC_TM_WARM_THR_ENABLE = Disables warm temperature threshold.
* %ADC_TM_HIGH_THR_DISABLE: Disable high and low voltage/temperature
* threshold.
*/
enum adc_tm_state_request {
ADC_TM_HIGH_THR_ENABLE = 0,
ADC_TM_COOL_THR_ENABLE = ADC_TM_HIGH_THR_ENABLE,
ADC_TM_LOW_THR_ENABLE,
ADC_TM_WARM_THR_ENABLE = ADC_TM_LOW_THR_ENABLE,
ADC_TM_HIGH_LOW_THR_ENABLE,
ADC_TM_HIGH_THR_DISABLE,
ADC_TM_COOL_THR_DISABLE = ADC_TM_HIGH_THR_DISABLE,
ADC_TM_LOW_THR_DISABLE,
ADC_TM_WARM_THR_DISABLE = ADC_TM_LOW_THR_DISABLE,
ADC_TM_HIGH_LOW_THR_DISABLE,
ADC_TM_THR_NUM,
};
struct adc_tm_param {
unsigned long id;
int low_thr;
int high_thr;
uint32_t channel;
enum adc_tm_state_request state_request;
void *btm_ctx;
void (*threshold_notification)(enum adc_tm_state state,
void *ctx);
};
struct device;
/* Public API */
#if IS_ENABLED(CONFIG_QCOM_SPMI_ADC5_GEN3)
struct adc5_chip *get_adc_tm_gen3(struct device *dev, const char *name);
int32_t adc_tm_channel_measure_gen3(struct adc5_chip *chip,
struct adc_tm_param *param);
int32_t adc_tm_disable_chan_meas_gen3(struct adc5_chip *chip,
struct adc_tm_param *param);
#else
static inline struct adc5_chip *get_adc_tm_gen3(
struct device *dev, const char *name)
{ return ERR_PTR(-ENXIO); }
static inline int32_t adc_tm_channel_measure_gen3(
struct adc5_chip *chip,
struct adc_tm_param *param)
{ return -ENXIO; }
static inline int32_t adc_tm_disable_chan_meas_gen3(
struct adc5_chip *chip,
struct adc_tm_param *param)
{ return -ENXIO; }
#endif
#endif /* __QCOM_ADC_TM_H_CLIENTS__ */

16
include/linux/adreno-smmu-priv.h
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@@ -1,12 +1,14 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2020 Google, Inc
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __ADRENO_SMMU_PRIV_H
#define __ADRENO_SMMU_PRIV_H
#include <linux/io-pgtable.h>
#include <linux/qcom-io-pgtable.h>
/**
* struct adreno_smmu_fault_info - container for key fault information
@@ -49,6 +51,7 @@ struct adreno_smmu_fault_info {
* before set_ttbr0_cfg(). If stalling on fault is enabled,
* the GPU driver must call resume_translation()
* @resume_translation: Resume translation after a fault
* @pgtbl_info: io-pagetables info for the GPUs context-bank
*
*
* The GPU driver (drm/msm) and adreno-smmu work together for controlling
@@ -61,12 +64,13 @@ struct adreno_smmu_fault_info {
* it's domain.
*/
struct adreno_smmu_priv {
const void *cookie;
const struct io_pgtable_cfg *(*get_ttbr1_cfg)(const void *cookie);
int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg *cfg);
void (*get_fault_info)(const void *cookie, struct adreno_smmu_fault_info *info);
void (*set_stall)(const void *cookie, bool enabled);
void (*resume_translation)(const void *cookie, bool terminate);
const void *cookie;
const struct io_pgtable_cfg *(*get_ttbr1_cfg)(const void *cookie);
int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg *cfg);
void (*get_fault_info)(const void *cookie, struct adreno_smmu_fault_info *info);
void (*set_stall)(const void *cookie, bool enabled);
void (*resume_translation)(const void *cookie, bool terminate);
struct qcom_io_pgtable_info pgtbl_info;
};
#endif /* __ADRENO_SMMU_PRIV_H */

300
include/linux/adsp/adsp_ft_common.h Executable file
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@@ -0,0 +1,300 @@
/*
* Copyright (C) 2012, Samsung Electronics Co. Ltd. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ADSP_FT_COMMON_H__
#define __ADSP_FT_COMMON_H__
#ifdef SS_SLPI_PROJECT// hal build
#ifndef IS_ENABLED
#define IS_ENABLED(x) 0
#endif
#else// kernel build
#include <linux/kernel.h>
#endif
#define PID 20000
#define NETLINK_ADSP_FAC 23
#define MAX_REG_NUM 128
/* max size of each sensor's msg_buf */
#define MSG_TYPE_SIZE_ZERO 0
#define MSG_ACCEL_MAX 128
#define MSG_GYRO_MAX 20
#define MSG_MAG_MAX 16
#define MSG_LIGHT_MAX 16
#define MSG_PROX_MAX 16
#define MSG_GYRO_TEMP_MAX 3
#define MSG_PRESSURE_TEMP_MAX 3
#define MSG_PRESSURE_MAX 128
#define MSG_FLIP_COVER_DETECTOR_MAX 3
#define MSG_BACKTAP_MAX 1
#define MSG_VOPTIC_MAX 2
#define MSG_REG_SNS_MAX 24 /* 8 * 3 */
#if IS_ENABLED(CONFIG_SUPPORT_AK09973) || defined(CONFIG_SUPPORT_AK09973)
#define MSG_DIGITAL_HALL_MAX 15
#define MSG_DIGITAL_HALL_ANGLE_MAX 58
#elif IS_ENABLED(CONFIG_SUPPORT_REF_ANGLE_WITHOUT_DIGITAL_HALL) || defined(CONFIG_SUPPORT_REF_ANGLE_WITHOUT_DIGITAL_HALL)
#define MSG_REF_ANGLE_MAX 9
#endif
#if IS_ENABLED(CONFIG_SUPPORT_DUAL_DDI_COPR_FOR_LIGHT_SENSOR) || defined(CONFIG_SUPPORT_DUAL_DDI_COPR_FOR_LIGHT_SENSOR)
#define MSG_DDI_MAX 12
#endif
#if IS_ENABLED(CONFIG_SUPPORT_FLICKER) || defined(CONFIG_SUPPORT_FLICKER)
#define MSG_FLICKER_MAX 12
#endif
#define MSG_COMMON_INFO_MAX BD_SENSOR_MAX
#define ACCEL_FACTORY_CAL_PATH "/efs/FactoryApp/accel_factory_cal"
#define SUB_ACCEL_FACTORY_CAL_PATH "/efs/FactoryApp/sub_accel_factory_cal"
#define SUB2_ACCEL_FACTORY_CAL_PATH "/efs/FactoryApp/sub2_accel_factory_cal"
#define ACCEL_HIGHG_FACTORY_CAL_PATH "/efs/FactoryApp/accel_highg_factory_cal"
#define SW_OFFSET_FILE_PATH "/efs/FactoryApp/baro_sw_offset"
#if IS_ENABLED(CONFIG_SUPPORT_AK09973) || defined(CONFIG_SUPPORT_AK09973)
#define AUTO_CAL_DATA_NUM 19
#define AUTO_CAL_FILE_BUF_LEN 140
#define DIGITAL_HALL_AUTO_CAL_X_PATH "/efs/FactoryApp/digital_hall_auto_cal_x"
#define DIGITAL_HALL_AUTO_CAL_Y_PATH "/efs/FactoryApp/digital_hall_auto_cal_y"
#define DIGITAL_HALL_AUTO_CAL_Z_PATH "/efs/FactoryApp/digital_hall_auto_cal_z"
#define ENABLE_LF_STREAM 0
#endif
#define DEVICE_MODE_HALL_OPEN 0
#define DEVICE_MODE_HALL_CLOSE 1
#define SNS_SLEEP_DURATION_10S (10)
#define SNS_ISLAND_EXIT_MAX_CNT (50)
enum {
MSG_ACCEL,
MSG_GYRO,
MSG_MAG,
MSG_PRESSURE,
MSG_LIGHT,
MSG_PROX, //5
#if IS_ENABLED(CONFIG_SUPPORT_DUAL_OPTIC) || defined(CONFIG_SUPPORT_DUAL_OPTIC)
MSG_LIGHT_SUB,
MSG_PROX_SUB,
#endif
#if IS_ENABLED(CONFIG_FLICKER_FACTORY) || defined(CONFIG_FLICKER_FACTORY)
MSG_FLICKER,
#endif
#if IS_ENABLED(CONFIG_SUPPORT_DUAL_6AXIS) || defined(CONFIG_SUPPORT_DUAL_6AXIS)
MSG_ACCEL_SUB,
MSG_GYRO_SUB,
#endif
#if IS_ENABLED(CONFIG_SUPPORT_TRIPLE_6AXIS) || defined(CONFIG_SUPPORT_TRIPLE_6AXIS)
MSG_ACCEL_SUB2,
MSG_GYRO_SUB2,
#endif
#if IS_ENABLED(CONFIG_SUPPORT_ACCEL_HIGHG) || defined(CONFIG_SUPPORT_ACCEL_HIGHG)
MSG_ACCEL_HIGHG,
#endif
#if IS_ENABLED(CONFIG_SUPPORT_DUAL_MAG) || defined(CONFIG_SUPPORT_DUAL_MAG)
MSG_MAG_SUB,
#endif
PHYSICAL_SENSOR_SYSFS,//MSG_TYPE_SIZE_ZERO
MSG_GYRO_TEMP,
#if IS_ENABLED(CONFIG_SUPPORT_DUAL_6AXIS) || defined(CONFIG_SUPPORT_DUAL_6AXIS)
MSG_GYRO_SUB_TEMP,
#endif
#if IS_ENABLED(CONFIG_SUPPORT_TRIPLE_6AXIS) || defined(CONFIG_SUPPORT_TRIPLE_6AXIS)
MSG_GYRO_SUB2_TEMP,
#endif
MSG_PRESSURE_TEMP,
MSG_MAG_CAL,//MSG_TYPE_SIZE_ZERO
#if IS_ENABLED(CONFIG_SUPPORT_DUAL_MAG) || defined(CONFIG_SUPPORT_DUAL_MAG)
MSG_MAG_CAL_SUB,
#endif
#if IS_ENABLED(CONFIG_FLIP_COVER_DETECTOR_FACTORY) || defined(CONFIG_FLIP_COVER_DETECTOR_FACTORY)
MSG_FLIP_COVER_DETECTOR,
#endif
#if IS_ENABLED(CONFIG_SUPPORT_VIRTUAL_OPTIC) || defined(CONFIG_SUPPORT_VIRTUAL_OPTIC)
MSG_VIR_OPTIC,
#endif
MSG_REG_SNS,//MSG_REG_SNS_MAX
#if IS_ENABLED(CONFIG_SUPPORT_AK09973) || defined(CONFIG_SUPPORT_AK09973)
MSG_DIGITAL_HALL,
MSG_DIGITAL_HALL_ANGLE,
#if ENABLE_LF_STREAM
MSG_LF_STREAM,
#endif
#elif IS_ENABLED(CONFIG_SUPPORT_REF_ANGLE_WITHOUT_DIGITAL_HALL) || defined(CONFIG_SUPPORT_REF_ANGLE_WITHOUT_DIGITAL_HALL)
MSG_REF_ANGLE,
#endif
#if IS_ENABLED(CONFIG_SUPPORT_DUAL_DDI_COPR_FOR_LIGHT_SENSOR) || defined(CONFIG_SUPPORT_DUAL_DDI_COPR_FOR_LIGHT_SENSOR)
MSG_DDI,
#endif
#if IS_ENABLED(CONFIG_SUPPORT_LIGHT_MAIN2_SENSOR) || defined(CONFIG_SUPPORT_LIGHT_MAIN2_SENSOR)
MSG_LIGHT_MAIN2,
#endif
#if IS_ENABLED(CONFIG_BACKTAP_FACTORY) || defined(CONFIG_BACKTAP_FACTORY)
MSG_BACKTAP,
#endif
MSG_FACTORY_INIT_CMD,//MSG_TYPE_SIZE_ZERO
MSG_SSC_CORE,//MSG_TYPE_SIZE_ZERO
MSG_SENSOR_MAX
};
/* Netlink ENUMS Message Protocols */
enum {
MSG_TYPE_GET_RAW_DATA,
MSG_TYPE_ST_SHOW_DATA,
MSG_TYPE_SET_ACCEL_LPF,
MSG_TYPE_SET_ACCEL_MOTOR,
MSG_TYPE_GET_THRESHOLD,
MSG_TYPE_SET_THRESHOLD,
MSG_TYPE_SET_TEMPORARY_MSG,
MSG_TYPE_GET_REGISTER,
MSG_TYPE_SET_REGISTER,
MSG_TYPE_GET_DUMP_REGISTER,
MSG_TYPE_GET_CAL_DATA, /*10*/
MSG_TYPE_SET_CAL_DATA,
MSG_TYPE_GET_DHR_INFO,
MSG_TYPE_FACTORY_ENABLE,
MSG_TYPE_FACTORY_DISABLE,
MSG_TYPE_OPTION_DEFINE,
MSG_TYPE_DUMPSTATE,
MSG_TYPE_MAX
};
/* Sensor types defined by android */
/* (Keep in sync with hardware/sensors-base.h and Sensor.java.) */
#define SENSOR_HANDLE_ACCELEROMETER (1)
#define SENSOR_HANDLE_GEOMAGNETIC_FIELD (2)
#define SENSOR_HANDLE_GYROSCOPE (4)
#define SENSOR_HANDLE_LIGHT (5)
#define SENSOR_HANDLE_PRESSURE (6)
#if IS_ENABLED(CONFIG_SUPPORT_DUAL_6AXIS)
#define SENSOR_HANDLE_ACCELEROMETER_SUB (65687)
#endif
#define SENSOR_HANDLE_ALL (0)
#define SENSOR_NAME_MAX 40
#if IS_ENABLED(CONFIG_SUPPORT_DUAL_OPTIC) || defined(CONFIG_SUPPORT_DUAL_OPTIC)
enum {
FSTATE_INACTIVE,
FSTATE_ACTIVE,
FSTATE_FAC_INACTIVE,
FSTATE_FAC_ACTIVE,
FSTATE_FAC_INACTIVE_2
};
#define LIGHT_DUAL_CHECK_MODE 13
enum {
VOPTIC_OP_CMD_FAC_FLIP,
VOPTIC_OP_CMD_SSC_FLIP,
VOPTIC_OP_CMD_SSC_FLIP_UPDATE,
VOPTIC_OP_CMD_MAX
};
#endif
enum {
COMMON_DATA_SET_ABS_OFF, // 0x00 00 47 C1
COMMON_DATA_SET_ABS_ON, // 0x01 00 47 C1
#if IS_ENABLED(CONFIG_SUPPORT_VFOLD_FLEX) || defined(CONFIG_SUPPORT_VFOLD_FLEX)
COMMON_DATA_SET_MAIN_ON, // 0x02 00 47 C1
COMMON_DATA_SET_SUB_ON, // 0x03 00 47 C1
#endif
COMMON_DATA_SET_LCD_INTENT_ON = 0xf1, // 0xf1 00 47 C1
COMMON_DATA_SET_LCD_INTENT_OFF, // 0xf2 00 47 C1
};
// for ssc_core sensor type
enum {
OPTION_TYPE_SSC_CHARGING_STATE, // for pocket mode
OPTION_TYPE_SSC_ABS_LCD_TYPE, // for pocket mode
OPTION_TYPE_SSC_LCD_TYPE, // for pocket mode + auto roation
OPTION_TYPE_SSC_LCD_INTENT_TYPE, // for auto rotation
OPTION_TYPE_SSC_DUMP_TYPE, // for pocket mode
OPTION_TYPE_SSC_AOD_RECT, // for AOD
OPTION_TYPE_SSC_AOD_LIGHT_CIRCLE, // for AOD
OPTION_TYPE_SSC_LIGHT_SEAMLESS, // for light seamless
OPTION_TYPE_SSC_AUTO_ROTATION_MODE, // for auto rotation
OPTION_TYPE_SSC_SBM_INIT, // for sar backoff motion
OPTION_TYPE_SSC_WAKEUP_REASON, // for commoninfo
OPTION_TYPE_SSC_RECOVERY, // for commoninfo
OPTION_TYPE_SSC_POCKET_INJECT, // for pocket mode
OPTION_TYPE_SSC_SSR_DUMP, // for commoninfo
OPTION_TYPE_SSC_DEVICE_MODE, // for device mode
OPTION_TYPE_SSC_MAX
};
enum {
BD_SMD, //0
BD_TILT,
BD_PICKUP,
BD_SBM,
BD_WAKEUP_MOTION,
BD_PROXIMITY,
BD_CALL_GESTURE,
BD_POCKET_MODE,
BD_LED_COVER,
BD_FLIP_COVER,
BD_DROP_CLASSIFIER, // 10
BD_POCKET_PS_MODE,
BD_STEP_CNT_ALERT,
BD_FOLDING_STATE_LPM,
BD_HINGE_ANGLE,
BD_LID_ANGLE_FUSION,
BD_ANGLE_SENSOR_STATUS,
BD_SCONTEXT_START_IDX,
BD_SEM_MOVEMENT = BD_SCONTEXT_START_IDX, //17
BD_SEM_AUTO_ROTATION,
BD_SEM_WIRELESS_CHARGING_DET,
BD_SEM_PUT_DOWN_MOTION, //20
BD_SEM_SLOCATION,
BD_SEM_AMD,
BD_SEM_AOD,
BD_SEM_FLAT_MOTION,
BD_SEM_SNS_STATUS_CHECK,
BD_SEM_DEVICE_POSITION,
BD_SEM_LOC_CHANGE_TRIGGER,
BD_SEM_FREE_FALL_DET,
BD_SEM_START_ACTIVITIES,
BD_SEM_PEDOMETER = BD_SEM_START_ACTIVITIES,
BD_SEM_STEP_LEVEL_MONITOR, //30
BD_SEM_AT_NORMAL,
BD_SEM_AT_INT,
BD_SEM_AT_BATCH,
BD_SEM_AT_EXT_INT,
BD_SEM_ACTIVITY_CAL, // Activity vehicle
BD_SENSOR_MAX
};
enum {
DEVICE_MODE_FLIP_OPEN = 1, //Folding
DEVICE_MODE_RESERVED_FOR_OEM_1 = 62,
DEVICE_MODE_MAX= 63,
};
enum {
SNS_RECOVERY_SSR = 0,
SNS_RECOVERY_SSR_DUMP_ON,
SNS_RECOVERY_SSR_DUMP_OFF,
SNS_RECOVERY_SSR_DUMP_START,
SNS_RECOVERY_SSR_DUMP_COMPLETE,
SNS_RECOVERY_SSR_RECOVERY_MSG_MAX
};
enum {
SNS_TRIGGER_SKIP = 0,
SNS_TRIGGER_PANIC,
SNS_TRIGGER_SSR,
SNS_TRIGGER_SSR_DUMP,
SNS_TRIGGER_MAX
};
#endif

18
include/linux/adsp/slpi-loader.h Executable file
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@@ -0,0 +1,18 @@
/* Copyright (c) 2012-2013, 2015 The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _SLPI_LOADER_H_
#define _SLPI_LOADER_H_
#ifdef CONFIG_DSP_SLEEP_RECOVERY
int slpi_ssr(void);
#endif
#endif

6
include/linux/adsp/ssc_ssr_reason.h Executable file
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@@ -0,0 +1,6 @@
#ifndef SSC_SSR_REASON_H
#define SSC_SSR_REASON_H
void ssr_reason_call_back(char reason[], int len);
bool ssc_get_fssr_ignore(void);
#endif /* SSP_MOTOR_H */

50
include/linux/battery/sb_def.h Normal file
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/*
* sb_def.h
* Samsung Mobile Battery DEF Header
*
* Copyright (C) 2012 Samsung Electronics, Inc.
*
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __SB_DEF_H
#define __SB_DEF_H __FILE__
enum sb_dev_type {
SB_DEV_UNKNOWN = 0,
SB_DEV_BATTERY,
SB_DEV_DIRECT_CHARGER,
SB_DEV_DUAL_BATTERY,
SB_DEV_CHARGER,
SB_DEV_FUEL_GAUGE,
SB_DEV_WIRELESS_CHARGER,
SB_DEV_LIMITTER,
SB_DEV_DIVIDER,
SB_DEV_MODULE,
SB_DEV_MAX,
};
typedef unsigned long long sb_data;
#define cast_to_sb_data(data) ((sb_data)(data))
#define cast_to_sb_pdata(data) ((sb_data *)(data))
#define cast_sb_data(type, data) ((type)(data))
#define cast_sb_data_ptr(type, data) ((type *)(data))
#define cast_sb_pdata(type, pdata) ((type)(*pdata))
#define cast_sb_pdata_ptr(type, pdata) ((type *)(*pdata))
#endif /* __SB_DEF_H */

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