Add qcom-spmi-temp-alarm devices for the TEMP_ALARM and TEMP_ALARM_LITE
PMIC peripherals found in PMICs PM8550VE_D, PM8550VE_G, PM8550VS_F,
PM8550VS_J, PMIH010X, and PMD802X which are used on Sun boards. Each
TEMP_ALARM device can monitor the die temperature of a particular PMIC.
Change-Id: I3e29ec91f50a5c27d4a8e581c9c17ad3ae09d187
Signed-off-by: David Collins <quic_collinsd@quicinc.com>
Specify a pinctrl configuration for PMK8550 GPIO 3 to enable
alt_sleep_clk output so that clients like WLAN and BT can
function properly.
Change-Id: I74506946647b55e391a8c848c44ccf20af966739
Signed-off-by: Subbaraman Narayanamurthy <quic_subbaram@quicinc.com>
Bindings for fastrpc nodes and the child nodes.
Change-Id: Ic967b92d2324d5f9671614f62973c5f9820d6b4b
Signed-off-by: Gokul krishna Krishnakumar <quic_gokukris@quicinc.com>
Correct the following pcie1 dt property names on pineapple
device as they are modified for this latest kernel devicetree
documentation.
clock-frequency -> qcom,pcie-clock-frequency.
Change-Id: I048275f388f31fe71b157f1f9ab4aaf5eec6131b
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Update qcom,spmi-vadc bindings to include "qcom,scale-fn-type"
property for ADC7.
Change-Id: Ieb8ad5779b078dd77838c498b3a4e0bbcf907df8
Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com>
[quic_amelende@quicinc.com: Converted binding change from .txt to .yaml
and removed changes already captured in yaml]
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
Following device tree register addresses change from upstream commit
ee13b50 ("qcom: llcc/edac: Fix the base address used for accessing LLCC
banks").
Change LLCC bindings for Pineapple and Sun SoC.
Change-Id: I60bdfd7e4bc19343a3eb6a1c0c597523f1c30963
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
Based on upstream commit ee13b50 ("qcom: llcc/edac: Fix the base address
used for accessing LLCC banks"), the devicetree needs to be updated with
LLCC bank 0 through 3, instead of just the start LLCC bank 0 and the end
LLCC broadcast.
Change-Id: I1d2b758693f6a71338653fa677dbb833299475c6
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
Based on upstream commit ee13b50 ("qcom: llcc/edac: Fix the base address
used for accessing LLCC banks"), the devicetree needs to be updated with
LLCC bank 0 through 3, instead of just the start LLCC bank 0 and the end
LLCC broadcast.
Change-Id: I7c2b62697721074660c6b7371e0d2b1bf195ba5d
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
Add a gpio-keys device for Sun MTP, CDP and QRD boards that use
PM8550 GPIO 6.
Change-Id: I3b6ec4f7cb826cd482e85cdbbcbea3db485284c1
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
Add the LPG LED device for sun platforms. Currently, pm8550 LED
devices use the downstream leds-qti-tri-led driver. Update the LED
devices so that they use the upstream leds-qcom-lpg driver.
Change-Id: I6e9c80d9e7725e5978fbc8bebf02a7d66968d32e
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
The clock required to access this GDSC depends on a clock coming from
GPU_CC, which is enabled by default in gpucc probe. Add a phandle to
gpucc to ensure it probes first and enables the required clock.
Change-Id: I5aae1a6a1a3615cf1a8227b839a721a6af945243
Signed-off-by: Mike Tipton <quic_mdtipton@quicinc.com>
Correct the following pcie dt property names on pineapple
device as they are modified for this latest kernel devicetree
documentation.
qcom,pcie-clkreq-gpio -> qcom,pcie-clkreq-pin.
clock-frequency -> qcom,pcie-clock-frequency.
Change-Id: I79454ef04a69d5427e32c45042304809cdcb886c
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Enable tlmm VM mem access device tree nodes for Pineapple.
Change-Id: I2bfbc22e8f9e933e3d0ec419b3fa67ff89b4fdad
Signed-off-by: Hrishabh Rajput <quic_hrishabh@quicinc.com>
Sun and pineapple share certain PMICs. Prepare the shared PMIC devices
to be used for both Sun and Pineapple.
Change-Id: I378e781751b4ee42b3c0d4940dff30ffbd2b3e5a
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
Update the Qualcomm Technologies, INC. PMIC GPIO binding documentation
to include compatible strings for PMIH010x and PMD802x PMICs.
Change-Id: Icf07b2f657d0e6fd104ae36553d1631caadcdb70
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
Update prescale ratios to support the new channels.
Change-Id: I4d37e9653962954e856f464df32297d9aa90757a
Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com>
[quic_amelende@quicinc.com: Converted binding change from .txt to .yaml]
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
Update compatible string to support ADC channels that are registered to
thermal framework, without registering interrupts.
Change-Id: Ie2a1d59272434453c27f2daa2b758ab8a6c96db2
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
Add device tree files needed to support Sun SoC + Kiwi platforms.
Change-Id: Ie27eea504087f8da315ab6b0e90d1660d32e3815
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
Add spmi-pmic-arb devices for the primary and secondary SPMI buses
found on Sun. The primary bus operates at 19.2 MHz and is used for
most of the PMICs.
The secondary bus operates at 4.8 MHz and is used exclusively for
charging PMICs. Note that the secondary bus is not connected to
the SoC on the board due to voltage level differences. Therefore,
keep the secondary bus device disabled.
Change-Id: I6b2bb6b54e285fd9c333971b08134c3768087869
Signed-off-by: David Collins <quic_collinsd@quicinc.com>
Add base TUIVM and OEMVM device tree support for Sun RUMI platform.
Change-Id: I32598ce2c3488658e2c9caf0cd7a2368665c0b06
Signed-off-by: Meena Pasumarthi <quic_pasumart@quicinc.com>
Signed-off-by: Sahitya Tummala <quic_stummala@quicinc.com>
Add base TUIVM and OEMVM device tree support for all Pineapple platforms.
Change-Id: I7c3cc2112e122f25a2f0b573128e8fdfb86975c5
Signed-off-by: Meena Pasumarthi <quic_pasumart@quicinc.com>
Signed-off-by: Hrishabh Rajput <quic_hrishabh@quicinc.com>
Adding bindings to support vm on Sun.
This is snapshot of bindings from 'commit 999a92cd8b38
("Merge "ARM: dts: qcom: Add platform support for VMs on
Cliffs"")' from device tree project msm-6.1 branch.
Change-Id: I47eda741b3451d38d215f7d95505a2bb4dd86565
Signed-off-by: Meena Pasumarthi <quic_pasumart@quicinc.com>
Signed-off-by: Sahitya Tummala <quic_stummala@quicinc.com>
Add device tree entries for smcinvoke, shmbridge and tz-log
drivers and qseecom heaps.
Change-Id: I1a427c66e12a02532097db352a1d26fe5ececb9f
Signed-off-by: Anmolpreet Kaur <quic_anmolpre@quicinc.com>
Add initial devicetree nodes and entries to support
PCIe RC0 port configuration on sun.
Change-Id: I3b7419bfd376a51388785cc4e2f9702ddaabe397
Signed-off-by: Lazarus Motha <quic_lmotha@quicinc.com>
