ARM: dts: msm: Fix the base addresses of LLCC banks for Sun SoC
Based on upstream commit ee13b50 ("qcom: llcc/edac: Fix the base address used for accessing LLCC banks"), the devicetree needs to be updated with LLCC bank 0 through 3, instead of just the start LLCC bank 0 and the end LLCC broadcast. Change-Id: I1d2b758693f6a71338653fa677dbb833299475c6 Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
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@@ -455,8 +455,11 @@
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cache-controller@24800000 {
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compatible = "qcom,sun-llcc";
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reg = <0x24800000 0x2000000> , <0x26800000 0x200000>;
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reg-names = "llcc_base", "llcc_broadcast_base";
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reg = <0x24800000 0x200000>, <0x25800000 0x200000>,
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<0x24C00000 0x200000>, <0x25C00000 0x200000>,
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<0x26800000 0x200000>;
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reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
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"llcc3_base", "llcc_broadcast_base";
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interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
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cap-based-alloc-and-pwr-collapse;
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};
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