ARM: dts: msm: Fix the base addresses of LLCC banks for Sun SoC

Based on upstream commit ee13b50 ("qcom: llcc/edac: Fix the base address
used for accessing LLCC banks"), the devicetree needs to be updated with
LLCC bank 0 through 3, instead of just the start LLCC bank 0 and the end
LLCC broadcast.

Change-Id: I1d2b758693f6a71338653fa677dbb833299475c6
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
This commit is contained in:
Unnathi Chalicheemala
2023-09-29 11:50:39 -07:00
parent 989e04083d
commit 04b52df658

View File

@@ -455,8 +455,11 @@
cache-controller@24800000 {
compatible = "qcom,sun-llcc";
reg = <0x24800000 0x2000000> , <0x26800000 0x200000>;
reg-names = "llcc_base", "llcc_broadcast_base";
reg = <0x24800000 0x200000>, <0x25800000 0x200000>,
<0x24C00000 0x200000>, <0x25C00000 0x200000>,
<0x26800000 0x200000>;
reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
"llcc3_base", "llcc_broadcast_base";
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
cap-based-alloc-and-pwr-collapse;
};