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ARM: dts: qcom: add SPMI bus controller for Sun

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Add spmi-pmic-arb devices for the primary and secondary SPMI buses
found on Sun.  The primary bus operates at 19.2 MHz and is used for
most of the PMICs.

The secondary bus operates at 4.8 MHz and is used exclusively for
charging PMICs.  Note that the secondary bus is not connected to
the SoC on the board due to voltage level differences.  Therefore,
keep the secondary bus device disabled.

Change-Id: I6b2bb6b54e285fd9c333971b08134c3768087869
Signed-off-by: David Collins <quic_collinsd@quicinc.com>
This commit is contained in:
David Collins
2023-09-13 14:30:00 -07:00
parent 8e96b50796
commit 0d4bfb44d3
1 changed files with 42 additions and 0 deletions
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42
qcom/sun.dtsi
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@@ -1352,6 +1352,48 @@
msm_gpu: qcom,kgsl-3d0@3d00000 { };
spmi_bus: spmi0_bus: qcom,spmi@c42d000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0xc42d000 0x4000>,
<0xc400000 0x3000>,
<0xc500000 0x400000>,
<0xc440000 0x80000>,
<0xc4c0000 0x10000>;
reg-names = "cnfg", "core", "chnls", "obsrvr", "intr";
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "periph_irq";
interrupt-controller;
#interrupt-cells = <4>;
#address-cells = <2>;
#size-cells = <0>;
cell-index = <0>;
qcom,channel = <0>;
qcom,ee = <0>;
qcom,bus-id = <0>;
};
spmi1_bus: qcom,spmi@c432000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0xc432000 0x4000>,
<0xc400000 0x3000>,
<0xc500000 0x400000>,
<0xc440000 0x80000>,
<0xc4d0000 0x10000>;
reg-names = "cnfg", "core", "chnls", "obsrvr", "intr";
interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "periph_irq";
interrupt-controller;
#interrupt-cells = <4>;
#address-cells = <2>;
#size-cells = <0>;
cell-index = <0>;
qcom,channel = <0>;
qcom,ee = <0>;
qcom,bus-id = <1>;
depends-on-supply = <&spmi0_bus>;
status = "disabled";
};
qcom,msm-adsprpc-mem {
compatible = "qcom,msm-adsprpc-mem-region";
memory-region = <&adsp_mem_heap>;