0d4bfb44d3
Add spmi-pmic-arb devices for the primary and secondary SPMI buses found on Sun. The primary bus operates at 19.2 MHz and is used for most of the PMICs. The secondary bus operates at 4.8 MHz and is used exclusively for charging PMICs. Note that the secondary bus is not connected to the SoC on the board due to voltage level differences. Therefore, keep the secondary bus device disabled. Change-Id: I6b2bb6b54e285fd9c333971b08134c3768087869 Signed-off-by: David Collins <quic_collinsd@quicinc.com>
1678 lines
40 KiB
Plaintext
1678 lines
40 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,cambistmclkcc-sun.h>
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#include <dt-bindings/clock/qcom,camcc-sun.h>
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#include <dt-bindings/clock/qcom,dispcc-sun.h>
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#include <dt-bindings/clock/qcom,evacc-sun.h>
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#include <dt-bindings/clock/qcom,gcc-sun.h>
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#include <dt-bindings/clock/qcom,gpucc-sun.h>
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#include <dt-bindings/clock/qcom,gxclkctl-sun.h>
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#include <dt-bindings/clock/qcom,tcsrcc-sun.h>
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#include <dt-bindings/clock/qcom,videocc-sun.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interconnect/qcom,sun.h>
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#include <dt-bindings/soc/qcom,ipcc.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/power/qcom-aoss-qmp.h>
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/ {
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model = "Qualcomm Technologies, Inc. Sun";
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compatible = "qcom,sun";
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qcom,msm-id = <618 0x10000>;
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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memory { device_type = "memory"; reg = <0 0 0 0>; };
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chosen: chosen {
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bootargs = "nokaslr kpti=0 log_buf_len=256K swiotlb=0 loop.max_part=7";
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stdout-path = "/soc/qcom,qupv3_1_geni_se@ac0000/qcom,qup_uart@a9c000:115200n8";
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};
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aliases: aliases {
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serial0 = &qupv3_se7_2uart;
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ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
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sdhc2 = &sdhc_2;
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};
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firmware: firmware { };
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x100>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x200>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x300>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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};
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CPU4: cpu@400 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x400>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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};
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CPU5: cpu@500 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x500>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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};
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CPU6: cpu@10000 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x10000>;
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enable-method = "psci";
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next-level-cache = <&L2_6>;
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L2_6: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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};
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};
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CPU7: cpu@10100 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x10100>;
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enable-method = "psci";
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next-level-cache = <&L2_6>;
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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core4 {
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cpu = <&CPU4>;
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};
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core5 {
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cpu = <&CPU5>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU6>;
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};
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core1 {
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cpu = <&CPU7>;
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};
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};
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};
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};
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reserved_memory: reserved-memory { };
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soc: soc { };
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};
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&firmware {
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qcom-scm {
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compatible = "qcom,scm";
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};
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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ipcc_mproc: qcom,ipcc@406000 {
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compatible = "qcom,ipcc";
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reg = <0x406000 0x1000>;
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interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <3>;
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#mbox-cells = <2>;
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};
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tcsr_mutex_block: syscon@1f40000 {
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compatible = "syscon";
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reg = <0x1f40000 0x20000>;
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};
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tcsr: syscon@1fc0000 {
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compatible = "syscon";
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reg = <0x1fc0000 0x30000>;
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};
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tcsr_mutex: hwlock {
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compatible = "qcom,tcsr-mutex";
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syscon = <&tcsr_mutex_block 0 0x1000>;
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#hwlock-cells = <1>;
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};
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pdc: interrupt-controller@b220000 {
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compatible = "qcom,sun-pdc", "qcom,pdc";
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reg = <0xb220000 0x10000>, <0x164400F0 0x64>;
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qcom,pdc-ranges = <0 745 51>, <51 527 47>,
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<98 609 32>, <130 717 12>,
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<142 251 5>, <147 796 16>;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupt-controller;
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};
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aoss_qmp: power-controller@c300000 {
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compatible = "qcom,aoss-qmp";
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reg = <0xc300000 0x400>;
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interrupt-parent = <&ipcc_mproc>;
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interrupts = <IPCC_CLIENT_AOP
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IPCC_MPROC_SIGNAL_GLINK_QMP
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc_mproc IPCC_CLIENT_AOP
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IPCC_MPROC_SIGNAL_GLINK_QMP>;
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#power-domain-cells = <1>;
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#clock-cells = <0>;
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};
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qmp_tme: qcom,qmp-tme {
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compatible = "qcom,qmp-mbox";
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qcom,remote-pid = <14>;
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mboxes = <&ipcc_mproc IPCC_CLIENT_TME
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IPCC_MPROC_SIGNAL_GLINK_QMP>;
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mbox-names = "tme_qmp";
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interrupt-parent = <&ipcc_mproc>;
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interrupts = <IPCC_CLIENT_TME
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IPCC_MPROC_SIGNAL_GLINK_QMP
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IRQ_TYPE_EDGE_RISING>;
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label = "tme";
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qcom,early-boot;
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priority = <0>;
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mbox-desc-offset = <0x0>;
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#mbox-cells = <1>;
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};
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qcom,smp2p-adsp {
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compatible = "qcom,smp2p";
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qcom,smem = <443>, <429>;
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interrupt-parent = <&ipcc_mproc>;
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interrupts = <IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
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IPCC_MPROC_SIGNAL_SMP2P>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <2>;
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adsp_smp2p_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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adsp_smp2p_in: slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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sleepstate_smp2p_out: sleepstate-out {
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qcom,entry-name = "sleepstate";
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#qcom,smem-state-cells = <1>;
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};
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sleepstate_smp2p_in: qcom,sleepstate-in {
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qcom,entry-name = "sleepstate_see";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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qcom,smp2p-cdsp {
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compatible = "qcom,smp2p";
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qcom,smem = <94>, <432>;
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interrupt-parent = <&ipcc_mproc>;
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interrupts = <IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <5>;
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cdsp_smp2p_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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cdsp_smp2p_in: slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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qcom,smp2p-modem {
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compatible = "qcom,smp2p";
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qcom,smem = <435>, <428>;
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interrupt-parent = <&ipcc_mproc>;
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interrupts = <IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <1>;
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modem_smp2p_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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modem_smp2p_in: slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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qcom,smp2p-soccp {
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compatible = "qcom,smp2p";
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qcom,smem = <617>, <616>;
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interrupt-parent = <&ipcc_mproc>;
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interrupts = <IPCC_CLIENT_SOCCP IPCC_MPROC_SIGNAL_SMP2P
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc_mproc IPCC_CLIENT_SOCCP IPCC_MPROC_SIGNAL_SMP2P>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <19>;
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soccp_smp2p_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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soccp_smp2p_in: slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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tlmm: pinctrl@f000000 {
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compatible = "qcom,sun-tlmm";
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reg = <0xf000000 0x202000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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wakeup-parent = <&pdc>;
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};
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intc: interrupt-controller@16000000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x40000>;
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reg = <0x16000000 0x10000>, /* GICD */
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<0x16080000 0x200000>; /* GICR * 8 */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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memtimer: timer@16800000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0x16800000 0x1000>;
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clock-frequency = <19200000>;
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frame@16801000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x16801000 0x1000>,
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<0x16802000 0x1000>;
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};
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frame@16803000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x16803000 0x1000>;
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status = "disabled";
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};
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frame@16805000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x16805000 0x1000>;
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status = "disabled";
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};
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frame@16807000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x16807000 0x1000>;
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status = "disabled";
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};
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frame@16809000 {
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frame-number = <4>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x16809000 0x1000>;
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status = "disabled";
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};
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frame@1680b000 {
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frame-number = <5>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x1680b000 0x1000>;
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status = "disabled";
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};
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frame@1680d000 {
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frame-number = <6>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x1680d000 0x1000>;
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status = "disabled";
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};
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};
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eud: qcom,msm-eud@88e0000 {
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compatible = "qcom,msm-eud";
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interrupt-names = "eud_irq";
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interrupts = <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x88e0000 0x2000>,
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<0x88e2000 0x1000>;
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reg-names = "eud_base", "eud_mode_mgr2";
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qcom,secure-eud-en;
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status = "ok";
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};
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cache-controller@24800000 {
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compatible = "qcom,sun-llcc";
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reg = <0x24800000 0x2000000> , <0x26800000 0x200000>;
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reg-names = "llcc_base", "llcc_broadcast_base";
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interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
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cap-based-alloc-and-pwr-collapse;
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};
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qcom,secure-buffer {
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compatible = "qcom,secure-buffer";
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qcom,vmid-cp-camera-preview-ro;
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};
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qcom,mem-buf {
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compatible = "qcom,mem-buf";
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qcom,mem-buf-capabilities = "supplier";
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qcom,vmid = <3>;
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};
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qcom,mem-buf-msgq {
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compatible = "qcom,mem-buf-msgq";
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <19200000>;
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};
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qcom_tzlog: tz-log@0 {
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};
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clk_virt: interconnect@0 {
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compatible = "qcom,sun-clk_virt";
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#interconnect-cells = <1>;
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qcom,bcm-voter-names = "hlos";
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qcom,bcm-voters = <&apps_bcm_voter>;
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qcom,disabled-voters = "pcie_crm_hw_0", "pcie_crm_hw_1";
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};
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mc_virt: interconnect@1 {
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compatible = "qcom,sun-mc_virt";
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#interconnect-cells = <1>;
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qcom,bcm-voter-names = "hlos";
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qcom,bcm-voters = <&apps_bcm_voter>;
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qcom,disabled-voters = "disp",
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"cam_ife_0",
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"cam_ife_1",
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"cam_ife_2",
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"pcie_crm_hw_0",
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"pcie_crm_hw_1";
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};
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config_noc: interconnect@1600000 {
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compatible = "qcom,sun-cnoc_cfg";
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|
reg = <0x1600000 0x6200>;
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
cnoc_main: interconnect@1500000 {
|
|
compatible = "qcom,sun-cnoc_main";
|
|
reg = <0x1500000 0x16080>;
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
system_noc: interconnect@1680000 {
|
|
compatible = "qcom,sun-system_noc";
|
|
reg = <0x1680000 0x1d080>;
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
pcie_noc: interconnect@16c0000 {
|
|
compatible = "qcom,sun-pcie_anoc";
|
|
reg = <0x16c0000 0x11400>;
|
|
#interconnect-cells = <1>;
|
|
clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
|
|
<&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
qcom,disabled-voters = "pcie_crm_hw_0", "pcie_crm_hw_1";
|
|
qcom,skip-qos;
|
|
};
|
|
|
|
aggre1_noc: interconnect@16e0000 {
|
|
compatible = "qcom,sun-aggre1_noc";
|
|
reg = <0x16e0000 0x16400>;
|
|
#interconnect-cells = <1>;
|
|
clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
|
|
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
qcom,skip-qos;
|
|
};
|
|
|
|
aggre2_noc: interconnect@1700000 {
|
|
compatible = "qcom,sun-aggre2_noc";
|
|
reg = <0x1700000 0x1f400>;
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
clocks = <&rpmhcc RPMH_IPA_CLK>;
|
|
qcom,skip-qos;
|
|
};
|
|
|
|
mmss_noc: interconnect@1780000 {
|
|
compatible = "qcom,sun-mmss_noc";
|
|
reg = <0x1780000 0x5b800>;
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
qcom,disabled-voters = "disp", "cam_ife_0", "cam_ife_1", "cam_ife_2";
|
|
qcom,skip-qos;
|
|
};
|
|
|
|
gem_noc: interconnect@24100000 {
|
|
compatible = "qcom,sun-gem_noc";
|
|
reg = <0x24100000 0x14b080>;
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
qcom,disabled-voters = "disp",
|
|
"cam_ife_0",
|
|
"cam_ife_1",
|
|
"cam_ife_2",
|
|
"pcie_crm_hw_0",
|
|
"pcie_crm_hw_1";
|
|
qcom,skip-qos;
|
|
};
|
|
|
|
nsp_noc: interconnect@320c0000 {
|
|
compatible = "qcom,sun-nsp_noc";
|
|
reg = <0x320c0000 0x13080>;
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
lpass_ag_noc: interconnect@7e40000 {
|
|
compatible = "qcom,sun-lpass_ag_noc";
|
|
reg = <0x7e40000 0xe080>;
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
lpass_lpiaon_noc: interconnect@7400000 {
|
|
compatible = "qcom,sun-lpass_lpiaon_noc";
|
|
reg = <0x7400000 0x19080>;
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
lpass_lpicx_noc: interconnect@7420000 {
|
|
compatible = "qcom,sun-lpass_lpicx_noc";
|
|
reg = <0x7420000 0x44080>;
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
apps_rsc: rsc@16500000 {
|
|
label = "apps_rsc";
|
|
compatible = "qcom,rpmh-rsc";
|
|
reg = <0x16500000 0x10000>,
|
|
<0x16510000 0x10000>,
|
|
<0x16520000 0x10000>;
|
|
reg-names = "drv-0", "drv-1", "drv-2";
|
|
qcom,drv-count = <3>;
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
apps_rsc_drv2: drv@2 {
|
|
qcom,drv-id = <2>;
|
|
qcom,tcs-offset = <0xd00>;
|
|
channel@0 {
|
|
qcom,tcs-config = <ACTIVE_TCS 3>,
|
|
<SLEEP_TCS 2>,
|
|
<WAKE_TCS 2>,
|
|
<CONTROL_TCS 0>,
|
|
<FAST_PATH_TCS 1>;
|
|
};
|
|
apps_bcm_voter: bcm_voter {
|
|
compatible = "qcom,bcm-voter";
|
|
};
|
|
};
|
|
};
|
|
|
|
clocks {
|
|
xo_board: xo_board {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <76800000>;
|
|
clock-output-names = "xo_board";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
sleep_clk: sleep_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <32000>;
|
|
clock-output-names = "sleep_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
pcie_0_pipe_clk: pcie_0_pipe_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "pcie_0_pipe_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
ufs_phy_rx_symbol_0_clk: ufs_phy_rx_symbol_0_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "ufs_phy_rx_symbol_0_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
ufs_phy_rx_symbol_1_clk: ufs_phy_rx_symbol_1_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "ufs_phy_rx_symbol_1_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
ufs_phy_tx_symbol_0_clk: ufs_phy_tx_symbol_0_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "ufs_phy_tx_symbol_0_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
};
|
|
|
|
cxo: bi_tcxo {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&xo_board>;
|
|
clock-mult = <1>;
|
|
clock-div = <4>;
|
|
#clock-cells = <0>;
|
|
clock-output-names = "bi_tcxo";
|
|
};
|
|
|
|
cxo_a: bi_tcxo_ao {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&xo_board>;
|
|
clock-mult = <1>;
|
|
clock-div = <4>;
|
|
#clock-cells = <0>;
|
|
clock-output-names = "bi_tcxo_ao";
|
|
};
|
|
|
|
rpmhcc: clock-controller {
|
|
compatible = "fixed-clock";
|
|
clock-output-names = "rpmh_clocks";
|
|
clock-frequency = <19200000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
cambistmclkcc: clock-controller@1760000 {
|
|
compatible = "qcom,sun-cambistmclkcc", "syscon";
|
|
reg = <0x1760000 0x6000>;
|
|
reg-name = "cc_base";
|
|
vdd_mx-supply = <&VDD_MX_LEVEL>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&sleep_clk>,
|
|
<&gcc GCC_CAM_BIST_MCLK_AHB_CLK>;
|
|
clock-names = "bi_tcxo",
|
|
"sleep_clk",
|
|
"iface";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
camcc: clock-controller@ade0000 {
|
|
compatible = "qcom,sun-camcc", "syscon";
|
|
reg = <0xade0000 0x20000>;
|
|
reg-name = "cc_base";
|
|
vdd_mm-supply = <&VDD_MM_LEVEL>;
|
|
vdd_mx-supply = <&VDD_MX_LEVEL>;
|
|
vdd_mxc-supply = <&VDD_MXC_LEVEL>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK_A>,
|
|
<&sleep_clk>,
|
|
<&gcc GCC_CAMERA_AHB_CLK>;
|
|
clock-names = "bi_tcxo",
|
|
"bi_tcxo_ao",
|
|
"sleep_clk",
|
|
"iface";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
dispcc: clock-controller@af00000 {
|
|
compatible = "qcom,sun-dispcc", "syscon";
|
|
reg = <0xaf00000 0x20000>;
|
|
reg-name = "cc_base";
|
|
vdd_mm-supply = <&VDD_MM_LEVEL>;
|
|
vdd_mx-supply = <&VDD_MX_LEVEL>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK_A>,
|
|
<&sleep_clk>,
|
|
<&gcc GCC_DISP_AHB_CLK>;
|
|
clock-names = "bi_tcxo",
|
|
"bi_tcxo_ao",
|
|
"sleep_clk",
|
|
"iface";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
evacc: clock-controller@abf0000 {
|
|
compatible = "qcom,sun-evacc", "syscon";
|
|
reg = <0xabf0000 0x10000>;
|
|
reg-name = "cc_base";
|
|
vdd_mm-supply = <&VDD_MM_LEVEL>;
|
|
vdd_mxc-supply = <&VDD_MXC_LEVEL>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK_A>,
|
|
<&sleep_clk>,
|
|
<&gcc GCC_EVA_AHB_CLK>;
|
|
clock-names = "bi_tcxo",
|
|
"bi_tcxo_ao",
|
|
"sleep_clk",
|
|
"iface";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
gcc: clock-controller@100000 {
|
|
compatible = "qcom,sun-gcc", "syscon";
|
|
reg = <0x100000 0x1f4200>;
|
|
reg-name = "cc_base";
|
|
vdd_cx-supply = <&VDD_CX_LEVEL>;
|
|
vdd_mx-supply = <&VDD_MX_LEVEL>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&pcie_0_pipe_clk>,
|
|
<&sleep_clk>,
|
|
<&ufs_phy_rx_symbol_0_clk>,
|
|
<&ufs_phy_rx_symbol_1_clk>,
|
|
<&ufs_phy_tx_symbol_0_clk>,
|
|
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
|
|
clock-names = "bi_tcxo",
|
|
"pcie_0_pipe_clk",
|
|
"sleep_clk",
|
|
"ufs_phy_rx_symbol_0_clk",
|
|
"ufs_phy_rx_symbol_1_clk",
|
|
"ufs_phy_tx_symbol_0_clk",
|
|
"usb3_phy_wrapper_gcc_usb30_pipe_clk";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
gpucc: clock-controller@3d90000 {
|
|
compatible = "qcom,sun-gpucc", "syscon";
|
|
reg = <0x3d90000 0x9800>;
|
|
reg-name = "cc_base";
|
|
vdd_cx-supply = <&VDD_CX_LEVEL>;
|
|
vdd_mx-supply = <&VDD_MX_LEVEL>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
|
|
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
|
|
clock-names = "bi_tcxo",
|
|
"gpll0_out_main",
|
|
"gpll0_out_main_div";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
gxclkctl: clock-controller@3d64000 {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "gxclkctl_clocks";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
tcsrcc: clock-controller@f204008 {
|
|
compatible = "qcom,sun-tcsrcc", "syscon";
|
|
reg = <0xf204008 0x3004>;
|
|
reg-name = "cc_base";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
videocc: clock-controller@aaf0000 {
|
|
compatible = "qcom,sun-videocc", "syscon";
|
|
reg = <0xaaf0000 0x10000>;
|
|
reg-name = "cc_base";
|
|
vdd_mm-supply = <&VDD_MM_LEVEL>;
|
|
vdd_mxc-supply = <&VDD_MXC_LEVEL>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK_A>,
|
|
<&sleep_clk>,
|
|
<&gcc GCC_VIDEO_AHB_CLK>;
|
|
clock-names = "bi_tcxo",
|
|
"bi_tcxo_ao",
|
|
"sleep_clk",
|
|
"iface";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
apsscc: syscon@16450000 {
|
|
compatible = "syscon";
|
|
reg = <0x16450000 0x3553000>;
|
|
};
|
|
|
|
mccc: syscon@240ba000 {
|
|
compatible = "syscon";
|
|
reg = <0x240ba000 0x800>;
|
|
};
|
|
|
|
/* CAM_CC GDSCs */
|
|
cam_cc_ipe_0_gdsc: qcom,gdsc@adf017c {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xadf017c 0x4>;
|
|
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
|
regulator-name = "cam_cc_ipe_0_gdsc";
|
|
parent-supply = <&cam_cc_titan_top_gdsc>;
|
|
qcom,retain-regs;
|
|
qcom,support-hw-trigger;
|
|
qcom,support-cfg-gdscr;
|
|
};
|
|
|
|
cam_cc_ofe_gdsc: qcom,gdsc@adf00c8 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xadf00c8 0x4>;
|
|
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
|
regulator-name = "cam_cc_ofe_gdsc";
|
|
parent-supply = <&cam_cc_titan_top_gdsc>;
|
|
qcom,retain-regs;
|
|
qcom,support-hw-trigger;
|
|
qcom,support-cfg-gdscr;
|
|
};
|
|
|
|
cam_cc_tfe_0_gdsc: qcom,gdsc@adf1004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xadf1004 0x4>;
|
|
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
|
regulator-name = "cam_cc_tfe_0_gdsc";
|
|
parent-supply = <&cam_cc_titan_top_gdsc>;
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
};
|
|
|
|
cam_cc_tfe_1_gdsc: qcom,gdsc@adf1084 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xadf1084 0x4>;
|
|
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
|
regulator-name = "cam_cc_tfe_1_gdsc";
|
|
parent-supply = <&cam_cc_titan_top_gdsc>;
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
};
|
|
|
|
cam_cc_tfe_2_gdsc: qcom,gdsc@adf10ec {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xadf10ec 0x4>;
|
|
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
|
regulator-name = "cam_cc_tfe_2_gdsc";
|
|
parent-supply = <&cam_cc_titan_top_gdsc>;
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
};
|
|
|
|
cam_cc_titan_top_gdsc: qcom,gdsc@adf134c {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xadf134c 0x4>;
|
|
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
|
regulator-name = "cam_cc_titan_top_gdsc";
|
|
parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
};
|
|
|
|
/* DISP_CC GDSCs */
|
|
disp_cc_mdss_core_gdsc: qcom,gdsc@af09000 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xaf09000 0x4>;
|
|
clocks = <&gcc GCC_DISP_AHB_CLK>;
|
|
regulator-name = "disp_cc_mdss_core_gdsc";
|
|
parent-supply = <&VDD_MM_LEVEL>;
|
|
proxy-supply = <&disp_cc_mdss_core_gdsc>;
|
|
qcom,proxy-consumer-enable;
|
|
qcom,retain-regs;
|
|
qcom,support-hw-trigger;
|
|
qcom,support-cfg-gdscr;
|
|
};
|
|
|
|
disp_cc_mdss_core_int2_gdsc: qcom,gdsc@af0b000 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xaf0b000 0x4>;
|
|
clocks = <&gcc GCC_DISP_AHB_CLK>;
|
|
regulator-name = "disp_cc_mdss_core_int2_gdsc";
|
|
parent-supply = <&VDD_MM_LEVEL>;
|
|
qcom,retain-regs;
|
|
qcom,support-hw-trigger;
|
|
qcom,support-cfg-gdscr;
|
|
};
|
|
|
|
/* EVA_CC GDSCs */
|
|
eva_cc_mvs0_gdsc: qcom,gdsc@abf8068 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xabf8068 0x4>;
|
|
clocks = <&gcc GCC_EVA_AHB_CLK>;
|
|
regulator-name = "eva_cc_mvs0_gdsc";
|
|
parent-supply = <&eva_cc_mvs0c_gdsc>;
|
|
qcom,retain-regs;
|
|
qcom,support-hw-trigger;
|
|
qcom,support-cfg-gdscr;
|
|
};
|
|
|
|
eva_cc_mvs0c_gdsc: qcom,gdsc@abf8034 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xabf8034 0x4>;
|
|
clocks = <&gcc GCC_EVA_AHB_CLK>;
|
|
regulator-name = "eva_cc_mvs0c_gdsc";
|
|
parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
};
|
|
|
|
gcc_apcs_gdsc_vote_ctrl: syscon@15214c {
|
|
compatible = "syscon";
|
|
reg = <0x15214c 0x4>;
|
|
};
|
|
|
|
/* GCC GDSCs */
|
|
gcc_pcie_0_gdsc: qcom,gdsc@16b004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x16b004 0x4>;
|
|
regulator-name = "gcc_pcie_0_gdsc";
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
qcom,retain-regs;
|
|
qcom,no-status-check-on-disable;
|
|
qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 0>;
|
|
qcom,support-cfg-gdscr;
|
|
};
|
|
|
|
gcc_pcie_0_phy_gdsc: qcom,gdsc@16c000 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x16c000 0x4>;
|
|
regulator-name = "gcc_pcie_0_phy_gdsc";
|
|
parent-supply = <&VDD_MX_LEVEL>;
|
|
qcom,retain-regs;
|
|
qcom,no-status-check-on-disable;
|
|
qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 2>;
|
|
qcom,support-cfg-gdscr;
|
|
};
|
|
|
|
gcc_ufs_mem_phy_gdsc: qcom,gdsc@19e000 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x19e000 0x4>;
|
|
regulator-name = "gcc_ufs_mem_phy_gdsc";
|
|
parent-supply = <&VDD_MX_LEVEL>;
|
|
proxy-supply = <&gcc_ufs_mem_phy_gdsc>;
|
|
qcom,proxy-consumer-enable;
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
};
|
|
|
|
gcc_ufs_phy_gdsc: qcom,gdsc@177004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x177004 0x4>;
|
|
regulator-name = "gcc_ufs_phy_gdsc";
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
proxy-supply = <&gcc_ufs_phy_gdsc>;
|
|
qcom,proxy-consumer-enable;
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
};
|
|
|
|
gcc_usb30_prim_gdsc: qcom,gdsc@139004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x139004 0x4>;
|
|
regulator-name = "gcc_usb30_prim_gdsc";
|
|
proxy-supply = <&gcc_usb30_prim_gdsc>;
|
|
qcom,proxy-consumer-enable;
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
};
|
|
|
|
gcc_usb3_phy_gdsc: qcom,gdsc@150018 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x150018 0x4>;
|
|
regulator-name = "gcc_usb3_phy_gdsc";
|
|
parent-supply = <&VDD_MX_LEVEL>;
|
|
proxy-supply = <&gcc_usb3_phy_gdsc>;
|
|
qcom,proxy-consumer-enable;
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
};
|
|
|
|
/* GPU_CC GDSCs */
|
|
gpu_cc_cx_gdsc_hw_ctrl: syscon@3d99094 {
|
|
compatible = "syscon";
|
|
reg = <0x3d99094 0x4>;
|
|
};
|
|
|
|
gpu_cc_cx_gdsc: qcom,gdsc@3d99080 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x3d99080 0x4>;
|
|
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
|
|
regulator-name = "gpu_cc_cx_gdsc";
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
hw-ctrl-addr = <&gpu_cc_cx_gdsc_hw_ctrl>;
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
};
|
|
|
|
/* GX_CLKCTL GDSCs */
|
|
gx_clkctl_gx_gdsc: qcom,gdsc@3d68024 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x3d68024 0x4>;
|
|
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
|
|
regulator-name = "gx_clkctl_gx_gdsc";
|
|
parent-supply = <&VDD_GFX_GFX_MXC_VOTER_LEVEL>;
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
};
|
|
|
|
/* VIDEO_CC GDSCs */
|
|
video_cc_mvs0_gdsc: qcom,gdsc@aaf8068 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xaaf8068 0x4>;
|
|
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
|
|
regulator-name = "video_cc_mvs0_gdsc";
|
|
parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
|
|
qcom,retain-regs;
|
|
qcom,support-hw-trigger;
|
|
qcom,support-cfg-gdscr;
|
|
};
|
|
|
|
video_cc_mvs0c_gdsc: qcom,gdsc@aaf8034 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xaaf8034 0x4>;
|
|
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
|
|
regulator-name = "video_cc_mvs0c_gdsc";
|
|
parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
};
|
|
|
|
psci {
|
|
compatible = "arm,psci-1.0";
|
|
method = "smc";
|
|
};
|
|
|
|
ufsphy_mem: ufsphy_mem@1d80000 {
|
|
reg = <0x1d80000 0x2000>;
|
|
reg-names = "phy_mem";
|
|
#phy-cells = <0>;
|
|
|
|
lanes-per-direction = <2>;
|
|
clock-names = "ref_clk_src",
|
|
"ref_aux_clk", "qref_clk",
|
|
"rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk",
|
|
"rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk";
|
|
clocks = <&rpmhcc RPMH_CXO_PAD_CLK>,
|
|
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
|
|
<&tcsrcc TCSR_UFS_CLKREF_EN>,
|
|
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC>,
|
|
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC>,
|
|
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC>,
|
|
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
|
|
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
|
|
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>;
|
|
resets = <&ufshc_mem 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ice_cfg: shared_ice {
|
|
alg1 {
|
|
alg-name = "alg1";
|
|
rx-alloc-percent = <60>;
|
|
status = "disabled";
|
|
};
|
|
|
|
alg2 {
|
|
alg-name = "alg2";
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
alg3 {
|
|
alg-name = "alg3";
|
|
num-core = <28 28 15 13>;
|
|
status = "ok";
|
|
};
|
|
};
|
|
|
|
ufshc_mem: ufshc@1d84000 {
|
|
compatible = "qcom,ufshc";
|
|
reg = <0x1d84000 0x3000>,
|
|
<0x1d88000 0x8000>,
|
|
<0x1d90000 0x9800>;
|
|
reg-names = "ufs_mem", "ufs_ice", "ufs_ice_hwkm";
|
|
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
|
|
phys = <&ufsphy_mem>;
|
|
phy-names = "ufsphy";
|
|
#reset-cells = <1>;
|
|
|
|
lanes-per-direction = <2>;
|
|
dev-ref-clk-freq = <0>; /* 19.2 MHz */
|
|
clock-names =
|
|
"core_clk",
|
|
"bus_aggr_clk",
|
|
"iface_clk",
|
|
"core_clk_unipro",
|
|
"core_clk_ice",
|
|
"ref_clk",
|
|
"tx_lane0_sync_clk",
|
|
"rx_lane0_sync_clk",
|
|
"rx_lane1_sync_clk";
|
|
clocks =
|
|
<&gcc GCC_UFS_PHY_AXI_CLK>,
|
|
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
|
|
<&gcc GCC_UFS_PHY_AHB_CLK>,
|
|
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
|
|
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
|
|
<&rpmhcc RPMH_LN_BB_CLK3>,
|
|
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
|
|
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
|
|
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
|
|
freq-table-hz =
|
|
<100000000 403000000>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<100000000 403000000>,
|
|
<100000000 403000000>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<0 0>;
|
|
|
|
interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
|
|
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
|
|
interconnect-names = "ufs-ddr", "cpu-ufs";
|
|
|
|
qcom,ufs-bus-bw,name = "ufshc_mem";
|
|
qcom,ufs-bus-bw,num-cases = <30>;
|
|
qcom,ufs-bus-bw,num-paths = <2>;
|
|
qcom,ufs-bus-bw,vectors-KBps =
|
|
/*
|
|
* During HS G3 UFS runs at nominal voltage corner, vote
|
|
* higher bandwidth to push other buses in the data path
|
|
* to run at nominal to achieve max throughput.
|
|
* 4GBps pushes BIMC to run at nominal.
|
|
* 200MBps pushes CNOC to run at nominal.
|
|
* Vote for half of this bandwidth for HS G3 1-lane.
|
|
* For max bandwidth, vote high enough to push the buses
|
|
* to run in turbo voltage corner.
|
|
*/
|
|
<0 0>, <0 0>, /* No vote */
|
|
<922 0>, <1000 0>, /* PWM G1 */
|
|
<1844 0>, <1000 0>, /* PWM G2 */
|
|
<3688 0>, <1000 0>, /* PWM G3 */
|
|
<7376 0>, <1000 0>, /* PWM G4 */
|
|
<14752 0>, <1000 0>, /* PWM G5 */
|
|
<1844 0>, <1000 0>, /* PWM G1 L2 */
|
|
<3688 0>, <1000 0>, /* PWM G2 L2 */
|
|
<7376 0>, <1000 0>, /* PWM G3 L2 */
|
|
<14752 0>, <1000 0>, /* PWM G4 L2 */
|
|
<29504 0>, <1000 0>, /* PWM G5 L2 */
|
|
<127796 0>, <1000 0>, /* HS G1 RA */
|
|
<255591 0>, <1000 0>, /* HS G2 RA */
|
|
<1492582 0>, <102400 0>, /* HS G3 RA */
|
|
<2915200 0>, <204800 0>, /* HS G4 RA */
|
|
<255591 0>, <1000 0>, /* HS G1 RA L2 */
|
|
<511181 0>, <1000 0>, /* HS G2 RA L2 */
|
|
<1492582 0>, <204800 0>, /* HS G3 RA L2 */
|
|
<2915200 0>, <409600 0>, /* HS G4 RA L2 */
|
|
<149422 0>, <1000 0>, /* HS G1 RB */
|
|
<298189 0>, <1000 0>, /* HS G2 RB */
|
|
<1492582 0>, <102400 0>, /* HS G3 RB */
|
|
<2915200 0>, <204800 0>, /* HS G4 RB */
|
|
<298189 0>, <1000 0>, /* HS G1 RB L2 */
|
|
<596378 0>, <1000 0>, /* HS G2 RB L2 */
|
|
/* As UFS working in HS G3 RB L2 mode, aggregated
|
|
* bandwidth (AB) should take care of providing
|
|
* optimum throughput requested. However, as tested,
|
|
* in order to scale up CNOC clock, instantaneous
|
|
* bindwidth (IB) needs to be given a proper value too.
|
|
*/
|
|
<1492582 0>, <204800 409600>, /* HS G3 RB L2 KBPs */
|
|
<2915200 0>, <409600 409600>, /* HS G4 RB L2 */
|
|
<5836800 0>, <819200 0>, /* HS G5 RA L2*/
|
|
<5836800 0>, <819200 0>, /* HS G5 RB L2 */
|
|
<7643136 0>, <819200 0>; /* Max. bandwidth */
|
|
|
|
qcom,bus-vector-names = "MIN",
|
|
"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", "PWM_G5_L1",
|
|
"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", "PWM_G5_L2",
|
|
"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1",
|
|
"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2",
|
|
"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1",
|
|
"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2",
|
|
"HS_RA_G5_L2", "HS_RB_G5_L2",
|
|
"MAX";
|
|
|
|
iommus = <&apps_smmu 0x60 0x0>;
|
|
shared-ice-cfg = <&ice_cfg>;
|
|
|
|
qcom,bypass-pbl-rst-wa;
|
|
|
|
status = "disabled";
|
|
|
|
qos0 {
|
|
mask = <0xfc>;
|
|
vote = <44>;
|
|
perf;
|
|
cpu_freq_vote = <2 5 7>;
|
|
};
|
|
|
|
qos1 {
|
|
mask = <0x03>;
|
|
vote = <44>;
|
|
cpu_freq_vote = <0>;
|
|
};
|
|
};
|
|
|
|
sdhc2_opp_table: sdhc2-opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-100000000 {
|
|
opp-hz = /bits/ 64 <100000000>;
|
|
opp-peak-kBps = <160000 100000>;
|
|
opp-avg-kBps = <80000 50000>;
|
|
};
|
|
|
|
opp-202000000 {
|
|
opp-hz = /bits/ 64 <202000000>;
|
|
opp-peak-kBps = <200000 120000>;
|
|
opp-avg-kBps = <80000 50000>;
|
|
};
|
|
};
|
|
|
|
qcom,rmtfs_sharedmem@0 {
|
|
compatible = "qcom,sharedmem-uio";
|
|
reg = <0x0 0x400000>;
|
|
reg-names = "rmtfs";
|
|
qcom,client-id = <0x00000001>;
|
|
};
|
|
|
|
sdhc_2: sdhci@8804000 {
|
|
status = "disabled";
|
|
|
|
compatible = "qcom,sdhci-msm-v5";
|
|
reg = <0x08804000 0x1000>;
|
|
reg-names = "hc_mem";
|
|
|
|
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "hc_irq", "pwr_irq";
|
|
|
|
bus-width = <4>;
|
|
no-sdio;
|
|
no-mmc;
|
|
qcom,restore-after-cx-collapse;
|
|
|
|
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
|
|
<&gcc GCC_SDCC2_APPS_CLK>;
|
|
clock-names = "iface", "core";
|
|
|
|
/*
|
|
* DLL HSR settings. Refer go/hsr - <Target> DLL settings.
|
|
* Note that the DLL_CONFIG_2 value is not passed from the
|
|
* device tree, but it is calculated in the driver.
|
|
*/
|
|
qcom,dll-hsr-list = <0x0007442C 0x0 0x10
|
|
0x090106C0 0x80040868>;
|
|
|
|
iommus = <&apps_smmu 0x540 0x0>;
|
|
qcom,iommu-dma = "fastmap";
|
|
dma-coherent;
|
|
|
|
interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>,
|
|
<&gem_noc MASTER_APPSS_PROC &config_noc
|
|
SLAVE_SDCC_2>;
|
|
interconnect-names = "sdhc-ddr","cpu-sdhc";
|
|
operating-points-v2 = <&sdhc2_opp_table>;
|
|
|
|
qos0 {
|
|
mask = <0xf0>;
|
|
vote = <44>;
|
|
};
|
|
|
|
qos1 {
|
|
mask = <0x0f>;
|
|
vote = <44>;
|
|
};
|
|
};
|
|
|
|
cpu_pmu: cpu-pmu {
|
|
compatible = "arm,armv8-pmuv3";
|
|
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
msm_gpu: qcom,kgsl-3d0@3d00000 { };
|
|
|
|
spmi_bus: spmi0_bus: qcom,spmi@c42d000 {
|
|
compatible = "qcom,spmi-pmic-arb";
|
|
reg = <0xc42d000 0x4000>,
|
|
<0xc400000 0x3000>,
|
|
<0xc500000 0x400000>,
|
|
<0xc440000 0x80000>,
|
|
<0xc4c0000 0x10000>;
|
|
reg-names = "cnfg", "core", "chnls", "obsrvr", "intr";
|
|
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "periph_irq";
|
|
interrupt-controller;
|
|
#interrupt-cells = <4>;
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
cell-index = <0>;
|
|
qcom,channel = <0>;
|
|
qcom,ee = <0>;
|
|
qcom,bus-id = <0>;
|
|
};
|
|
|
|
spmi1_bus: qcom,spmi@c432000 {
|
|
compatible = "qcom,spmi-pmic-arb";
|
|
reg = <0xc432000 0x4000>,
|
|
<0xc400000 0x3000>,
|
|
<0xc500000 0x400000>,
|
|
<0xc440000 0x80000>,
|
|
<0xc4d0000 0x10000>;
|
|
reg-names = "cnfg", "core", "chnls", "obsrvr", "intr";
|
|
interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "periph_irq";
|
|
interrupt-controller;
|
|
#interrupt-cells = <4>;
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
cell-index = <0>;
|
|
qcom,channel = <0>;
|
|
qcom,ee = <0>;
|
|
qcom,bus-id = <1>;
|
|
depends-on-supply = <&spmi0_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qcom,msm-adsprpc-mem {
|
|
compatible = "qcom,msm-adsprpc-mem-region";
|
|
memory-region = <&adsp_mem_heap>;
|
|
restrict-access;
|
|
};
|
|
|
|
thermal_zones: thermal-zones {
|
|
};
|
|
};
|
|
|
|
&reserved_memory {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
gunyah_hyp_mem: gunyah_hyp_region@80000000 {
|
|
no-map;
|
|
reg = <0x0 0x80000000 0x0 0xe00000>;
|
|
};
|
|
|
|
cpusys_vm_mem: cpusys_vm_region@80e00000 {
|
|
no-map;
|
|
reg = <0x0 0x80e00000 0x0 0x400000>;
|
|
};
|
|
|
|
cpucp_mem: cpucp_region@81200000 {
|
|
no-map;
|
|
reg = <0x0 0x81200000 0x0 0x200000>;
|
|
};
|
|
|
|
/*
|
|
* hyp_tags_mem is dynamically removed from the RAM
|
|
* partition tables before boot occurs. Size of region
|
|
* varies.
|
|
*/
|
|
|
|
/* merged xbl_dtlog, xbl_ramdump and aop_image regions */
|
|
xbl_aop_merged_mem: xbl_aop_merged_region@81a00000 {
|
|
no-map;
|
|
reg = <0x0 0x81a00000 0x0 0x260000>;
|
|
};
|
|
|
|
aop_cmd_db_mem: aop_cmd_db_region@81c60000 {
|
|
compatible = "qcom,cmd-db";
|
|
no-map;
|
|
reg = <0x0 0x81c60000 0x0 0x20000>;
|
|
};
|
|
|
|
/* merged aop_config, tme_crash_dump, tme_log and uefi_log regions */
|
|
aop_tme_uefi_merged_mem: aop_tme_uefi_merged_region@81c80000 {
|
|
no-map;
|
|
reg = <0x0 0x81c80000 0x0 0x74000>;
|
|
};
|
|
|
|
/* secdata region can be reused by apps */
|
|
|
|
smem_mem: smem_region@81d00000 {
|
|
compatible = "qcom,smem";
|
|
reg = <0x0 0x81d00000 0x0 0x200000>;
|
|
hwlocks = <&tcsr_mutex 3>;
|
|
no-map;
|
|
};
|
|
|
|
pdp_ns_shared_mem: pdp_ns_shared_region@81f00000 {
|
|
no-map;
|
|
reg = <0x0 0x81f00000 0x0 0x100000>;
|
|
};
|
|
|
|
cpucp_scandump_mem: cpucp_scandump_region@82000000 {
|
|
no-map;
|
|
reg = <0x0 0x82000000 0x0 0x380000>;
|
|
};
|
|
|
|
adsp_mhi_mem: adsp_mhi_region@82380000 {
|
|
no-map;
|
|
reg = <0x0 0x82380000 0x0 0x20000>;
|
|
};
|
|
|
|
soccp_sdi_mem: soccp_sdi_region@823a0000 {
|
|
no-map;
|
|
reg = <0x0 0x823a0000 0x0 0x40000>;
|
|
};
|
|
|
|
pmic_minii_dump_mem: pmic_minii_dump_region@823e0000 {
|
|
no-map;
|
|
reg = <0x0 0x823e0000 0x0 0x80000>;
|
|
};
|
|
|
|
pvm_fw_mem: pvm_fw_region@824a0000 {
|
|
no-map;
|
|
reg = <0x0 0x824a0000 0x0 0x100000>;
|
|
};
|
|
|
|
/* hyp_mem_database_mem is removed by HYP in the RAM partition table */
|
|
|
|
global_sync_mem: global_sync_region@82600000 {
|
|
no-map;
|
|
reg = <0x0 0x82600000 0x0 0x100000>;
|
|
};
|
|
|
|
tz_stat_mem: tz_stat_region@82700000 {
|
|
no-map;
|
|
reg = <0x0 0x82700000 0x0 0x100000>;
|
|
};
|
|
|
|
qdss_apps_mem: qdss_apps_region@82800000 {
|
|
compatible = "shared-dma-pool";
|
|
reg = <0x0 0x82800000 0x0 0x2000000>;
|
|
reusable;
|
|
};
|
|
|
|
dsm_partition_1_mem: dsm_partition_1_region@86b00000 {
|
|
no-map;
|
|
reg = <0x0 0x86b00000 0x0 0x4900000>;
|
|
};
|
|
|
|
dsm_partition_2_mem: dsm_partition_2_region@8b400000 {
|
|
no-map;
|
|
reg = <0x0 0x8b400000 0x0 0x800000>;
|
|
};
|
|
|
|
mpss_mem: mpss_region@8bc00000 {
|
|
no-map;
|
|
reg = <0x0 0x8bc00000 0x0 0xf400000>;
|
|
};
|
|
|
|
q6_mpss_dtb_mem: q6_mpss_dtb_region@9b000000 {
|
|
no-map;
|
|
reg = <0x0 0x9b000000 0x0 0x80000>;
|
|
};
|
|
|
|
ipa_fw_mem: ipa_fw_region@9b080000 {
|
|
no-map;
|
|
reg = <0x0 0x9b080000 0x0 0x10000>;
|
|
};
|
|
|
|
ipa_gsi_mem: ipa_gsi_region@9b090000 {
|
|
no-map;
|
|
reg = <0x0 0x9b090000 0x0 0xa000>;
|
|
};
|
|
|
|
gpu_microcode_mem: gpu_microcode_region@9b09a000 {
|
|
no-map;
|
|
reg = <0x0 0x9b09a000 0x0 0x2000>;
|
|
};
|
|
|
|
spss_region_mem: spss_region_region@9b100000 {
|
|
no-map;
|
|
reg = <0x0 0x9b100000 0x0 0x180000>;
|
|
};
|
|
|
|
spu_secure_shared_memory_mem: spu_secure_shared_memory_region@9b280000 {
|
|
no-map;
|
|
reg = <0x0 0x9b280000 0x0 0x80000>;
|
|
};
|
|
|
|
camera_mem: camera_region@9b300000 {
|
|
no-map;
|
|
reg = <0x0 0x9b300000 0x0 0x800000>;
|
|
};
|
|
|
|
camera_2_mem: camera_2_region@9bb00000 {
|
|
no-map;
|
|
reg = <0x0 0x9bb00000 0x0 0x800000>;
|
|
};
|
|
|
|
video_mem: video_region@9c300000 {
|
|
no-map;
|
|
reg = <0x0 0x9c300000 0x0 0x800000>;
|
|
};
|
|
|
|
cvp_mem: cvp_region@9cb00000 {
|
|
no-map;
|
|
reg = <0x0 0x9cb00000 0x0 0x700000>;
|
|
};
|
|
|
|
cdsp_mem: cdsp_region@9d200000 {
|
|
no-map;
|
|
reg = <0x0 0x9d200000 0x0 0x2000000>;
|
|
};
|
|
|
|
q6_cdsp_dtb_mem: q6_cdsp_dtb_region@9f200000 {
|
|
no-map;
|
|
reg = <0x0 0x9f200000 0x0 0x80000>;
|
|
};
|
|
|
|
q6_adsp_dtb_mem: q6_adsp_dtb_region@9f280000 {
|
|
no-map;
|
|
reg = <0x0 0x9f280000 0x0 0x80000>;
|
|
};
|
|
|
|
adspslpi_mem: adspslpi_region@9f300000 {
|
|
no-map;
|
|
reg = <0x0 0x9f300000 0x0 0x4080000>;
|
|
};
|
|
|
|
soccp_mem: soccp_region@a3380000 {
|
|
no-map;
|
|
reg = <0x0 0xa3380000 0x0 0x100000>;
|
|
};
|
|
|
|
/* uefi region can be reused by apps */
|
|
|
|
/* Linux kernel image is loaded at 0xa8000000 */
|
|
|
|
/* merged tz_reserved, xbl_sc, and qtee regions */
|
|
tz_merged_mem: tz_merged_region@d8000000 {
|
|
no-map;
|
|
reg = <0x0 0xd8000000 0x0 0x600000>;
|
|
};
|
|
|
|
/*
|
|
* ta/tags mem is dynamically removed from the RAM
|
|
* partition tables before boot occurs. Size of region
|
|
* varies.
|
|
*/
|
|
|
|
trust_ui_vm_mem: trust_ui_vm_region@f3800000 {
|
|
compatible = "shared-dma-pool";
|
|
reg = <0x0 0xf3800000 0x0 0x4400000>;
|
|
reusable;
|
|
alignment = <0x0 0x400000>;
|
|
};
|
|
|
|
oem_vm_mem: oem_vm_region@f7c00000 {
|
|
compatible = "shared-dma-pool";
|
|
reg = <0x0 0xf7c00000 0x0 0x4c00000>;
|
|
reusable;
|
|
alignment = <0x0 0x400000>;
|
|
};
|
|
|
|
llcc_lpi_mem: llcc_lpi_region@ff800000 {
|
|
no-map;
|
|
reg = <0x0 0xff800000 0x0 0x800000>;
|
|
};
|
|
|
|
system_cma: linux,cma {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x0 0x400000>;
|
|
size = <0x0 0xC00000>;
|
|
linux,cma-default;
|
|
};
|
|
|
|
/* cdsp eva shared memory */
|
|
cdsp_eva_mem: cdsp_eva_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x0 0x400000>;
|
|
size = <0x0 0x400000>;
|
|
};
|
|
|
|
adsp_mem_heap: adsp_heap_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x0 0x400000>;
|
|
size = <0x0 0xC00000>;
|
|
};
|
|
};
|
|
|
|
#include "sun-dma-heaps.dtsi"
|
|
#include "sun-coresight.dtsi"
|
|
#include "sun-debug.dtsi"
|
|
#include "msm-arm-smmu-sun.dtsi"
|
|
#include "sun-pinctrl.dtsi"
|
|
#include "sun-regulators.dtsi"
|
|
#include "sun-qupv3.dtsi"
|
|
#include "sun-usb.dtsi"
|
|
#include "sun-thermal.dtsi"
|
|
|
|
&qupv3_se7_2uart {
|
|
status = "ok";
|
|
};
|
|
|
|
#include "ipcc-test.dtsi"
|
|
/delete-node/ &ipcc_self_ping_adsp;
|
|
/delete-node/ &ipcc_self_ping_cdsp;
|
|
/delete-node/ &ipcc_self_ping_slpi;
|