ARM: dts: qcom: add PMIC devices for Sun

Add top level SPMI slave devices for PMD802x, PMIH010x, PM8550VE and
PM8550VS.

Change-Id: I7658cd5e9bb0c2801db10029380cb7a76a97abff
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>

qcom/pm8550ve.dtsi

@@ -12,6 +12,40 @@
 	interrupt-controller;
 	#interrupt-cells = <4>;
 
+	pm8550ve_d: qcom,pm8550ve@3 {
+		compatible = "qcom,spmi-pmic";
+		reg = <0x3 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+
+		pm8550ve_d_gpios: pinctrl@8800 {
+			compatible = "qcom,pm8550ve-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	pm8550ve_g: qcom,pm8550ve@6 {
+		compatible = "qcom,spmi-pmic";
+		reg = <0x6 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+
+		pm8550ve_g_gpios: pinctrl@8800 {
+			compatible = "qcom,pm8550ve-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
 	pm8550ve_i: qcom,pm8550ve@8 {
 		compatible = "qcom,spmi-pmic";
 		reg = <0x8 SPMI_USID>;

qcom/pm8550vs.dtsi

@@ -84,6 +84,23 @@
 		};
 	};
 
+	pm8550vs_f: qcom,pm8550vs@5 {
+		compatible = "qcom,spmi-pmic";
+		reg = <0x5 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+
+		pm8550vs_f_gpios: pinctrl@8800 {
+			compatible = "qcom,pm8550vs-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
 	pm8550vs_g: qcom,pm8550vs@6 {
 		compatible = "qcom,spmi-pmic";
 		reg = <0x6 SPMI_USID>;
@@ -107,6 +124,23 @@
 			#interrupt-cells = <2>;
 		};
 	};
+
+	pm8550vs_j: qcom,pm8550vs@9 {
+		compatible = "qcom,spmi-pmic";
+		reg = <0x9 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+
+		pm8550vs_j_gpios: pinctrl@8800 {
+			compatible = "qcom,pm8550vs-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
 };
 
 &thermal_zones {

qcom/pmd802x.dtsi

@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+	#address-cells = <2>;
+	#size-cells = <0>;
+	interrupt-controller;
+	#interrupt-cells = <4>;
+
+	qcom,pmd802x@4 {
+		compatible = "qcom,spmi-pmic";
+		reg = <0x4 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pmd802x_gpios: pinctrl@8800 {
+			compatible = "qcom,pmd802x-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+};

qcom/pmih010x.dtsi

@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+	#address-cells = <2>;
+	#size-cells = <0>;
+	interrupt-controller;
+	#interrupt-cells = <4>;
+
+	qcom,pmih010x@7 {
+		compatible = "qcom,spmi-pmic";
+		reg = <0x7 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pmih010x_gpios: pinctrl@8800 {
+			compatible = "qcom,pmih010x-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+};

qcom/sun-cdp.dtsi

@@ -3,3 +3,4 @@
  * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
+#include "sun-pmic-overlay.dtsi"

qcom/sun-mtp.dtsi

@@ -3,3 +3,4 @@
  * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
+#include "sun-pmic-overlay.dtsi"

qcom/sun-pmic-overlay.dtsi

@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "pm8010.dtsi"
+#include "pm8550.dtsi"
+#include "pm8550ve.dtsi"
+#include "pm8550vs.dtsi"
+#include "pmd802x.dtsi"
+#include "pmih010x.dtsi"
+#include "pmk8550.dtsi"
+#include "pmr735d.dtsi"
+
+&pm8550vs_f {
+	status = "ok";
+};
+
+&pm8550vs_j {
+	status = "ok";
+};
+
+&pm8550ve_d {
+	status = "ok";
+};
+
+&pm8550ve_g {
+	status = "ok";
+};
+
+&pm8550ve_i {
+	status = "ok";
+};
+
+&pm8550ve_i_temp_alarm {
+	status = "ok";
+};

qcom/sun-qrd.dtsi

@@ -3,3 +3,4 @@
  * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
+#include "sun-pmic-overlay.dtsi"

qcom/sun-rumi.dtsi

@@ -7,6 +7,8 @@
 #include <dt-bindings/clock/qcom,gcc-pineapple.h>
 #include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
 
+#include "sun-pmic-overlay.dtsi"
+
 &reserved_memory {
 	spintable: spintable_region@90000000 {
 		no-map;