Correct the following pcie1 dt property names on pineapple
device as they are modified for this latest kernel devicetree
documentation.
clock-frequency -> qcom,pcie-clock-frequency.
Change-Id: I048275f388f31fe71b157f1f9ab4aaf5eec6131b
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Based on upstream commit ee13b50 ("qcom: llcc/edac: Fix the base address
used for accessing LLCC banks"), the devicetree needs to be updated with
LLCC bank 0 through 3, instead of just the start LLCC bank 0 and the end
LLCC broadcast.
Change-Id: I1d2b758693f6a71338653fa677dbb833299475c6
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
Based on upstream commit ee13b50 ("qcom: llcc/edac: Fix the base address
used for accessing LLCC banks"), the devicetree needs to be updated with
LLCC bank 0 through 3, instead of just the start LLCC bank 0 and the end
LLCC broadcast.
Change-Id: I7c2b62697721074660c6b7371e0d2b1bf195ba5d
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
The clock required to access this GDSC depends on a clock coming from
GPU_CC, which is enabled by default in gpucc probe. Add a phandle to
gpucc to ensure it probes first and enables the required clock.
Change-Id: I5aae1a6a1a3615cf1a8227b839a721a6af945243
Signed-off-by: Mike Tipton <quic_mdtipton@quicinc.com>
Correct the following pcie dt property names on pineapple
device as they are modified for this latest kernel devicetree
documentation.
qcom,pcie-clkreq-gpio -> qcom,pcie-clkreq-pin.
clock-frequency -> qcom,pcie-clock-frequency.
Change-Id: I79454ef04a69d5427e32c45042304809cdcb886c
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Enable tlmm VM mem access device tree nodes for Pineapple.
Change-Id: I2bfbc22e8f9e933e3d0ec419b3fa67ff89b4fdad
Signed-off-by: Hrishabh Rajput <quic_hrishabh@quicinc.com>
Sun and pineapple share certain PMICs. Prepare the shared PMIC devices
to be used for both Sun and Pineapple.
Change-Id: I378e781751b4ee42b3c0d4940dff30ffbd2b3e5a
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
Add device tree files needed to support Sun SoC + Kiwi platforms.
Change-Id: Ie27eea504087f8da315ab6b0e90d1660d32e3815
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
Add spmi-pmic-arb devices for the primary and secondary SPMI buses
found on Sun. The primary bus operates at 19.2 MHz and is used for
most of the PMICs.
The secondary bus operates at 4.8 MHz and is used exclusively for
charging PMICs. Note that the secondary bus is not connected to
the SoC on the board due to voltage level differences. Therefore,
keep the secondary bus device disabled.
Change-Id: I6b2bb6b54e285fd9c333971b08134c3768087869
Signed-off-by: David Collins <quic_collinsd@quicinc.com>
Add base TUIVM and OEMVM device tree support for Sun RUMI platform.
Change-Id: I32598ce2c3488658e2c9caf0cd7a2368665c0b06
Signed-off-by: Meena Pasumarthi <quic_pasumart@quicinc.com>
Signed-off-by: Sahitya Tummala <quic_stummala@quicinc.com>
Add base TUIVM and OEMVM device tree support for all Pineapple platforms.
Change-Id: I7c3cc2112e122f25a2f0b573128e8fdfb86975c5
Signed-off-by: Meena Pasumarthi <quic_pasumart@quicinc.com>
Signed-off-by: Hrishabh Rajput <quic_hrishabh@quicinc.com>
Add device tree entries for smcinvoke, shmbridge and tz-log
drivers and qseecom heaps.
Change-Id: I1a427c66e12a02532097db352a1d26fe5ececb9f
Signed-off-by: Anmolpreet Kaur <quic_anmolpre@quicinc.com>
Add initial devicetree nodes and entries to support
PCIe RC0 port configuration on sun.
Change-Id: I3b7419bfd376a51388785cc4e2f9702ddaabe397
Signed-off-by: Lazarus Motha <quic_lmotha@quicinc.com>
Add crmb and crmc register space for cesta devices on pineapple.
Change-Id: Ia8ec195ca1683e652b31a5daa2ab271e8bcec321
Signed-off-by: Gokul krishna Krishnakumar <quic_gokukris@quicinc.com>
Since we use downstream pmic_glink drivers, use the right compatible
string for pmic_glink devices on pineapple to support battery
management.
Change-Id: Ia6375ec2c938149dd31ae073b906b1c09b37b21e
Signed-off-by: Subbaraman Narayanamurthy <quic_subbaram@quicinc.com>
GCC needs to probe before GDSC regulator driver as driver will be
unable to read registers without required gcc config ahb clocks. These
config ahb clocks are enabled in GCC probe. Thus GCC needs to probe
before GDSC driver. Adding GCC phandles to sequence the probe order
during kernel boot.
Change-Id: Icd13d18f07540f96cb4175edc5bd41526b6a3841
Signed-off-by: Vivek Aknurwar <quic_viveka@quicinc.com>
Port of the DT entry which provides configuration settings for the
msm_sharedmem driver. This is needed for correct operation of
MPSS RFS/EFS.
Change-Id: Ic08e19398f10908920f8ac1d7e4670109de5e356
Signed-off-by: Marc Guillaume <quic_mguillau@quicinc.com>
Add bindings for WCD and WSA in pinctrl dt
file for sun.
Change-Id: Icb1fd6fb5950c5814cb4039d369647baac93ddf3
Signed-off-by: Eric Rosas <quic_erosas@quicinc.com>
Audio kernel depends on the aliases label being defined
from the top level. Add label to aliases node to allow
for proper compilation of audio kernel.
Change-Id: Idb88dd470ca0dec31670adef8546e34fee14a4d7
Signed-off-by: Eric Rosas <quic_erosas@quicinc.com>
Describe the registers and interrupts of the kgsl_iommu device.
Change-Id: I632cdb3f204dda4af32829c0e373c15065f87af9
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
