Add bindings for SW-calibrated ADC used on PMR735A/PMR735B on
targets which don't have PMK8350 running in master mode.
Change-Id: I753b3caf1e52ac9920a9df32cbef465277409700
Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com>
[quic_amelende@quicinc.com: Converted binding change from .txt to .yaml]
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
There were 2 entries for spss, remove one.
Change-Id: Ia7aae336809953377f9a9da6457289262fb2524a
Signed-off-by: Gokul krishna Krishnakumar <quic_gokukris@quicinc.com>
Add documentation for ufs-phy-qmp-v4-sun phy driver.
Change-Id: I5238ad385f7833e9de3a4c85a9a2936d3dc6a8f4
Signed-off-by: Bao D. Nguyen <quic_nguyenb@quicinc.com>
Adding the firmware name and updating the additional memory assign node
for remoteproc's to be compatible with the driver.
Change-Id: I3787fd0c97c039821a91e15bc6e554caccf071a8
Signed-off-by: Gokul krishna Krishnakumar <quic_gokukris@quicinc.com>
The driver provides the framework to test memory lend to VM.
Change-Id: I90c2b17181ce9e50c037fa4997f8f9a5f6b9154b
Signed-off-by: Hrishabh Rajput <quic_hrishabh@quicinc.com>
Add qcom-spmi-temp-alarm devices for the TEMP_ALARM and TEMP_ALARM_LITE
PMIC peripherals found in PMICs PM8550VE_D, PM8550VE_G, PM8550VS_F,
PM8550VS_J, PMIH010X, and PMD802X which are used on Sun boards. Each
TEMP_ALARM device can monitor the die temperature of a particular PMIC.
Change-Id: I3e29ec91f50a5c27d4a8e581c9c17ad3ae09d187
Signed-off-by: David Collins <quic_collinsd@quicinc.com>
Specify a pinctrl configuration for PMK8550 GPIO 3 to enable
alt_sleep_clk output so that clients like WLAN and BT can
function properly.
Change-Id: I74506946647b55e391a8c848c44ccf20af966739
Signed-off-by: Subbaraman Narayanamurthy <quic_subbaram@quicinc.com>
Bindings for fastrpc nodes and the child nodes.
Change-Id: Ic967b92d2324d5f9671614f62973c5f9820d6b4b
Signed-off-by: Gokul krishna Krishnakumar <quic_gokukris@quicinc.com>
Correct the following pcie1 dt property names on pineapple
device as they are modified for this latest kernel devicetree
documentation.
clock-frequency -> qcom,pcie-clock-frequency.
Change-Id: I048275f388f31fe71b157f1f9ab4aaf5eec6131b
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Update qcom,spmi-vadc bindings to include "qcom,scale-fn-type"
property for ADC7.
Change-Id: Ieb8ad5779b078dd77838c498b3a4e0bbcf907df8
Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com>
[quic_amelende@quicinc.com: Converted binding change from .txt to .yaml
and removed changes already captured in yaml]
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
Following device tree register addresses change from upstream commit
ee13b50 ("qcom: llcc/edac: Fix the base address used for accessing LLCC
banks").
Change LLCC bindings for Pineapple and Sun SoC.
Change-Id: I60bdfd7e4bc19343a3eb6a1c0c597523f1c30963
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
Based on upstream commit ee13b50 ("qcom: llcc/edac: Fix the base address
used for accessing LLCC banks"), the devicetree needs to be updated with
LLCC bank 0 through 3, instead of just the start LLCC bank 0 and the end
LLCC broadcast.
Change-Id: I1d2b758693f6a71338653fa677dbb833299475c6
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
Based on upstream commit ee13b50 ("qcom: llcc/edac: Fix the base address
used for accessing LLCC banks"), the devicetree needs to be updated with
LLCC bank 0 through 3, instead of just the start LLCC bank 0 and the end
LLCC broadcast.
Change-Id: I7c2b62697721074660c6b7371e0d2b1bf195ba5d
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
Add a gpio-keys device for Sun MTP, CDP and QRD boards that use
PM8550 GPIO 6.
Change-Id: I3b6ec4f7cb826cd482e85cdbbcbea3db485284c1
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
Add the LPG LED device for sun platforms. Currently, pm8550 LED
devices use the downstream leds-qti-tri-led driver. Update the LED
devices so that they use the upstream leds-qcom-lpg driver.
Change-Id: I6e9c80d9e7725e5978fbc8bebf02a7d66968d32e
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
The clock required to access this GDSC depends on a clock coming from
GPU_CC, which is enabled by default in gpucc probe. Add a phandle to
gpucc to ensure it probes first and enables the required clock.
Change-Id: I5aae1a6a1a3615cf1a8227b839a721a6af945243
Signed-off-by: Mike Tipton <quic_mdtipton@quicinc.com>
Correct the following pcie dt property names on pineapple
device as they are modified for this latest kernel devicetree
documentation.
qcom,pcie-clkreq-gpio -> qcom,pcie-clkreq-pin.
clock-frequency -> qcom,pcie-clock-frequency.
Change-Id: I79454ef04a69d5427e32c45042304809cdcb886c
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Enable tlmm VM mem access device tree nodes for Pineapple.
Change-Id: I2bfbc22e8f9e933e3d0ec419b3fa67ff89b4fdad
Signed-off-by: Hrishabh Rajput <quic_hrishabh@quicinc.com>
Sun and pineapple share certain PMICs. Prepare the shared PMIC devices
to be used for both Sun and Pineapple.
Change-Id: I378e781751b4ee42b3c0d4940dff30ffbd2b3e5a
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
Update the Qualcomm Technologies, INC. PMIC GPIO binding documentation
to include compatible strings for PMIH010x and PMD802x PMICs.
Change-Id: Icf07b2f657d0e6fd104ae36553d1631caadcdb70
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
Update prescale ratios to support the new channels.
Change-Id: I4d37e9653962954e856f464df32297d9aa90757a
Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com>
[quic_amelende@quicinc.com: Converted binding change from .txt to .yaml]
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
Update compatible string to support ADC channels that are registered to
thermal framework, without registering interrupts.
Change-Id: Ie2a1d59272434453c27f2daa2b758ab8a6c96db2
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
Add device tree files needed to support Sun SoC + Kiwi platforms.
Change-Id: Ie27eea504087f8da315ab6b0e90d1660d32e3815
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
