Add ldo-ocp notifier support for tuna for platforms.
Change-Id: I46c1feb2f4ff2da3945f9ad445eb5d99f81f7af4
Signed-off-by: Kavya Nunna <quic_knunna@quicinc.com>
Add device tree bindings for arm,arch-cache node.
Change-Id: I46acfdd171e297368d6bedc431af7dd1270909f8
Signed-off-by: Asit Shah <quic_asitshah@quicinc.com>
Add devicetree support for Tuna7 and TunaP SoC.
Change-Id: I5f94559c66f00bcb746fc05f7c445a8e2501d862
Signed-off-by: Hrishabh Rajput <quic_hrishabh@quicinc.com>
(cherry picked from commit b0ed9373e7)
Added initial device tree for QCS610 LE target.
Change-Id: Ia8b8790fa0916a8a87a5bc696f5b9e23d7e951dc
Signed-off-by: Kunal Singh Ranawat <quic_kranawat@quicinc.com>
Add devicetree support for Tuna7 and TunaP SoC.
Change-Id: I5f94559c66f00bcb746fc05f7c445a8e2501d862
Signed-off-by: Hrishabh Rajput <quic_hrishabh@quicinc.com>
Update memory map for kera, inline with v4.
Change-Id: Ifc5acdc379372239f4fde0f22fcd8c17f66ce636
Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
According to the Hardware Programming Guide, when going into hibern8,
select XO clock (RPMH_CXO_CLK) clock as the parent of the phy symbol
mux clocks (GCC_UFS_PHY_RX/TX_SYMBOL_0/1_CLK_SRC). When exiting the
hibern8, select the phy symbol clocks (UFS_PHY_RX/TX_SYMBOL_0/1_CLK)
as the parent of the phy symbol mux clocks.
Change-Id: I624f98c39b7548dc2a9a5207d82600bb69ac41d5
Signed-off-by: Bao D. Nguyen <quic_nguyenb@quicinc.com>
Update memory map for kera, inline with v4.
Change-Id: Ifc5acdc379372239f4fde0f22fcd8c17f66ce636
Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
Reserve 16kb to dcc on TZ while HLOS have 16 KB.
Change-Id: I2063be0924b5719bd2c3abfffc84c0044d74ae37
Signed-off-by: Yingchao Deng <quic_yingdeng@quicinc.com>
(cherry picked from commit 285a63e7b4)
Add MHI device related DT bindings on sdxkova.
Change-Id: I4bbdfc6e29555d6011cd474f5d0e54d9cd6517d7
Signed-off-by: Anvita T <quic_atadepal@quicinc.com>
Add PCIE endpoint related DT bindings on sdxkova.
Change-Id: Ied1e29b5f272cd10b18334e710c611c407422c43
Signed-off-by: Anvita T <quic_atadepal@quicinc.com>
Increase the number of pipe clock toggles that will occur after
phystatus goes high at the output of the PHY during L1SS/P2 entry
in PCS_PCIE_POWER_STATE_CONFIG6 register, so that if the phy and
controller goes out of sync this may help us. The number of pipe
clock toggles is equal to (4*value)+1.
Change-Id: I7a31882f18879ef990825aa2d978fc7f39233472
Signed-off-by: Vivek Pernamitta <quic_vpernami@quicinc.com>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Add the soc-specific compatible string as it is
required to apply appropriate keepout regions.
Change-Id: I59fe0c9dffdf182bfb52468ef5a0d564ad7a8b38
Signed-off-by: Saranya R <quic_sarar@quicinc.com>
Add dtsi node to enable Hardware key manager for monaco target.
And add the device tree bindings for the Hardware key manager driver.
Change-Id: If1e38c3c71148fd85058eb31d4eee5f806e47fef
Signed-off-by: Shivangi Kesharwani <quic_skesharw@quicinc.com>
