a3a111ed95
Increase the number of pipe clock toggles that will occur after phystatus goes high at the output of the PHY during L1SS/P2 entry in PCS_PCIE_POWER_STATE_CONFIG6 register, so that if the phy and controller goes out of sync this may help us. The number of pipe clock toggles is equal to (4*value)+1. Change-Id: I7a31882f18879ef990825aa2d978fc7f39233472 Signed-off-by: Vivek Pernamitta <quic_vpernami@quicinc.com> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>