Add MHI device related DT bindings on sdxkova.
Change-Id: I4bbdfc6e29555d6011cd474f5d0e54d9cd6517d7
Signed-off-by: Anvita T <quic_atadepal@quicinc.com>
Add PCIE endpoint related DT bindings on sdxkova.
Change-Id: Ied1e29b5f272cd10b18334e710c611c407422c43
Signed-off-by: Anvita T <quic_atadepal@quicinc.com>
Increase the number of pipe clock toggles that will occur after
phystatus goes high at the output of the PHY during L1SS/P2 entry
in PCS_PCIE_POWER_STATE_CONFIG6 register, so that if the phy and
controller goes out of sync this may help us. The number of pipe
clock toggles is equal to (4*value)+1.
Change-Id: I7a31882f18879ef990825aa2d978fc7f39233472
Signed-off-by: Vivek Pernamitta <quic_vpernami@quicinc.com>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Add the soc-specific compatible string as it is
required to apply appropriate keepout regions.
Change-Id: I59fe0c9dffdf182bfb52468ef5a0d564ad7a8b38
Signed-off-by: Saranya R <quic_sarar@quicinc.com>
Add dtsi node to enable Hardware key manager for monaco target.
And add the device tree bindings for the Hardware key manager driver.
Change-Id: If1e38c3c71148fd85058eb31d4eee5f806e47fef
Signed-off-by: Shivangi Kesharwani <quic_skesharw@quicinc.com>
Add ulps and roi support for 120hz, 90hz & 60hz
VTDR6130 panel on Kera target.
Change-Id: I21bf599aadc6d4f10d25c3f1d232c1ba37a0d8b1
Signed-off-by: Abhinav Saurabh <quic_abhisaur@quicinc.com>
Add record in audio-routes for tuna7
where it is missing for record over AATC.
With this can record using AATC.
Change-Id: I9a76e16d5dc8168a11411ce715559350e6cc0c1f
Signed-off-by: Ravulapati Vishnu Vardhan Rao <quic_visr@quicinc.com>
(cherry picked from commit d2fe78d4a6)
Add parrot qfprom compatible string so that data can be
attached to it in the driver.
Change-Id: Ib69c0438446f6493d4a66c3453f1a878ccc0b10a
Signed-off-by: Saranya R <quic_sarar@quicinc.com>
Reserve 16kb to dcc on TZ while HLOS have 16 KB.
Change-Id: I2063be0924b5719bd2c3abfffc84c0044d74ae37
Signed-off-by: Yingchao Deng <quic_yingdeng@quicinc.com>
Add bindings documentation for qcom,pmic-ecid. PMIC ECID provides the
PMIC specific information for identification.
Change-Id: I012670359ad1b1c4aea92f59b9430efc6e446f5f
Signed-off-by: Brindha T<quic_brint@quicinc.com>
Add devices to track CPU LPMs, SoC level LPMs, and system pm
violators.
Change-Id: I65a0dfeb814b47bdfcc4468ec8f1e7f63338581c
Signed-off-by: Sneh Mankad <quic_smankad@quicinc.com>
Update clk div factor entries for TX and VA macros to reflect
proper HW configuration.
Change-Id: Ic5456d7e30245a484b6a4888835c7e6f838eb92b
Signed-off-by: Ravulapati Vishnu Vardhan Rao <quic_visr@quicinc.com>
Update the slave address for slave charger debug support.
As well as update the slave address for glink adc channels
to fix reading I/O errors.
Change-Id: If1a0725aeeb1a67d7a19a3a5629ca2be44ff674c
Signed-off-by: Tingguo Cheng <quic_tingguoc@quicinc.com>
To enable and disable mdp clock gating functionality with
cesta immediate vote approach, add disp_cc_io memory to
sde cesta. Add changes to enable ctl hyp property for
reserve reservation on datapath used in a VM.
Change-Id: Id10875ecb90acb8a922ef4e4788da13a764ea102
Signed-off-by: Sailesh Reddy Male <quic_reddymal@quicinc.com>
Add xo clock in sde_cesta for kera target. This will help
to vote for xo frequency during cesta idle time.
Change-Id: Ic4370c8a49ffbec2743c022e438280d371a5a968
Signed-off-by: Sailesh Reddy Male <quic_reddymal@quicinc.com>
Add display cesta related DT node on kera target. Move
the GDSC & MDP core clock from MDP to cesta node, as it
will be controlled through cesta. Add the cesta
related register offsets in trusted-vm DT.
Change-Id: I1f777f3402d8a4d7d57ca889206a4095447abb7d
Signed-off-by: Sailesh Reddy Male <quic_reddymal@quicinc.com>
To enable and disable mdp clock gating functionality with
cesta immediate vote approach, add disp_cc_io memory to
sde cesta. Add ctl hyp DT property for reserve reservation
on a datapath used in VM.
Change-Id: I4c1b900dfb5e1a7d725aea80b4519bc1f9472e03
Signed-off-by: Sampurna Bolloju <quic_sampboll@quicinc.com>
Fix the memory mapping error for non dma-coherent target Monaco
when iommu-dma is used as "fastmap" by changing it to "atomic".
Hence, Change iommu-dma to atomic setting.
Change-Id: Ic21cbd4d5e9e429dd6aa577652d0ccb1a9acc99c
Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com>
