Update power-source to 2 for chipsets to use 1.2 V for BT_EN
CRs-Fixed: 4065538
Change-Id: I72ec6863be8d40b40cdeefbb837f1ac652319173
Signed-off-by: Hemant Gupta <quic_hemantg@quicinc.com>
(cherry picked from commit 4eff48c0b7)
Add interconnect device bindings. These devices can be used to
describe any RPMH and NoC based interconnect devices.
Change-Id: Ic9a21d11bb3ce92ffb0cde91739990441673861d
Signed-off-by: Veera Vegivada <quic_vvegivad@quicinc.com>
Signed-off-by: Aryan Modi <quic_aryamodi@quicinc.com>
- Added new SOC-ID's to support parrot target
Change-Id: I75a3db97b95a365e01a94a69b68cf6d41dd1e8b6
Signed-off-by: Manish Kumar Sharma <quic_msharm@quicinc.com>
Added smem, syscon and dependent nodes for SM6150.
Change-Id: Icb9485e46c8720919310bc0e2560bd51b23f5dec
Signed-off-by: Asit Shah <quic_asitshah@quicinc.com>
Add support for TLMM pinctrl on SM6150 platform.
Change-Id: I45dfd3d84900ed4b24ecda47462c2c5178bbb02f
Signed-off-by: Kunal Singh Ranawat <quic_kranawat@quicinc.com>
Add bindings for sm6150 llcc node.
Change-Id: I4f239f190c01110e59c1081ccf0a57cb1631fb95
Signed-off-by: Asit Shah <quic_asitshah@quicinc.com>
(cherry picked from commit 4173e882bd59e39d8b698fed8b92417231c98e4e)
Add the Level Shifter's external feedback clock entry to support
the SD card HS50 mode running at 50MHz.
By default, the Sun platforms use the Level Shifter devices with
external feedback clock signal connects back to the MSM in order
for the HS50 mode to work at 50MHz. Without the external feedback
clock, the HS50 mode works at reduced frequency at 37.5MHz.
Change-Id: I56c61411d7f792a389fa85661fce7fa5074e2c9f
Signed-off-by: Bao D. Nguyen <quic_nguyenb@quicinc.com>
Update power-source to 2 for chipsets to use 1.2 V for BT_EN
CRs-Fixed: 4065538
Change-Id: I72ec6863be8d40b40cdeefbb837f1ac652319173
Signed-off-by: Hemant Gupta <quic_hemantg@quicinc.com>
Reduce the buffer size from 32KB to 16KB and decrease the number
of buffers submitting to the HW to 128 per pipe for effective
utilization and memory optimization.
Change-Id: I709141bd9083570bb18bba0ce13e86956fdfea4a
Signed-off-by: Pavan Kumar M <quic_rpavan@quicinc.com>
WLAN has a requirement to trigger a PBS sequence for XO calibration
for factory testing. To support this, expose a new register under
PMK8550 SDAM2 for clients to write input data into and a new PBS
regulator on which clients can vote to trigger the PBS sequence.
Change-Id: I0e4882d842ea57def4dfdfe4baa5e606a3847f40
Signed-off-by: Kamal Wadhwa <quic_kamalw@quicinc.com>
WLAN has a requirement to trigger a PBS sequence for XO
calibration for factory testing. As part of this feature
expose a new register under PMK8550 SDAM2, which will
be used by PBS for reading XO trims settings.
Change-Id: I620b2d9d0ca6b7452f693ff665ddf995f17e4e2c
Signed-off-by: Kamal Wadhwa <quic_kamalw@quicinc.com>
WLAN has a requirement to trigger a PBS sequence for XO calibration
for factory testing. To support this, expose a new register under
PMK8550 SDAM2 for clients to write input data into and a new PBS
regulator on which clients can vote to trigger the PBS sequence.
Change-Id: Ia314c8cba7a6205943b99e7530990ea6dde8b09c
Signed-off-by: Kamal Wadhwa <quic_kamalw@quicinc.com>
This change removes support for display clock scaling
through mmrm is not supported in kera target.
Change-Id: Idb83968784dcd1e6cabc5bc107a5bd8013612686
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
Signed-off-by: lnxdisplay <lnxdisplay@localhost>
