Add bindings documentation for qcom,pmic-ecid. PMIC ECID provides the
PMIC specific information for identification.
Change-Id: I012670359ad1b1c4aea92f59b9430efc6e446f5f
Signed-off-by: Brindha T<quic_brint@quicinc.com>
Add devices to track CPU LPMs, SoC level LPMs, and system pm
violators.
Change-Id: I65a0dfeb814b47bdfcc4468ec8f1e7f63338581c
Signed-off-by: Sneh Mankad <quic_smankad@quicinc.com>
Update clk div factor entries for TX and VA macros to reflect
proper HW configuration.
Change-Id: Ic5456d7e30245a484b6a4888835c7e6f838eb92b
Signed-off-by: Ravulapati Vishnu Vardhan Rao <quic_visr@quicinc.com>
Update the slave address for slave charger debug support.
As well as update the slave address for glink adc channels
to fix reading I/O errors.
Change-Id: If1a0725aeeb1a67d7a19a3a5629ca2be44ff674c
Signed-off-by: Tingguo Cheng <quic_tingguoc@quicinc.com>
To enable and disable mdp clock gating functionality with
cesta immediate vote approach, add disp_cc_io memory to
sde cesta. Add changes to enable ctl hyp property for
reserve reservation on datapath used in a VM.
Change-Id: Id10875ecb90acb8a922ef4e4788da13a764ea102
Signed-off-by: Sailesh Reddy Male <quic_reddymal@quicinc.com>
Add xo clock in sde_cesta for kera target. This will help
to vote for xo frequency during cesta idle time.
Change-Id: Ic4370c8a49ffbec2743c022e438280d371a5a968
Signed-off-by: Sailesh Reddy Male <quic_reddymal@quicinc.com>
Add display cesta related DT node on kera target. Move
the GDSC & MDP core clock from MDP to cesta node, as it
will be controlled through cesta. Add the cesta
related register offsets in trusted-vm DT.
Change-Id: I1f777f3402d8a4d7d57ca889206a4095447abb7d
Signed-off-by: Sailesh Reddy Male <quic_reddymal@quicinc.com>
To enable and disable mdp clock gating functionality with
cesta immediate vote approach, add disp_cc_io memory to
sde cesta. Add ctl hyp DT property for reserve reservation
on a datapath used in VM.
Change-Id: I4c1b900dfb5e1a7d725aea80b4519bc1f9472e03
Signed-off-by: Sampurna Bolloju <quic_sampboll@quicinc.com>
Fix the memory mapping error for non dma-coherent target Monaco
when iommu-dma is used as "fastmap" by changing it to "atomic".
Hence, Change iommu-dma to atomic setting.
Change-Id: Ic21cbd4d5e9e429dd6aa577652d0ccb1a9acc99c
Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com>
Update cpu pause mappings to cpu tsens sensors for tuna.
Change-Id: I998e4e916e8f552d2705cd51b1d6053070fc2470
Signed-off-by: Priyansh Jain <quic_priyjain@quicinc.com>
Update ESI affinity mask in tuna device tree for UFS
performance reasons.
Change-Id: Ie06355e2d2604553da0f1e72b6d46032c55cdcf4
Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
Reserve 24kb to dcc on TZ while HLOS have 8 KB.
Change-Id: Ic30e6c0c32d6994e495091b4bddfa07e55c36285
Signed-off-by: songchai <quic_songchai@quicinc.com>
Add 60hz and 90hz support for VTDR6130 panel on tuna target.
Change-Id: Iad6d7514f241be42bf2cd8addaefa2d3fb1e89a8
Signed-off-by: Abhinav Saurabh <quic_abhisaur@quicinc.com>
Signed-off-by: lnxdisplay <lnxdisplay@localhost>
Update in Sharp qhd+ panel GPIO name as per recent change
from supplier and enablement of its physical panel in Kera.
Change-Id: I15115714f5e719eed63e741bc7aef8b2fb608c0d
Signed-off-by: Abhinav Saurabh <quic_abhisaur@quicinc.com>
Signed-off-by: lnxdisplay <lnxdisplay@localhost>
Reserves memory region to enable continuous splash
and ramdump on tuna target.
Change-Id: I0c2da9b0093923b83344e0bf3927022eceb30326
Signed-off-by: Sailesh Reddy Male <quic_reddymal@quicinc.com>
Signed-off-by: lnxdisplay <lnxdisplay@localhost>
Reserve 16kb to dcc on TZ while HLOS have 16 KB.
Change-Id: Ic30e6c0c32d6994e495091b4bddfa07e55c36285
Signed-off-by: songchai <quic_songchai@quicinc.com>
