ARM: dts: msm: reserve memory region for splash and ramdump
Reserves memory region to enable continuous splash and ramdump on tuna target. Change-Id: I0c2da9b0093923b83344e0bf3927022eceb30326 Signed-off-by: Sailesh Reddy Male <quic_reddymal@quicinc.com> Signed-off-by: lnxdisplay <lnxdisplay@localhost>
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lnxdisplay
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@@ -1,6 +1,6 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/clock/qcom,dispcc-tuna.h>
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@@ -14,6 +14,18 @@
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clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
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clock-names = "mdp_core_clk";
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};
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disp_rdump_memory: disp_rdump_region@0xfc800000 {
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reg = <0xfc800000 0x00800000>;
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label = "disp_rdump_region";
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};
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};
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&reserved_memory {
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splash_memory: splash_region {
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reg = <0x0 0xFC800000 0x0 0x02B00000>;
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label = "cont_splash_region";
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};
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};
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&sde_dsi {
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@@ -1,6 +1,6 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
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@@ -183,6 +183,7 @@
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smmu_sde_iommu_region_partition: smmu_sde_iommu_region_partition {
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iommu-addresses = <&smmu_sde_unsec 0x0 0x00060000>,
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<&smmu_sde_unsec 0xFC800000 0x02B00000>,
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<&smmu_sde_sec 0x0 0x00020000>;
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};
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