From 3253c6e1eae380da6751a76381b1da61ae7c718e Mon Sep 17 00:00:00 2001
From: Sailesh Reddy Male <quic_reddymal@quicinc.com>
Date: Fri, 3 Jan 2025 12:24:22 +0530
Subject: [PATCH] ARM: dts: msm: reserve memory region for splash and ramdump

Reserves memory region to enable continuous splash
and ramdump on tuna target.

Change-Id: I0c2da9b0093923b83344e0bf3927022eceb30326
Signed-off-by: Sailesh Reddy Male <quic_reddymal@quicinc.com>
Signed-off-by: lnxdisplay <lnxdisplay@localhost>
---
 display/kera-sde-display.dtsi | 14 +++++++++++++-
 display/kera-sde.dtsi         |  3 ++-
 2 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/display/kera-sde-display.dtsi b/display/kera-sde-display.dtsi
index 9404dfd8..ee0d4543 100644
--- a/display/kera-sde-display.dtsi
+++ b/display/kera-sde-display.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: BSD-3-Clause
 /*
- * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <dt-bindings/clock/qcom,dispcc-tuna.h>
@@ -14,6 +14,18 @@
 		clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
 		clock-names = "mdp_core_clk";
 	};
+
+	disp_rdump_memory: disp_rdump_region@0xfc800000 {
+		reg = <0xfc800000 0x00800000>;
+		label = "disp_rdump_region";
+	};
+};
+
+&reserved_memory {
+	splash_memory: splash_region {
+		reg = <0x0 0xFC800000 0x0 0x02B00000>;
+		label = "cont_splash_region";
+	};
 };
 
 &sde_dsi {
diff --git a/display/kera-sde.dtsi b/display/kera-sde.dtsi
index 0b5dc6c9..bb73d70f 100644
--- a/display/kera-sde.dtsi
+++ b/display/kera-sde.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: BSD-3-Clause
 /*
- * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
@@ -183,6 +183,7 @@
 
 	smmu_sde_iommu_region_partition: smmu_sde_iommu_region_partition {
 		iommu-addresses = <&smmu_sde_unsec 0x0 0x00060000>,
+				  <&smmu_sde_unsec 0xFC800000 0x02B00000>,
 				  <&smmu_sde_sec 0x0 0x00020000>;
 	};