ARM: dts: msm: support 4k sharp panel on Tuna CDP
Support 4k sharp panel on Tuna CDP. Change-Id: Ifdc1fa4edfe7ac752e1e4d8ab56d4735427d633b Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com> Signed-off-by: lnxdisplay <lnxdisplay@localhost>
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lnxdisplay
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@@ -259,6 +259,24 @@
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qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
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};
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&dsi_sharp_4k_dsc_cmd {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lcd>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
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qcom,mdss-dsi-bl-min-level = <1>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,platform-reset-gpio = <&tlmm 14 0>;
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qcom,platform-bklight-en-gpio = <&pm8550vs_d_gpios 4 0>;
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};
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&dsi_sharp_4k_dsc_video {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lcd>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
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qcom,mdss-dsi-bl-min-level = <1>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,platform-reset-gpio = <&tlmm 14 0>;
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qcom,platform-bklight-en-gpio = <&pm8550vs_d_gpios 4 0>;
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};
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&dsi_sharp_qhd_plus_dsc_cmd {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lcd>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
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@@ -18,6 +18,8 @@
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#include "dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi"
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#include "dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi"
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#include "dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi"
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#include "dsi-panel-sharp-dsc-4k-cmd.dtsi"
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#include "dsi-panel-sharp-dsc-4k-video.dtsi"
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#include "dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi"
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#include "dsi-panel-sharp-dsc-qhd-plus-video.dtsi"
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#include "dsi-panel-sim-cmd-au.dtsi"
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@@ -748,6 +750,48 @@
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};
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};
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&dsi_sharp_4k_dsc_cmd {
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qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
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qcom,mdss-dsi-panel-status-check-mode = "reg_read";
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qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c];
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qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
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qcom,mdss-dsi-panel-status-value = <0x77>;
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qcom,mdss-dsi-panel-on-check-value = <0x77>;
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qcom,mdss-dsi-panel-status-read-length = <1>;
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qcom,esd-check-enabled;
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qcom,mdss-dsi-display-timings {
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timing@0 {
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qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06
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06 07 02 04 00 15 0b];
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qcom,display-topology = <2 2 2>;
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qcom,default-topology-index = <0>;
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};
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};
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};
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&dsi_sharp_4k_dsc_video {
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qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
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qcom,mdss-dsi-panel-status-check-mode = "reg_read";
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qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c];
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qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
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qcom,mdss-dsi-panel-status-value = <0x77>;
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qcom,mdss-dsi-panel-on-check-value = <0x77>;
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qcom,mdss-dsi-panel-status-read-length = <1>;
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qcom,esd-check-enabled;
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qcom,mdss-dsi-display-timings {
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timing@0 {
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qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06
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06 07 02 04 00 15 0b];
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qcom,display-topology = <2 2 2>;
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qcom,default-topology-index = <0>;
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};
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};
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};
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&dsi_sharp_qhd_plus_dsc_cmd {
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qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
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@@ -1,6 +1,6 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/clock/qcom,dispcc-tuna.h>
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@@ -214,6 +214,10 @@
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};
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};
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&dsi_sharp_4k_dsc_cmd {
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qcom,ulps-enabled;
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};
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&dsi_sim_cmd {
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qcom,ulps-enabled;
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qcom,mdss-dsi-display-timings {
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