Add devices to track CPU LPMs, SoC level LPMs, and system pm
violators.
Change-Id: I65a0dfeb814b47bdfcc4468ec8f1e7f63338581c
Signed-off-by: Sneh Mankad <quic_smankad@quicinc.com>
Add show-resume-irqs feature to show the irq number that triggered
suspend exit.
Change-Id: I54c59bdc1ae476ca7a86fd34976744eb3db6dcf9
Signed-off-by: Sneh Mankad <quic_smankad@quicinc.com>
Add PDC interrupt controller as wakeup-parent to enable
TLMM interrupts to wake up the SoC.
Change-Id: I3b75f257153ffbc4cac6d58f2f57bdb70cf07913
Signed-off-by: Sneh Mankad <quic_smankad@quicinc.com>
Add idle states for CPU and CPU clusters, add PSCI device to
enable CPU to enter LPMs.
Additionally, update APPS RSC device to be in cluster power
domain to handle RSC activites when cluster is powering off.
Change-Id: Ibe2fa720bc5e81084d380b2e5dc4f8fa8910566c
Signed-off-by: Sneh Mankad <quic_smankad@quicinc.com>
Added new dtsi flag 'qcom,suspend-ignore-children', to ignore
dependencies on children by runtime PM framework, this helps to
exit quickly from msm_geni_serial_runtime_suspend and save power.
Change-Id: I69d18296c196d79972319a51084c068cbb031621
Signed-off-by: Chandana Kishori Chiluveru <quic_cchiluve@quicinc.com>
Add all 3 PCIe RC configurations for sdxkova. The number of address
cells and size cells are seen as 2 in msm-imem. Based on this add the
register base addresses, MSI register addresses, Host address in ranges
as 64-bit addresses.
Update the PHY settings from latest HSR.
- For PCIe0 and PCIe1 there are no changes in PHY settings, update
the corresponding PHY versions to v1.11 and v1.12.
- For PCIe2, add one change (PCS_G3S2_PRE_GAIN) as per the PHY
version v1.5.
Change-Id: I09519045a13e96878046d905bbe6f2378578c464
Signed-off-by: Sai Chaitanya Kaveti <quic_skaveti@quicinc.com>
IMEM gets updated with Modem DSM memory region info when Modem taken out
of reset by APPS and the info is used for collection of coredumps.
Change-Id: If549119c1516f8a995978c419fcb74b3d3e3ed9d
Signed-off-by: Khaja Hussain Shaik Khaji <quic_kshaikkh@quicinc.com>
Change imem node ranges to map imem address space to the
child node's address space correctly.
Change-Id: Ic4ec5cbf233011f48341b7c2788e1cf983a2dc7b
Signed-off-by: Khaja Hussain Shaik Khaji <quic_kshaikkh@quicinc.com>
Add NAND controller support for sdxkova and its platforms.
Change-Id: I14f55288c2deaca96011276f1c876b7099062eef
Signed-off-by: Madhusudhan Sana <quic_msana@quicinc.com>
Add SPS module to device tree. SPS (Smart Peripheral System)
enables the support of all BAMs in the system which provide DMA
functionality to various peripherals for Niobe.
Change-Id: I54640b7c444744f527414280021186fd90e0acf5
Signed-off-by: Krishna Chaithanya Reddy G <quic_kgangapu@quicinc.com>
sdxkova uses PMK8550, PM7550BA and PMX75. Add SPMI slave device
and some of the peripheral devices for PMX75.
Update PMIC overlay file to add devices from these PMICs that
are common for all sdxkova platforms. Also add PM7550BA-related
configurations required for the IDP MBB platform.
Add spmi_debug_bus so that PMIC peripherals can be accessed via
debug bus on sdxkova devices where the fuse is not blown. This
is useful for debugging.
Add PMIC Glink devices and their client devices. The PMIC Glink
device with name PMIC_RTR_ADSP_APPS supports the clients: ucsi,
altmode, and battery_charger. The PMIC Glink device with name
PMIC_LOGS_ADSP_APPS supports the clients: battery_debug,
pmic_glink_debug, charger_ulog_glink, and glink_adc.
Change-Id: I6dc40cc36a46c1b34edd274655306dadd3143ebf
Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com>
Added QUPv3(I2C, SPI and UART), GPI DT nodes and
QUPv3 pinctrl support for sdxkova.
Change-Id: I55394b443be7dd2a37b04e62fa2f308ebdf67753
Signed-off-by: Krishna Chaithanya Reddy G <quic_kgangapu@quicinc.com>
The initialization of the OPP table from the device tree is failing
because the OPP framework expects the CPUFreq node to act as a clock
provider due to the presence of the clocks property in CPU nodes.
However, the qcom-cpufreq-hw scaling driver doesn't have the support
for handling the CPUFreq node as a clock provider, resulting in an
-EPROBE_DEFER error. Thus, to resolve this issue, remove the clocks
property from the CPU nodes.
Change-Id: I243807f58dc82c55f4ec390c09752b8652ac2706
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
This change removes the dependency of TLMM with PDC so that
it can probe without PDC. We can re-enable PDC dependency
once we validate PDC changes.
Change-Id: I3b78b6a5418ecf98675d31a8b5e47bdeeeedbd6b
Signed-off-by: Khaja Hussain Shaik Khaji <quic_kshaikkh@quicinc.com>
Upsteam DT does not have phandle for the armv8-timer node,
hence DT overlay is failing during ABL as phandle is necessary
for the overlay. Hence removed the timer node which was included
via upstream DT and added it along with a phandle.
Change-Id: Iba5b3ec985814fa44125c5918900dbf87cb45a6b
Signed-off-by: Keval Kulkarni <quic_kevalbha@quicinc.com>
This change moves the APSS RSC clients under APSS RSC node
as child nodes. Earlier those were wrongly added under SOC.
Change-Id: I7e04b78a138eae18384a4ee976ff2bc0018ea30d
Signed-off-by: Raghavendra Kakarla <quic_rkakarla@quicinc.com>
Add devicetree nodes to enable qmp communication with aop and tme.
Change-Id: I62d0020ca600820dd8ce256ee4cbe1ce0dc17b15
Signed-off-by: Vishnu Santhosh <quic_vishsant@quicinc.com>
Add the smp2p device nodes to enable smp2p communication with remote
processors. This adds the configuration for Modem on sdxkova.
Change-Id: Ibd86fcf2a589bfb9f16a645797113f0f0345c81a
Signed-off-by: Vishnu Santhosh <quic_vishsant@quicinc.com>
Currently the interconnect provider framework is expecting
the tag QCOM_ICC_TAG_ALWAYS as part of dtsi node of QUP.
In commit 481c435dd1 ("ARM: dts: qcom: sdxkova: update
interconnect providers with bcm-voter-names") interconnect
framework is not expecting the tag QCOM_ICC_TAG_ALWAYS, and
instead it is enabled by default or expects clients to override.
So, updated the QUPv3 and UART interconnects to remove the
additional interconnect tag.
Change-Id: If3780ec7156487f07cc8892a43341d1d9cb88b96
Signed-off-by: Krishna Chaithanya Reddy G <quic_kgangapu@quicinc.com>
Include IPCC test node for sdxkova, so IPCC kernel-tests can
run on sdxkova.
Change-Id: I96e4f925d62eec54455b8f03f46217fc402e43a5
Signed-off-by: Keval Kulkarni <quic_kevalbha@quicinc.com>
Signed-off-by: Khaja Hussain Shaik Khaji <quic_kshaikkh@quicinc.com>
Add ipcc node for sdxkova to enable inter processor
communication controller.
Adjust reg format for tz-log node.
Change-Id: I5519f5b8bfc02b2c85c1654a2f39c4ec61fdee9f
Signed-off-by: Keval Kulkarni <quic_kevalbha@quicinc.com>
Signed-off-by: Khaja Hussain Shaik Khaji <quic_kshaikkh@quicinc.com>
Update interconnect provider device nodes with bcm-voter-names to route
the bandwidth requests through appropriate DRV.
Add necessary clock handles to access the QoS registers.
Change-Id: I5c271682e0b3f094d85fa759e19f8a89ae8f0eff
Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
Add DWC3 USB controller device-tree nodes for sdxkova.
Change-Id: I9a44ad5d49dfb8bdadca04696c8580e283b5f2ec
Signed-off-by: Prashanth K <quic_prashk@quicinc.com>
Add support for GCC, DEBUGCC, GDSC and CPUFREQ-HW-DEBUG nodes
for sdxkova platform. While at it, update the cpufreq default
governor to performance.
Change-Id: Icba0ba93cf82e576e7b645c247d2d0e7f0f6da3f
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Add the TLMM GPIO reserved ranges for the sdxkova platform.
The reserved range is set to <110 6> to ensure proper
allocation and avoid conflicts with other GPIOs.
Change-Id: I6b01f9c6a21f918df078dcbe078be602dd889898
Signed-off-by: Khaja Hussain Shaik Khaji <quic_kshaikkh@quicinc.com>
