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ARM: dts: msm: Add eMMC & SD card support for sdxkova

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Add eMMC & SD card support for sdxkova.

Change-Id: I0ff97235e8dc6e8fcbe80a5ae811b3832130a75c
Signed-off-by: Sarthak Garg <quic_sartgarg@quicinc.com>
This commit is contained in:
Sarthak Garg
2024-07-25 15:33:32 +05:30
committed by Madhusudhan Sana
parent 88be481e76
commit 5b16785b02
1 changed files with 174 additions and 0 deletions
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174
qcom/sdxkova.dtsi
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@@ -128,6 +128,7 @@
aliases: aliases {
serial0 = &uart1;
mmc0 = &sdhc_1; /*SDC1 eMMC slot*/
};
};
@@ -164,6 +165,107 @@
&tlmm {
gpio-reserved-ranges = <110 6>;
sdc1_emmc_on: sdc1_emmc_on {
clk {
pins = "sdc1_clk";
bias-disable;
drive-strength = <16>;
};
cmd {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <10>;
};
data {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <10>;
};
rclk {
pins = "sdc1_rclk";
bias-pull-down;
};
};
sdc1_emmc_off: sdc1_emmc_off {
clk {
pins = "sdc1_clk";
bias-disable;
drive-strength = <2>;
};
cmd {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <2>;
};
data {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <2>;
};
rclk {
pins = "sdc1_rclk";
bias-pull-down;
};
};
sdc1_sd_on: sdc1_sd_on {
clk {
pins = "sdc1_clk";
bias-disable;
drive-strength = <16>;
};
cmd {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <10>;
};
data {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <10>;
};
sd-cd {
pins = "gpio103";
bias-pull-up;
drive-strength = <2>;
};
};
sdc1_sd_off: sdc1_sd_off {
clk {
pins = "sdc1_clk";
bias-disable;
drive-strength = <2>;
};
cmd {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <2>;
};
data {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <2>;
};
sd-cd {
pins = "gpio103";
bias-pull-up;
drive-strength = <2>;
};
};
};
&qupv3_id_0 {
@@ -485,6 +587,78 @@
mbox-desc-offset = <0x0>;
#mbox-cells = <1>;
};
sdhc1_opp_table: sdhc1-opp-table {
compatible = "operating-points-v2";
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
opp-peak-kBps = <1600000 56000>;
opp-avg-kBps = <104000 0>;
};
opp-384000000 {
opp-hz = /bits/ 64 <384000000>;
opp-peak-kBps = <7000000 360000>;
opp-avg-kBps = <400000 0>;
};
};
sdhc_1: sdhci@8804000 {
status = "disabled";
compatible = "qcom,sdhci-msm-v5";
reg = <0x0 0x08804000 0x0 0x1000>;
reg-names = "hc";
interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
bus-width = <4>;
no-sdio;
qcom,restore-after-cx-collapse;
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>;
clock-names = "iface", "core";
/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
qcom,dll-hsr-list = <0x0007442C 0x0 0x10
0x090106C0 0x80040868>;
iommus = <&apps_smmu 0x00A0 0x0>;
dma-coherent;
qcom,iommu-dma = "fastmap";
qcom,iommu-dma-addr-pool = <0x0 0x20000000 0x0 0x10000000>;
qcom,iommu-geometry = <0x0 0x20000000 0x0 0x10000000>;
interconnects = <&system_noc MASTER_SDCC_1 &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_SDCC_1>;
interconnect-names = "sdhc-ddr","cpu-sdhc";
operating-points-v2 = <&sdhc1_opp_table>;
qos0 {
mask = <0x0f>;
vote = <44>;
};
};
sdhc2_opp_table: sdhc2-opp-table {
compatible = "operating-points-v2";
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
opp-peak-kBps = <1600000 56000>;
opp-avg-kBps = <50000 0>;
};
opp-192000000 {
opp-hz = /bits/ 64 <192000000>;
opp-peak-kBps = <7000000 360000>;
opp-avg-kBps = <104000 0>;
};
};
};
&gcc {