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ARM: dts: msm: Add NAND controller support for sdxkova

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Add NAND controller support for sdxkova and its platforms.

Change-Id: I14f55288c2deaca96011276f1c876b7099062eef
Signed-off-by: Madhusudhan Sana <quic_msana@quicinc.com>
This commit is contained in:
Madhusudhan Sana
2024-08-30 08:16:27 +05:30
parent 711ff0a234
commit 455414457b
3 changed files with 39 additions and 0 deletions
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4
qcom/sdxkova-idp-m2.dtsi
View File

@@ -5,3 +5,7 @@
&soc {
};
&qnand_1 {
status = "ok";
};

4
qcom/sdxkova-idp-mbb.dtsi
View File

@@ -30,6 +30,10 @@
operating-points-v2 = <&sdhc2_opp_table>;
};
&qnand_1 {
status = "ok";
};
&pmk8550_vadc {
/* PM8550BA Channel nodes */
pm7550ba_offset_ref {

31
qcom/sdxkova.dtsi
View File

@@ -1707,6 +1707,37 @@
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
};
qnand_1: nand@1c98000 {
compatible = "qcom,msm-nand";
reg = <0x0 0x01c98000 0x0 0x1000>,
<0x0 0x01c9C000 0x0 0x1c000>;
reg-names = "nand_phys",
"bam_phys";
qcom,reg-adjustment-offset = <0x4000>;
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "bam_irq";
clock-names = "core_clk";
clocks = <&rpmhcc RPMH_QPIC_CLK>;
interconnects = <&system_noc MASTER_QPIC &mc_virt SLAVE_EBI1>;
interconnect-names = "nand-ddr";
qcom,msm-bus,name = "qpic_nand";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<0 0>,
/* Voting for max b/w on PNOC bus for now */
<1057800 725760>;
iommus = <&apps_smmu 0x100 0x3>;
qcom,iommu-dma = "atomic";
dma-coherent;
status = "disabled";
};
};
&gcc {