723 lines
16 KiB
Plaintext
723 lines
16 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/soc/qcom,ipcc.h>
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#include "sdx75.dtsi"
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/delete-node/ &apps_smmu;
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/delete-node/ &tcsr_mutex;
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#include "msm-arm-smmu-sdxkova.dtsi"
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/{
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qcom_tzlog: tz-log@14680720 {
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compatible = "qcom,tz-log";
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reg = <0x0 0x14680720 0x0 0x3000>;
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qcom,hyplog-enabled;
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hyplog-address-offset = <0x410>;
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hyplog-size-offset = <0x414>;
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};
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/delete-node/ reserved-memory;
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reserved_memory: reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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system_cma: linux,cma {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x2000000>;
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linux,cma-default;
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};
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};
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soc: soc {
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/delete-node/ rsc@17a00000;
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apps_rsc: rsc@17a00000 {
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label = "apps_rsc";
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compatible = "qcom,rpmh-rsc";
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reg = <0x0 0x17a00000 0x0 0x10000>,
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<0x0 0x17a10000 0x0 0x10000>,
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<0x0 0x17a20000 0x0 0x10000>;
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reg-names = "drv-0", "drv-1", "drv-2";
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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qcom,drv-count = <3>;
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apps_rsc_drv2: drv@2 {
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qcom,drv-id = <2>;
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qcom,tcs-offset = <0xd00>;
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channel@0 {
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qcom,tcs-offset = <0xd00>;
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qcom,tcs-config = <ACTIVE_TCS 3>,
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<SLEEP_TCS 2>,
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<WAKE_TCS 2>,
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<FAST_PATH_TCS 0>,
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<CONTROL_TCS 0>;
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};
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apps_bcm_voter: bcm-voter {
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compatible = "qcom,bcm-voter";
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};
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rpmhcc: clock-controller {
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compatible = "qcom,sdx75-rpmh-clk";
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clocks = <&xo_board>;
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clock-names = "xo";
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#clock-cells = <1>;
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};
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rpmhpd: power-controller {
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compatible = "qcom,sdx75-rpmhpd";
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#power-domain-cells = <1>;
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operating-points-v2 = <&rpmhpd_opp_table>;
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rpmhpd_opp_table: opp-table {
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compatible = "operating-points-v2";
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rpmhpd_opp_ret: opp-16 {
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opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
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};
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rpmhpd_opp_min_svs: opp-48 {
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opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
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};
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rpmhpd_opp_low_svs: opp-64 {
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opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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};
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rpmhpd_opp_svs: opp-128 {
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opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
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};
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rpmhpd_opp_svs_l1: opp-192 {
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opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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};
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rpmhpd_opp_nom: opp-256 {
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opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
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};
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rpmhpd_opp_nom_l1: opp-320 {
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opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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};
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rpmhpd_opp_nom_l2: opp-336 {
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opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
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};
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rpmhpd_opp_turbo: opp-384 {
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opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
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};
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rpmhpd_opp_turbo_l1: opp-416 {
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opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
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};
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};
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};
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};
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};
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};
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firmware: firmware { };
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aliases: aliases {
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serial0 = &uart1;
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mmc0 = &sdhc_1; /*SDC1 eMMC slot*/
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};
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};
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&clk_virt {
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#interconnect-cells = <1>;
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qcom,bcm-voter-names = "hlos";
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};
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&mc_virt {
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#interconnect-cells = <1>;
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qcom,bcm-voter-names = "hlos";
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};
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&system_noc {
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#interconnect-cells = <1>;
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qcom,bcm-voter-names = "hlos";
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clocks = <&gcc GCC_SYS_NOC_MVMSS_CLK>;
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};
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&pcie_anoc {
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#interconnect-cells = <1>;
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qcom,bcm-voter-names = "hlos";
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};
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&dc_noc {
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#interconnect-cells = <1>;
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qcom,bcm-voter-names = "hlos";
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};
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&gem_noc {
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#interconnect-cells = <1>;
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qcom,bcm-voter-names = "hlos";
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};
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&tlmm {
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gpio-reserved-ranges = <110 6>;
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sdc1_emmc_on: sdc1_emmc_on {
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clk {
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pins = "sdc1_clk";
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bias-disable;
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drive-strength = <16>;
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};
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cmd {
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pins = "sdc1_cmd";
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bias-pull-up;
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drive-strength = <10>;
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};
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data {
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pins = "sdc1_data";
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bias-pull-up;
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drive-strength = <10>;
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};
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rclk {
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pins = "sdc1_rclk";
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bias-pull-down;
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};
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};
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sdc1_emmc_off: sdc1_emmc_off {
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clk {
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pins = "sdc1_clk";
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bias-disable;
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drive-strength = <2>;
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};
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cmd {
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pins = "sdc1_cmd";
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bias-pull-up;
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drive-strength = <2>;
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};
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data {
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pins = "sdc1_data";
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bias-pull-up;
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drive-strength = <2>;
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};
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rclk {
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pins = "sdc1_rclk";
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bias-pull-down;
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};
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};
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sdc1_sd_on: sdc1_sd_on {
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clk {
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pins = "sdc1_clk";
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bias-disable;
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drive-strength = <16>;
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};
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cmd {
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pins = "sdc1_cmd";
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bias-pull-up;
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drive-strength = <10>;
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};
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data {
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pins = "sdc1_data";
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bias-pull-up;
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drive-strength = <10>;
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};
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sd-cd {
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pins = "gpio103";
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bias-pull-up;
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drive-strength = <2>;
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};
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};
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sdc1_sd_off: sdc1_sd_off {
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clk {
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pins = "sdc1_clk";
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bias-disable;
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drive-strength = <2>;
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};
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cmd {
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pins = "sdc1_cmd";
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bias-pull-up;
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drive-strength = <2>;
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};
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data {
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pins = "sdc1_data";
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bias-pull-up;
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drive-strength = <2>;
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};
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sd-cd {
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pins = "gpio103";
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bias-pull-up;
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drive-strength = <2>;
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};
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};
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};
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&qupv3_id_0 {
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interconnects =
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<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>;
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interconnect-names = "qup-core";
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status = "ok";
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};
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&uart1 {
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interconnects =
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<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
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<&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>;
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status = "ok";
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};
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&scm {
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qcom,dload-mode = <&tcsr 0x13000>;
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};
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&firmware {
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qtee_shmbridge {
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compatible = "qcom,tee-shared-memory-bridge";
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};
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};
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#include "sdxkova-regulators.dtsi"
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&chosen {
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bootargs = "cpufreq.default_governor=performance";
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};
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&soc {
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clocks {
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emac0_sgmiiphy_mac_rclk: emac0_sgmiiphy_mac_rclk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "emac0_sgmiiphy_mac_rclk";
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#clock-cells = <0>;
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};
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emac0_sgmiiphy_mac_tclk: emac0_sgmiiphy_mac_tclk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "emac0_sgmiiphy_mac_tclk";
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#clock-cells = <0>;
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};
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emac0_sgmiiphy_rclk: emac0_sgmiiphy_rclk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "emac0_sgmiiphy_rclk";
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#clock-cells = <0>;
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};
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emac0_sgmiiphy_tclk: emac0_sgmiiphy_tclk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "emac0_sgmiiphy_tclk";
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#clock-cells = <0>;
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};
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emac1_sgmiiphy_mac_rclk: emac1_sgmiiphy_mac_rclk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "emac1_sgmiiphy_mac_rclk";
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#clock-cells = <0>;
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};
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emac1_sgmiiphy_mac_tclk: emac1_sgmiiphy_mac_tclk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "emac1_sgmiiphy_mac_tclk";
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#clock-cells = <0>;
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};
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emac1_sgmiiphy_rclk: emac1_sgmiiphy_rclk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "emac1_sgmiiphy_rclk";
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#clock-cells = <0>;
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};
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emac1_sgmiiphy_tclk: emac1_sgmiiphy_tclk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "emac1_sgmiiphy_tclk";
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#clock-cells = <0>;
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};
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pcie20_phy_aux_clk: pcie20_phy_aux_clk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "pcie20_phy_aux_clk";
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#clock-cells = <0>;
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};
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pcie_1_pipe_clk: pcie_1_pipe_clk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "pcie_1_pipe_clk";
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#clock-cells = <0>;
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};
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pcie_2_pipe_clk: pcie_2_pipe_clk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "pcie_2_pipe_clk";
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#clock-cells = <0>;
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};
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pcie_pipe_clk: pcie_pipe_clk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "pcie_pipe_clk";
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#clock-cells = <0>;
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};
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usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
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#clock-cells = <0>;
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};
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};
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/* GCC GDSCs */
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gcc_emac0_gdsc: qcom,gdsc@f1004 {
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compatible = "qcom,gdsc";
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reg = <0x0 0xf1004 0x0 0x4>;
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regulator-name = "gcc_emac0_gdsc";
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parent-supply = <&VDD_CX_LEVEL>;
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qcom,retain-regs;
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qcom,support-hw-trigger;
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};
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gcc_emac1_gdsc: qcom,gdsc@f2004 {
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compatible = "qcom,gdsc";
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reg = <0x0 0xf2004 0x0 0x4>;
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regulator-name = "gcc_emac1_gdsc";
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parent-supply = <&VDD_CX_LEVEL>;
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qcom,retain-regs;
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qcom,support-hw-trigger;
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};
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gcc_pcie_1_gdsc: qcom,gdsc@e7004 {
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compatible = "qcom,gdsc";
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reg = <0x0 0xe7004 0x0 0x4>;
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regulator-name = "gcc_pcie_1_gdsc";
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parent-supply = <&VDD_CX_LEVEL>;
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qcom,retain-regs;
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qcom,support-hw-trigger;
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};
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gcc_pcie_1_phy_gdsc: qcom,gdsc@d6004 {
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compatible = "qcom,gdsc";
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reg = <0x0 0xd6004 0x0 0x4>;
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regulator-name = "gcc_pcie_1_phy_gdsc";
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parent-supply = <&VDD_MXA_LEVEL>;
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qcom,retain-regs;
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qcom,support-hw-trigger;
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};
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gcc_pcie_2_gdsc: qcom,gdsc@e8004 {
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compatible = "qcom,gdsc";
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reg = <0x0 0xe8004 0x0 0x4>;
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regulator-name = "gcc_pcie_2_gdsc";
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parent-supply = <&VDD_CX_LEVEL>;
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qcom,retain-regs;
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qcom,support-hw-trigger;
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};
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gcc_pcie_2_phy_gdsc: qcom,gdsc@ee004 {
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compatible = "qcom,gdsc";
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reg = <0x0 0xee004 0x0 0x4>;
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regulator-name = "gcc_pcie_2_phy_gdsc";
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parent-supply = <&VDD_MXA_LEVEL>;
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qcom,retain-regs;
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qcom,support-hw-trigger;
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};
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gcc_pcie_gdsc: qcom,gdsc@d3004 {
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compatible = "qcom,gdsc";
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reg = <0x0 0xd3004 0x0 0x4>;
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regulator-name = "gcc_pcie_gdsc";
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parent-supply = <&VDD_MXA_LEVEL>;
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qcom,retain-regs;
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qcom,support-hw-trigger;
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};
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gcc_pcie_phy_gdsc: qcom,gdsc@d4004 {
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compatible = "qcom,gdsc";
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reg = <0x0 0xd4004 0x0 0x4>;
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regulator-name = "gcc_pcie_phy_gdsc";
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parent-supply = <&VDD_MXA_LEVEL>;
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qcom,retain-regs;
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qcom,support-hw-trigger;
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};
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gcc_usb30_gdsc: qcom,gdsc@a7004 {
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compatible = "qcom,gdsc";
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reg = <0x0 0xa7004 0x0 0x4>;
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regulator-name = "gcc_usb30_gdsc";
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parent-supply = <&VDD_MXA_LEVEL>;
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qcom,retain-regs;
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};
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gcc_usb3_phy_gdsc: qcom,gdsc@a8008 {
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compatible = "qcom,gdsc";
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reg = <0x0 0xa8008 0x0 0x4>;
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regulator-name = "gcc_usb3_phy_gdsc";
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parent-supply = <&VDD_CX_LEVEL>;
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qcom,retain-regs;
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};
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apsscc: syscon@17aa0000 {
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compatible = "syscon";
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reg = <0x0 0x17aa0000 0x0 0x1c>;
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};
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mccc: syscon@190ba000 {
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compatible = "syscon";
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reg = <0x0 0x190ba000 0x0 0x54>;
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};
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debugcc: clock-controller@0 {
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compatible = "qcom,sdx75-debugcc";
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qcom,apsscc = <&apsscc>;
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qcom,gcc = <&gcc>;
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qcom,mccc = <&mccc>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc 0>;
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clock-names = "xo_clk_src",
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"gcc";
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#clock-cells = <1>;
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};
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qcom,cpufreq-hw-debug {
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compatible = "qcom,cpufreq-hw-epss-debug";
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qcom,freq-hw-domain = <&cpufreq_hw 0>;
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};
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ipcc_mproc: qcom,ipcc@408000 {
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compatible = "qcom,ipcc";
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reg = <0x0 0x408000 0x0 0x1000>;
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interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <3>;
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#mbox-cells = <2>;
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};
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llcc_device: cache-controller@19200000 {
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compatible = "qcom,sdxpinn-llcc";
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reg = <0x0 0x19200000 0x0 0x200000>;
|
|
reg-names = "llcc0_base";
|
|
interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
|
|
cap-based-alloc-and-pwr-collapse;
|
|
};
|
|
|
|
tcsr_mutex_block: syscon@1f40000 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0x1f40000 0x0 0x20000>;
|
|
};
|
|
|
|
tcsr_mutex: hwlock {
|
|
compatible = "qcom,tcsr-mutex";
|
|
syscon = <&tcsr_mutex_block 0 0x1000>;
|
|
#hwlock-cells = <1>;
|
|
};
|
|
|
|
tcsr: syscon@1fc0000 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0x1fc0000 0x0 0x30000>;
|
|
};
|
|
|
|
qcom,smp2p-modem {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <435>, <428>;
|
|
interrupt-parent = <&ipcc_mproc>;
|
|
interrupts = <IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>;
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <1>;
|
|
|
|
modem_smp2p_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
modem_smp2p_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
aoss_qmp: power-controller@c300000 {
|
|
compatible = "qcom,aoss-qmp";
|
|
reg = <0x0 0xc310000 0x0 0x1000>;
|
|
interrupt-parent = <&ipcc_mproc>;
|
|
interrupts = <IPCC_CLIENT_AOP
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc_mproc IPCC_CLIENT_AOP
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
|
|
#power-domain-cells = <1>;
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
qmp_aop: qcom,qmp-aop {
|
|
compatible = "qcom,qmp-mbox";
|
|
qcom,qmp = <&aoss_qmp>;
|
|
label = "aop";
|
|
#mbox-cells = <1>;
|
|
};
|
|
|
|
qmp_tme: qcom,qmp-tme {
|
|
compatible = "qcom,qmp-mbox";
|
|
qcom,remote-pid = <14>;
|
|
mboxes = <&ipcc_mproc IPCC_CLIENT_TME
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
mbox-names = "tme_qmp";
|
|
interrupt-parent = <&ipcc_mproc>;
|
|
interrupts = <IPCC_CLIENT_TME
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
|
|
label = "tme";
|
|
qcom,early-boot;
|
|
priority = <0>;
|
|
mbox-desc-offset = <0x0>;
|
|
#mbox-cells = <1>;
|
|
};
|
|
|
|
sdhc1_opp_table: sdhc1-opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-100000000 {
|
|
opp-hz = /bits/ 64 <100000000>;
|
|
opp-peak-kBps = <1600000 56000>;
|
|
opp-avg-kBps = <104000 0>;
|
|
};
|
|
|
|
opp-384000000 {
|
|
opp-hz = /bits/ 64 <384000000>;
|
|
opp-peak-kBps = <7000000 360000>;
|
|
opp-avg-kBps = <400000 0>;
|
|
};
|
|
};
|
|
|
|
sdhc_1: sdhci@8804000 {
|
|
status = "disabled";
|
|
|
|
compatible = "qcom,sdhci-msm-v5";
|
|
reg = <0x0 0x08804000 0x0 0x1000>;
|
|
reg-names = "hc";
|
|
|
|
interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "hc_irq", "pwr_irq";
|
|
|
|
bus-width = <4>;
|
|
no-sdio;
|
|
qcom,restore-after-cx-collapse;
|
|
|
|
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
|
|
<&gcc GCC_SDCC1_APPS_CLK>;
|
|
clock-names = "iface", "core";
|
|
|
|
/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
|
|
qcom,dll-hsr-list = <0x0007442C 0x0 0x10
|
|
0x090106C0 0x80040868>;
|
|
|
|
iommus = <&apps_smmu 0x00A0 0x0>;
|
|
dma-coherent;
|
|
qcom,iommu-dma = "fastmap";
|
|
qcom,iommu-dma-addr-pool = <0x0 0x20000000 0x0 0x10000000>;
|
|
qcom,iommu-geometry = <0x0 0x20000000 0x0 0x10000000>;
|
|
|
|
interconnects = <&system_noc MASTER_SDCC_1 &mc_virt SLAVE_EBI1>,
|
|
<&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_SDCC_1>;
|
|
interconnect-names = "sdhc-ddr","cpu-sdhc";
|
|
operating-points-v2 = <&sdhc1_opp_table>;
|
|
|
|
qos0 {
|
|
mask = <0x0f>;
|
|
vote = <44>;
|
|
};
|
|
};
|
|
|
|
sdhc2_opp_table: sdhc2-opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-100000000 {
|
|
opp-hz = /bits/ 64 <100000000>;
|
|
opp-peak-kBps = <1600000 56000>;
|
|
opp-avg-kBps = <50000 0>;
|
|
};
|
|
|
|
opp-192000000 {
|
|
opp-hz = /bits/ 64 <192000000>;
|
|
opp-peak-kBps = <7000000 360000>;
|
|
opp-avg-kBps = <104000 0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&gcc {
|
|
compatible = "qcom,sdx75-gcc", "syscon";
|
|
reg = <0x0 0x0080000 0x0 0x1f7400>;
|
|
vdd_cx-supply = <&VDD_CX_LEVEL>;
|
|
vdd_mx-supply = <&VDD_MXA_LEVEL>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&emac0_sgmiiphy_mac_rclk>,
|
|
<&emac0_sgmiiphy_mac_tclk>,
|
|
<&emac0_sgmiiphy_rclk>,
|
|
<&emac0_sgmiiphy_tclk>,
|
|
<&emac1_sgmiiphy_mac_rclk>,
|
|
<&emac1_sgmiiphy_mac_tclk>,
|
|
<&emac1_sgmiiphy_rclk>,
|
|
<&emac1_sgmiiphy_tclk>,
|
|
<&pcie20_phy_aux_clk>,
|
|
<&pcie_1_pipe_clk>,
|
|
<&pcie_2_pipe_clk>,
|
|
<&pcie_pipe_clk>,
|
|
<&sleep_clk>,
|
|
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
|
|
clock-names = "bi_tcxo",
|
|
"emac0_sgmiiphy_mac_rclk",
|
|
"emac0_sgmiiphy_mac_tclk",
|
|
"emac0_sgmiiphy_rclk",
|
|
"emac0_sgmiiphy_tclk",
|
|
"emac1_sgmiiphy_mac_rclk",
|
|
"emac1_sgmiiphy_mac_tclk",
|
|
"emac1_sgmiiphy_rclk",
|
|
"emac1_sgmiiphy_tclk",
|
|
"pcie20_phy_aux_clk",
|
|
"pcie_1_pipe_clk",
|
|
"pcie_2_pipe_clk",
|
|
"pcie_pipe_clk",
|
|
"sleep_clk",
|
|
"usb3_phy_wrapper_gcc_usb30_pipe_clk";
|
|
protected-clocks = <GCC_TLMM_125_CLK>,
|
|
<GCC_TLMM_125_CLK_SRC>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
#include "sdxkova-usb.dtsi"
|
|
#include "ipcc-test-sdxkova.dtsi"
|