Commit Graph

17 Commits

Author SHA1 Message Date
Karthik Anantha Ram
9899a066d3 ARM: dts: msm: Update OFE write ubwc config for Pakala
This change updates the UBWC write config for OFE on Pakala.

CRs-Fixed: 3833870
Change-Id: I21138604bdd7927f56c4ed6409537c0344ae1132
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
2024-06-10 00:03:04 -07:00
Atiya Kailany
9b361f64a4 ARM: dts: msm: Add flag indicating crmb api support
This flag is added in cpas node to indicate that the src clk
in this node supports crmb api passthrough when voting.

CRs-Fixed: 3799575
Change-Id: Ic11d376e2d04b49dad3185ef32ae863f60f1d759
Signed-off-by: Atiya Kailany <quic_akailany@quicinc.com>
2024-05-22 17:14:29 -07:00
Soumen Ghosh
f29ccb1222 ARM: dts: msm: correcting cci pinctrl information
cci1 pinctrl-2 and pinctrl-3 information was not correct,
added the correct information.

CRs-Fixed: 3809949
Change-Id: I38e06237d144ef324a0f8d4a756cb77630f8bf86
Signed-off-by: Soumen Ghosh <quic_soumeng@quicinc.com>
2024-05-15 22:28:16 -07:00
Mukund Madhusudan Atre
cc0099d021 ARM: dts: msm: Add property to max limit RT axi bw votes
Add cam-max-rt-axi-bw property to provide a max limiting value
for RT axi bw votes.

CRs-Fixed: 3780345
Change-Id: I14e330e02a0d2a9e978470b2c40ea4fe0e747749
Signed-off-by: Mukund Madhusudan Atre <quic_matre@quicinc.com>
2024-05-06 18:24:15 -07:00
Mukund Madhusudan Atre
dfb7c5948a ARM: dts: msm: Fix reg cam base for camera nodes in sun
Currently, the register base addresses in the reg cam base
property of camera nodes are incorrect. Update the values to
reflect the correct difference with camera base. Also, update
the reg base addresses in all the camera nodes for uniformity.

CRs-Fixed: 3762492
Change-Id: Idfa710a05b4e1f45ea6739b04ba739160b8b9f03
Signed-off-by: Mukund Madhusudan Atre <quic_matre@quicinc.com>
2024-03-28 18:00:21 -07:00
Soumen Ghosh
e17b23f800 ARM: dts: msm: enabling cesta and ddr drv
This change will help to enable CLK and DDR drv feature.

CRs-Fixed: 3736393
Change-Id: I6b9b76818f2d23d72936390fcfa8a961a894665b
Signed-off-by: Soumen Ghosh <quic_soumeng@quicinc.com>
2024-03-07 11:31:45 -08:00
Atiya Kailany
7e1660cc9b ARM: dts: msm: Adding lowsvsd1 vote level to device tree
This change adds lowsvsd1 vote level along with corresponding
rates to the device tree.

CRs-Fixed: 3678245
Change-Id: I99bc0cc781edfe9b31aedc1970d0d1b5ccded7d7
Signed-off-by: Atiya Kailany <quic_akailany@quicinc.com>
2024-02-13 11:45:01 -08:00
Soumen Ghosh
51741d2256 ARM: dts: msm: adding the 2MB iova region for LLCC
To make accessible LLCC register address space by ICP FW,
we need to map the 2MB. LLCC register region in SMMU context bank.

CRs-Fixed: 3701263
Change-Id: I2a95b918facef5fa9c9d47a7f04151f4779995c7
Signed-off-by: Soumen Ghosh <quic_soumeng@quicinc.com>
2024-01-29 22:42:29 -08:00
Soumen Ghosh
6fdb0bb346 ARM: dts: msm: replace existing use of iommu-dma-addr-pool with iommu-addresses
'qcom,iommu-dma-addr-pool' describe the addresses which a device CAN use
'iommu-addresses' describes the addresses it CANNOT use.

CRs-Fixed: 3697699
Change-Id: Ia0253d015073423ac50d0b4ace91278c7120f91f
Signed-off-by: Soumen Ghosh <quic_soumeng@quicinc.com>
2024-01-17 12:52:23 -08:00
Soumen Ghosh
7103074adc ARM: dts: msm: change the voltage corner name
soc util validation check was failing due to different name,
to fix it change voltage corener label name from lowsvs_d1 to lowsvsd1.

CRs-Fixed: 3696784
Change-Id: I5cb10f97292f09dea0fc0683fa60315c0cb5097d
Signed-off-by: Soumen Ghosh <quic_soumeng@quicinc.com>
2024-01-04 13:29:25 -08:00
Haochen Yang
124d3ea763 ARM: dts: msm: Fix ipe source clk rate for sun
This change fixes ipe0 src clk rate and adds lowsvs_d1 level
that is newly introduced.

CRs-Fixed: 3677567
Change-Id: I8fe98582faec4ba17b192d467e522beb700ea93d
Signed-off-by: Haochen Yang <quic_haocyang@quicinc.com>
2023-12-20 10:04:42 -08:00
Suraj Dongre
7c53ee0421 ARM: dts: msm: Fix jpeg dma reset for sun
Corrected register base start for jpeg dma on sun.
This impacts jpeg dma reset.

CRs-Fixed: 3648309
Change-Id: I43cbadac319f208cfb1f10158eb9d27e9c6eb734
Signed-off-by: Suraj Dongre <quic_sdongre@quicinc.com>
Signed-off-by: Mukund Madhusudan Atre <quic_matre@quicinc.com>
2023-12-06 17:19:14 -08:00
Mukund Madhusudan Atre
600c92672a ARM: dts: msm: Fix axi constituent paths for ofe in sun dtsi
Add missing paths in ofe camera bus nodes for axi bw voting.
Fix incorrect path in ofe read node.

CRs-Fixed: 3648309
Change-Id: I3e528c34e51102dc71f4b801aa7a9c4458a44f9e
Signed-off-by: Mukund Madhusudan Atre <quic_matre@quicinc.com>
2023-12-04 17:42:20 -08:00
Lokesh Kumar Aakulu
85cc560988 ARM: dts: msm: Correct MCLK on sun
Master Clock handle needs to updated
with bist handle and update correct
vreg for csiphy.

CRs-Fixed: 3656092
Change-Id: Ib2e8bb69ded52a07d0b9ef9ad9b25f892b1f2fbe
Signed-off-by: Lokesh Kumar Aakulu <quic_lkumar@quicinc.com>
2023-11-29 11:46:59 -08:00
Lokesh Kumar Aakulu
b2fa77def5 ARM: dts: msm: Add cam sensor devicetree for sun
Add device tree changes to  support for sensor,
eeprom, OIS & actuator for sun camera sensor.

CRs-Fixed: 3656092
Change-Id: I97d5c4976f531b6cba48211feb676eae424e75e2
Signed-off-by: Lokesh Kumar Aakulu <quic_lkumar@quicinc.com>
2023-11-20 17:41:33 -08:00
Mukund Madhusudan Atre
d2536ff522 ARM: dts: msm: Add interconnect path names for sun
Add interconnect path names separately in camera bus nodes,
so that they can be matched to interconnects in top level
cpas node. This is done to ensure compatibility with of_icc_get
during creation of path handles for ahb and axi voting.

CRs-Fixed: 3656156
Change-Id: Ia8ed566eadab413c38755af82d70a50196ae5f06
Signed-off-by: Mukund Madhusudan Atre <quic_matre@quicinc.com>
2023-11-09 14:50:13 -08:00
Soumen Ghosh
28ba146d6b ARM: dts: msm: Add devicetree changes for Sun dtsi
Update camera devicetree for changes in memory,
regulators, interrupts, clocks for CCI, CSIPHY,
CPAS, CDM, TPG, VFE, CSID, IPE, BPS, JPEG,
VFE-lite and CSID-lite nodes.

CRs-Fixed: 3648309
Change-Id: Ice6673d49cbd3958169c03863c34d40bf08317ee
Signed-off-by: Soumen Ghosh <quic_soumeng@quicinc.com>
2023-11-09 14:50:11 -08:00