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ARM: dts: msm: Correct MCLK on sun

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Master Clock handle needs to updated
with bist handle and update correct
vreg for csiphy.

CRs-Fixed: 3656092
Change-Id: Ib2e8bb69ded52a07d0b9ef9ad9b25f892b1f2fbe
Signed-off-by: Lokesh Kumar Aakulu <quic_lkumar@quicinc.com>
This commit is contained in:
Lokesh Kumar Aakulu
2023-11-29 11:46:59 -08:00
committed by Camera Software Integration
parent ea69728e84
commit 85cc560988
5 changed files with 93 additions and 93 deletions
Download Patch File Download Diff File Expand all files Collapse all files

32
sun-camera-sensor-cdp.dtsi
View File

@@ -123,7 +123,7 @@
gpio-req-tbl-label = "CAMIF_MCLK0",
"CAM_RESET0";
cci-master = <CCI_MASTER_0>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -159,7 +159,7 @@
gpio-req-tbl-label = "CAMIF_MCLK0",
"CAM_RESET0";
cci-master = <CCI_MASTER_0>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -195,7 +195,7 @@
gpio-req-tbl-label = "CAMIF_MCLK1",
"CAM_RESET1";
cci-master = <CCI_MASTER_1>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK1_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK1_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -236,7 +236,7 @@
gpio-req-tbl-label = "CAMIF_MCLK0",
"CAM_RESET0";
cci-master = <CCI_MASTER_0>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -280,7 +280,7 @@
gpio-req-tbl-label = "CAMIF_MCLK1",
"CAM_RESET1";
cci-master = <CCI_MASTER_1>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK1_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK1_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -323,7 +323,7 @@
gpio-req-tbl-label = "CAMIF_MCLK0",
"CAM_RESET0";
cci-master = <CCI_MASTER_0>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -374,7 +374,7 @@
gpio-req-tbl-label = "CAMIF_MCLK3",
"CAM_RESET3";
cci-master = <CCI_MASTER_0>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK3_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK3_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -416,7 +416,7 @@
gpio-req-tbl-label = "CAMIF_MCLK3",
"CAM_RESET3";
cci-master = <CCI_MASTER_0>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK3_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK3_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -455,7 +455,7 @@
gpio-req-tbl-label = "CAMIF_MCLK5",
"CAM_RESET5";
cci-master = <CCI_MASTER_1>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK5_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK5_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -496,7 +496,7 @@
gpio-req-tbl-label = "CAMIF_MCLK5",
"CAM_RESET5";
cci-master = <CCI_MASTER_1>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK5_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK5_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -537,7 +537,7 @@
gpio-req-tbl-flags = <1 0>;
gpio-req-tbl-label = "CAMIF_MCLK4",
"CAM_RESET4";
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK4_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK4_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -576,7 +576,7 @@
gpio-req-tbl-flags = <1 0>;
gpio-req-tbl-label = "CAMIF_MCLK4",
"CAM_RESET4";
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK4_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK4_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -634,7 +634,7 @@
gpio-req-tbl-flags = <1 0>;
gpio-req-tbl-label = "CAMIF_MCLK2",
"CAM_RESET2";
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -669,7 +669,7 @@
gpio-req-tbl-flags = <1 0>;
gpio-req-tbl-label = "CAMIF_MCLK2",
"CAM_RESET2";
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -718,7 +718,7 @@
gpio-req-tbl-label = "CAMIF_MCLK2",
"CAM_RESET2",
"CAM_I3CSELECT";
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -767,7 +767,7 @@
gpio-req-tbl-label = "CAMIF_MCLK2",
"CAM_RESET2",
"CAM_STANDBY";
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;

32
sun-camera-sensor-mtp.dtsi
View File

@@ -123,7 +123,7 @@
gpio-req-tbl-label = "CAMIF_MCLK0",
"CAM_RESET0";
cci-master = <CCI_MASTER_0>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -159,7 +159,7 @@
gpio-req-tbl-label = "CAMIF_MCLK0",
"CAM_RESET0";
cci-master = <CCI_MASTER_0>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -195,7 +195,7 @@
gpio-req-tbl-label = "CAMIF_MCLK1",
"CAM_RESET1";
cci-master = <CCI_MASTER_1>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK1_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK1_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -236,7 +236,7 @@
gpio-req-tbl-label = "CAMIF_MCLK0",
"CAM_RESET0";
cci-master = <CCI_MASTER_0>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -280,7 +280,7 @@
gpio-req-tbl-label = "CAMIF_MCLK1",
"CAM_RESET1";
cci-master = <CCI_MASTER_1>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK1_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK1_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -323,7 +323,7 @@
gpio-req-tbl-label = "CAMIF_MCLK0",
"CAM_RESET0";
cci-master = <CCI_MASTER_0>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -374,7 +374,7 @@
gpio-req-tbl-label = "CAMIF_MCLK3",
"CAM_RESET3";
cci-master = <CCI_MASTER_0>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK3_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK3_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -416,7 +416,7 @@
gpio-req-tbl-label = "CAMIF_MCLK3",
"CAM_RESET3";
cci-master = <CCI_MASTER_0>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK3_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK3_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -455,7 +455,7 @@
gpio-req-tbl-label = "CAMIF_MCLK5",
"CAM_RESET5";
cci-master = <CCI_MASTER_1>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK5_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK5_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -496,7 +496,7 @@
gpio-req-tbl-label = "CAMIF_MCLK5",
"CAM_RESET5";
cci-master = <CCI_MASTER_1>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK5_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK5_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -537,7 +537,7 @@
gpio-req-tbl-flags = <1 0>;
gpio-req-tbl-label = "CAMIF_MCLK4",
"CAM_RESET4";
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK4_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK4_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -576,7 +576,7 @@
gpio-req-tbl-flags = <1 0>;
gpio-req-tbl-label = "CAMIF_MCLK4",
"CAM_RESET4";
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK4_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK4_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -634,7 +634,7 @@
gpio-req-tbl-flags = <1 0>;
gpio-req-tbl-label = "CAMIF_MCLK2",
"CAM_RESET2";
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -669,7 +669,7 @@
gpio-req-tbl-flags = <1 0>;
gpio-req-tbl-label = "CAMIF_MCLK2",
"CAM_RESET2";
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -718,7 +718,7 @@
gpio-req-tbl-label = "CAMIF_MCLK2",
"CAM_RESET2",
"CAM_I3CSELECT";
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -767,7 +767,7 @@
gpio-req-tbl-label = "CAMIF_MCLK2",
"CAM_RESET2",
"CAM_STANDBY";
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;

32
sun-camera-sensor-qrd.dtsi
View File

@@ -123,7 +123,7 @@
gpio-req-tbl-label = "CAMIF_MCLK0",
"CAM_RESET0";
cci-master = <CCI_MASTER_0>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -159,7 +159,7 @@
gpio-req-tbl-label = "CAMIF_MCLK0",
"CAM_RESET0";
cci-master = <CCI_MASTER_0>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -195,7 +195,7 @@
gpio-req-tbl-label = "CAMIF_MCLK1",
"CAM_RESET1";
cci-master = <CCI_MASTER_1>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK1_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK1_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -236,7 +236,7 @@
gpio-req-tbl-label = "CAMIF_MCLK0",
"CAM_RESET0";
cci-master = <CCI_MASTER_0>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -280,7 +280,7 @@
gpio-req-tbl-label = "CAMIF_MCLK1",
"CAM_RESET1";
cci-master = <CCI_MASTER_1>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK1_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK1_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -323,7 +323,7 @@
gpio-req-tbl-label = "CAMIF_MCLK0",
"CAM_RESET0";
cci-master = <CCI_MASTER_0>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -374,7 +374,7 @@
gpio-req-tbl-label = "CAMIF_MCLK3",
"CAM_RESET3";
cci-master = <CCI_MASTER_0>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK3_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK3_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -416,7 +416,7 @@
gpio-req-tbl-label = "CAMIF_MCLK3",
"CAM_RESET3";
cci-master = <CCI_MASTER_0>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK3_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK3_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -455,7 +455,7 @@
gpio-req-tbl-label = "CAMIF_MCLK5",
"CAM_RESET5";
cci-master = <CCI_MASTER_1>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK5_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK5_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -496,7 +496,7 @@
gpio-req-tbl-label = "CAMIF_MCLK5",
"CAM_RESET5";
cci-master = <CCI_MASTER_1>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK5_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK5_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -537,7 +537,7 @@
gpio-req-tbl-flags = <1 0>;
gpio-req-tbl-label = "CAMIF_MCLK4",
"CAM_RESET4";
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK4_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK4_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -576,7 +576,7 @@
gpio-req-tbl-flags = <1 0>;
gpio-req-tbl-label = "CAMIF_MCLK4",
"CAM_RESET4";
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK4_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK4_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -634,7 +634,7 @@
gpio-req-tbl-flags = <1 0>;
gpio-req-tbl-label = "CAMIF_MCLK2",
"CAM_RESET2";
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -669,7 +669,7 @@
gpio-req-tbl-flags = <1 0>;
gpio-req-tbl-label = "CAMIF_MCLK2",
"CAM_RESET2";
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -718,7 +718,7 @@
gpio-req-tbl-label = "CAMIF_MCLK2",
"CAM_RESET2",
"CAM_I3CSELECT";
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -767,7 +767,7 @@
gpio-req-tbl-label = "CAMIF_MCLK2",
"CAM_RESET2",
"CAM_STANDBY";
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;

32
sun-camera-sensor-rumi.dtsi
View File

@@ -123,7 +123,7 @@
gpio-req-tbl-label = "CAMIF_MCLK0",
"CAM_RESET0";
cci-master = <CCI_MASTER_0>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -159,7 +159,7 @@
gpio-req-tbl-label = "CAMIF_MCLK0",
"CAM_RESET0";
cci-master = <CCI_MASTER_0>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -195,7 +195,7 @@
gpio-req-tbl-label = "CAMIF_MCLK1",
"CAM_RESET1";
cci-master = <CCI_MASTER_1>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK1_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK1_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -236,7 +236,7 @@
gpio-req-tbl-label = "CAMIF_MCLK0",
"CAM_RESET0";
cci-master = <CCI_MASTER_0>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -280,7 +280,7 @@
gpio-req-tbl-label = "CAMIF_MCLK1",
"CAM_RESET1";
cci-master = <CCI_MASTER_1>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK1_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK1_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -323,7 +323,7 @@
gpio-req-tbl-label = "CAMIF_MCLK0",
"CAM_RESET0";
cci-master = <CCI_MASTER_0>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK0_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -374,7 +374,7 @@
gpio-req-tbl-label = "CAMIF_MCLK3",
"CAM_RESET3";
cci-master = <CCI_MASTER_0>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK3_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK3_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -416,7 +416,7 @@
gpio-req-tbl-label = "CAMIF_MCLK3",
"CAM_RESET3";
cci-master = <CCI_MASTER_0>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK3_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK3_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -455,7 +455,7 @@
gpio-req-tbl-label = "CAMIF_MCLK5",
"CAM_RESET5";
cci-master = <CCI_MASTER_1>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK5_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK5_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -496,7 +496,7 @@
gpio-req-tbl-label = "CAMIF_MCLK5",
"CAM_RESET5";
cci-master = <CCI_MASTER_1>;
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK5_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK5_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -537,7 +537,7 @@
gpio-req-tbl-flags = <1 0>;
gpio-req-tbl-label = "CAMIF_MCLK4",
"CAM_RESET4";
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK4_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK4_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -576,7 +576,7 @@
gpio-req-tbl-flags = <1 0>;
gpio-req-tbl-label = "CAMIF_MCLK4",
"CAM_RESET4";
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK4_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK4_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -634,7 +634,7 @@
gpio-req-tbl-flags = <1 0>;
gpio-req-tbl-label = "CAMIF_MCLK2",
"CAM_RESET2";
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -669,7 +669,7 @@
gpio-req-tbl-flags = <1 0>;
gpio-req-tbl-label = "CAMIF_MCLK2",
"CAM_RESET2";
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -718,7 +718,7 @@
gpio-req-tbl-label = "CAMIF_MCLK2",
"CAM_RESET2",
"CAM_I3CSELECT";
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;
@@ -767,7 +767,7 @@
gpio-req-tbl-label = "CAMIF_MCLK2",
"CAM_RESET2",
"CAM_STANDBY";
clocks = <&camcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "nominal";
clock-rates = <24000000>;

58
sun-camera.dtsi
View File

@@ -881,12 +881,12 @@
interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>;
regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9";
gdscr-supply = <&cam_cc_titan_top_gdsc>;
csi-vdd-1p2-supply = <&L3I>;
csi-vdd-0p9-supply = <&L2I>;
csi-vdd-1p2-supply = <&L3G>;
csi-vdd-0p9-supply = <&L1F>;
rgltr-cntrl-support;
rgltr-min-voltage = <0 1200000 880000>;
rgltr-max-voltage = <0 1200000 912000>;
rgltr-load-current = <0 18000 32000>;
rgltr-max-voltage = <0 1256000 920000>;
rgltr-load-current = <0 6200 88200>;
shared-clks = <1 0 0 0>;
clock-names = "cphy_rx_clk_src",
"csiphy0_clk",
@@ -906,7 +906,7 @@
cam_csiphy1: qcom,csiphy1@adab000 {
cell-index = <1>;
compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy";
compatible = "qcom,csiphy-v2.3.0", "qcom,csiphy";
reg = <0xadab000 0x2000>;
reg-names = "csiphy";
reg-cam-base = <0xab000>;
@@ -914,12 +914,12 @@
interrupts = <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>;
regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9";
gdscr-supply = <&cam_cc_titan_top_gdsc>;
csi-vdd-1p2-supply = <&L3I>;
csi-vdd-0p9-supply = <&L2I>;
csi-vdd-1p2-supply = <&L3G>;
csi-vdd-0p9-supply = <&L1F>;
rgltr-cntrl-support;
rgltr-min-voltage = <0 1200000 880000>;
rgltr-max-voltage = <0 1200000 912000>;
rgltr-load-current = <0 18000 32200>;
rgltr-max-voltage = <0 1256000 920000>;
rgltr-load-current = <0 6200 88200>;
shared-clks = <1 0 0 0>;
clock-names = "cphy_rx_clk_src",
"csiphy1_clk",
@@ -939,7 +939,7 @@
cam_csiphy2: qcom,csiphy2@adad000 {
cell-index = <2>;
compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy";
compatible = "qcom,csiphy-v2.3.0", "qcom,csiphy";
reg = <0xadad000 0x2000>;
reg-names = "csiphy";
reg-cam-base = <0xad000>;
@@ -947,12 +947,12 @@
interrupts = <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>;
regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9";
gdscr-supply = <&cam_cc_titan_top_gdsc>;
csi-vdd-1p2-supply = <&L3I>;
csi-vdd-0p9-supply = <&L2I>;
csi-vdd-1p2-supply = <&L3G>;
csi-vdd-0p9-supply = <&L3I>;
rgltr-cntrl-support;
rgltr-min-voltage = <0 1200000 880000>;
rgltr-max-voltage = <0 1200000 912000>;
rgltr-load-current = <0 18000 32200>;
rgltr-max-voltage = <0 1256000 912000>;
rgltr-load-current = <0 6200 88200>;
shared-clks = <1 0 0 0>;
clock-names = "cphy_rx_clk_src",
"csiphy2_clk",
@@ -972,7 +972,7 @@
cam_csiphy3: qcom,csiphy3@adaf000 {
cell-index = <3>;
compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy";
compatible = "qcom,csiphy-v2.3.0", "qcom,csiphy";
reg = <0xadaf000 0x2000>;
reg-names = "csiphy";
reg-cam-base = <0xaf000>;
@@ -980,12 +980,12 @@
interrupts = <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>;
regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9";
gdscr-supply = <&cam_cc_titan_top_gdsc>;
csi-vdd-1p2-supply = <&L3I>;
csi-vdd-0p9-supply = <&L2I>;
csi-vdd-1p2-supply = <&L3G>;
csi-vdd-0p9-supply = <&L1F>;
rgltr-cntrl-support;
rgltr-min-voltage = <0 1200000 880000>;
rgltr-max-voltage = <0 1200000 912000>;
rgltr-load-current = <0 18000 32200>;
rgltr-max-voltage = <0 1256000 920000>;
rgltr-load-current = <0 6200 88200>;
shared-clks = <1 0 0 0>;
clock-names = "cphy_rx_clk_src",
"csiphy3_clk",
@@ -1005,7 +1005,7 @@
cam_csiphy4: qcom,csiphy4@adb1000 {
cell-index = <4>;
compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy";
compatible = "qcom,csiphy-v2.3.0", "qcom,csiphy";
reg = <0xadb1000 0x2000>;
reg-names = "csiphy";
reg-cam-base = <0xb1000>;
@@ -1013,12 +1013,12 @@
interrupts = <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>;
regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9";
gdscr-supply = <&cam_cc_titan_top_gdsc>;
csi-vdd-1p2-supply = <&L3I>;
csi-vdd-0p9-supply = <&L2I>;
csi-vdd-1p2-supply = <&L3G>;
csi-vdd-0p9-supply = <&L3I>;
rgltr-cntrl-support;
rgltr-min-voltage = <0 1200000 880000>;
rgltr-max-voltage = <0 1200000 912000>;
rgltr-load-current = <0 18600 37900>;
rgltr-max-voltage = <0 1256000 912000>;
rgltr-load-current = <0 6200 88200>;
shared-clks = <1 0 0 0>;
clock-names = "cphy_rx_clk_src",
"csiphy4_clk",
@@ -1038,7 +1038,7 @@
cam_csiphy5: qcom,csiphy5@adb3000 {
cell-index = <5>;
compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy";
compatible = "qcom,csiphy-v2.3.0", "qcom,csiphy";
reg = <0xadb3000 0x2000>;
reg-names = "csiphy";
reg-cam-base = <0xb3000>;
@@ -1046,12 +1046,12 @@
interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9";
gdscr-supply = <&cam_cc_titan_top_gdsc>;
csi-vdd-1p2-supply = <&L3I>;
csi-vdd-0p9-supply = <&L2I>;
csi-vdd-1p2-supply = <&L3G>;
csi-vdd-0p9-supply = <&L1F>;
rgltr-cntrl-support;
rgltr-min-voltage = <0 1200000 880000>;
rgltr-max-voltage = <0 1200000 912000>;
rgltr-load-current = <0 18000 32200>;
rgltr-max-voltage = <0 1256000 920000>;
rgltr-load-current = <0 6200 88200>;
shared-clks = <1 0 0 0>;
clock-names = "cphy_rx_clk_src",
"csiphy5_clk",