Commit Graph

2889 Commits

Author SHA1 Message Date
Brindha T
a52b4bbdb5 dt-bindings: soc: qcom: Add qcom,pmic-ecid bindings
Add bindings documentation for qcom,pmic-ecid. PMIC ECID provides the
PMIC specific information for identification.

Change-Id: I012670359ad1b1c4aea92f59b9430efc6e446f5f
Signed-off-by: Brindha T<quic_brint@quicinc.com>
2025-02-26 11:16:14 +05:30
QCTECMDR Service
e807503de3 Merge "ARM: dts: msm: enabling mem-object node for sdxkova" 2024-12-31 10:13:47 -08:00
QCTECMDR Service
36ac98b0c2 Merge "ARM: dts: msm: add changes for q2spi 4mA drive strength" 2024-12-31 10:13:47 -08:00
Priyansh Jain
3b62a4c338 ARM: dts: qcom: Add pmic die temp mitigation mapping for kera and tuna
Add pmic die temp mitigation mapping for kera and tuna.

Change-Id: I1ef3b8f4b775cd38b3c975ae47e4d90c640c30e1
Signed-off-by: Priyansh Jain <quic_priyjain@quicinc.com>
2024-12-31 01:58:31 -08:00
QCTECMDR Service
601e1716e8 Merge "ARM: dts: msm: enable QoS programming for KERA" 2024-12-30 12:30:34 -08:00
QCTECMDR Service
d34d450061 Merge "ARM: dts: msm: Correct FSA4480 I2C node" 2024-12-30 08:22:56 -08:00
kundan kumar
c7ac0d1333 ARM: dts: msm: enabling mem-object node for sdxkova
Enable mem-object node and heap buf.

Change-Id: I00dae06164ab2893a23ce3b54c9f4c0984c0d56c
Signed-off-by: kundan kumar <quic_kunkum@quicinc.com>
2024-12-30 20:38:35 +05:30
Yuhui Zhao
0a6ca3411e ARM: dts: msm: Correct FSA4480 I2C node
Correct FSA4480 I2C node.

Change-Id: I3e391d5f2984a9b17a60c670bfc6a5a3a20ca80d
Signed-off-by: Yuhui Zhao <quic_yuhuzhao@quicinc.com>
2024-12-30 03:32:39 -08:00
QCTECMDR Service
eddbabd9f6 Merge "ARM: dts: msm: tuna: Add USB_AXI clock for programming USB QoS" 2024-12-30 02:46:04 -08:00
QCTECMDR Service
84294ec126 Merge "ARM: dts: msm: Add pin configuration for USB3 PHY portselect on Kera" 2024-12-29 23:25:19 -08:00
QCTECMDR Service
ee5804c0c7 Merge "ARM: dts: msm: Add support for cpufreq_hw node on KERA" 2024-12-29 23:25:19 -08:00
Chandana Kishori Chiluveru
d88427773d ARM: dts: msm: add changes for q2spi 4mA drive strength
During Airplane mode testing with BT, UWB and PCIE concurrent
test scenarios, due to pcie traffic signal tolerance issue seen
on q2spi signals. As per the recommendation from design team
decreasing current drive strength from 6mA to 4mA for q2spi
active state GPIO configuration.

Change-Id: I530dfd636e834c4d6eb1e067e8dcb76dcfa4ab87
Signed-off-by: Chandana Kishori Chiluveru <quic_cchiluve@quicinc.com>
2024-12-29 21:45:38 -08:00
Anand Tarakh
02f2e181d1 ARM: dts: msm: enable touch support for Kera RCM platform
Enable touch support for Kera RCM platform.

Change-Id: Ib065708aaffd287f5ab12dd67cd3b2b7cda90c3f
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
2024-12-29 14:08:07 +05:30
Swetha Chintavatla
ddb6fa1714 ARM: dts: msm: enable QoS programming for KERA
Enable QoS programming for kera and add necessary AXI and
AHB clock handles for programming QoS for USB, IPA and PCIE masters.

Change-Id: I51bcc6a841005b6daf8ab3f22a79e6704dc3b3ed
Signed-off-by: Swetha Chintavatla <quic_chintava@quicinc.com>
2024-12-28 06:14:15 -08:00
QCTECMDR Service
8aff948cde Merge "ARM: dts: msm: Enable CDP SLT platform for Kera" 2024-12-28 03:16:11 -08:00
QCTECMDR Service
b8be33b11f Merge "ARM: dts: msm: Update the gcc and display clock controllers to tuna-v1" 2024-12-27 11:04:32 -08:00
Raviteja Laggyshetty
ab05b35d77 ARM: dts: msm: tuna: Add USB_AXI clock for programming USB QoS
Add USB AXI clock handle for accessing USB QoS register to program QoS.

Change-Id: I4e0a0057e55283578ab6333f0da1b46c36e01fe5
Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
2024-12-27 22:13:53 +05:30
Wasim Nazir
cf4a2ab06a ARM: dts: msm: Add supply for remoteproc instances
Add supply for adsp/cdsp/modem instances.

Change-Id: I07d21eea5db9074c6fe952466ce2d9af88c3b4d7
Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
2024-12-27 12:49:47 +05:30
Wasim Nazir
74c8fb319c ARM: dts: msm: Enable CDP SLT platform for Kera
Provide separate file for SLT so that ABL can pick
it properly. Currently, ABL doesn't check if multiple
board-id is added.

Change-Id: I9140ca7b19f6b0b368798950145abbe28e32e778
Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
2024-12-27 12:40:55 +05:30
QCTECMDR Service
d7faae4839 Merge "ARM: dts: msm: Add glink probe entry for Tuna" 2024-12-26 11:45:41 -08:00
QCTECMDR Service
4ed9bd9ae9 Merge "ARM: dts: msm: correct apss-tpda's element size" 2024-12-26 02:34:54 -08:00
QCTECMDR Service
2f83bab864 Merge "ARM: dts: msm: correct dl4-tpda's element size" 2024-12-26 02:34:53 -08:00
QCTECMDR Service
fa4317ec22 Merge "ARM: dts: msm: Add High Speed USB support on Kera" 2024-12-25 21:34:18 -08:00
QCTECMDR Service
5a433ab897 Merge "ARM: dts: qcom: Add cooling cell property for gpu node for kera" 2024-12-25 15:44:30 -08:00
Ajit Pandey
6c751c7e73 ARM: dts: msm: Add support for cpufreq_hw node on KERA
Add support for cpufreq_hw and cpufreq_hw_debug nodes on kera platform.
While at it, set the default governor to performance on kera platform.

Change-Id: Id6fd146d3c80f686780591e5efa594bd76155bcd
Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com>
2024-12-25 22:30:29 +05:30
Anaadi Mishra
7037f12c76 ARM: dts: msm: Move the pcie_1 clocks to protected-clocks
Mark the pcie_1 clocks as protected and remove the pcie_1 gdsc
nodes.

Change-Id: I3102a52895a6531fb82a411bdb760073fc3c28f3
Signed-off-by: Anaadi Mishra <quic_anaadim@quicinc.com>
2024-12-25 22:30:13 +05:30
Anaadi Mishra
f28b0bdded ARM: dts: msm: Update gpucc node as GenPD provider
Mark gpucc clock node as GenPD provider and disable the
graphics GDSC regulator nodes.
While at it, keep the gdsc's as it is on rumi platform.

Change-Id: I91b4915723e26685e950de3ae575540ac3940036
Signed-off-by: Anaadi Mishra <quic_anaadim@quicinc.com>
2024-12-25 22:30:04 +05:30
QCTECMDR Service
ba9d954ee2 Merge "ARM: dts: msm: Add power domain and interconnect for kgsl-smmu" 2024-12-25 02:41:16 -08:00
QCTECMDR Service
27bac66d5d Merge "ARM: dts: msm: Update dispcc clock node as GenPD provider on Kera" 2024-12-25 02:41:15 -08:00
Priyansh Jain
f9ccff95c8 ARM: dts: qcom: Add cooling cell property for gpu node for kera
Add cooling cell property for gpu node for kera.

Change-Id: Ic6c313f077c706817958c6941398c7c89aaa58cd
Signed-off-by: Priyansh Jain <quic_priyjain@quicinc.com>
2024-12-25 13:18:11 +05:30
Udipto Goswami
7bbc05c5d6 ARM: dts: msm: Add High Speed USB support on Kera
Currently, the node for eusb2_phy0 is defined but not used by controller
which makes the associated resources to be consumed. Therefore if phy
probes doesn't happen the controller goes into core soft reset failure.

Fix this by utilizing the node in the controller. This will call the
phy's probe and hence clocks & regulators will be initialized.

Change-Id: Ica46af01154d5e583e011e4f2d84a80fb0589ac8
Signed-off-by: Udipto Goswami <quic_ugoswami@quicinc.com>
2024-12-25 13:07:51 +05:30
QCTECMDR Service
a52ea8f04c Merge "ARM: dts: msm: enable tpdm-eva and funnel-eva for tuna" 2024-12-24 21:53:18 -08:00
songchai
a2853c528b ARM: dts: msm: correct dl4-tpda's element size
correct dl4-tpda's element size for tuna.

Change-Id: Id29c520789977f41d74f31ec8d29d5e946278503
Signed-off-by: songchai <quic_songchai@quicinc.com>
2024-12-24 17:43:29 -08:00
QCTECMDR Service
d2ebfa4670 Merge "ARM: dts: msm: Remove vm dma heaps dtsi for kera" 2024-12-24 17:04:49 -08:00
Vijayanand Jitta
0e53b492e5 ARM: dts: msm: Remove vm dma heaps dtsi for kera
The device tree for dma heaps on vm was incorrectly included.
so, remove it.

Fixes: 92398e011c ("ARM: dts: msm: Enable securemsm related nodes for kera")
Change-Id: Ib812725bedfd0510d6a998ecc83fe5df8619391c
Signed-off-by: Vijayanand Jitta <quic_vjitta@quicinc.com>
2024-12-24 18:29:46 +05:30
QCTECMDR Service
0c5c60b4fe Merge "ARM: dts: msm: Add pcie-pdc device for kera" 2024-12-24 03:03:42 -08:00
QCTECMDR Service
c8f55c5bd1 Merge "ARM: dts: msm: Fix for memory bootargs on kera" 2024-12-24 03:03:42 -08:00
QCTECMDR Service
f270a314e1 Merge "ARM: dts: msm: pcie: Set ultrashort channel settings TUNA PCIe" 2024-12-24 03:03:42 -08:00
Anaadi Mishra
fc794cac57 ARM: dts: msm: Update dispcc clock node as GenPD provider on Kera
Mark dispcc clock node as GenPD provider and disable the display GDSC
regulator nodes for kera platform.
While at it, keep the gdsc's as it is on kera-rumi platform and update
the compatible to align with freq plan.

Change-Id: If01f876b3d160cf5c1cfe6be13e3e4b42f62cfa6
Signed-off-by: Anaadi Mishra <quic_anaadim@quicinc.com>
2024-12-24 12:23:15 +05:30
Anaadi Mishra
f42efc56a8 dt-bindings: clock: qcom: add the DISPCC binding for kera
Add DISPCC clock binding for kera platform.

Change-Id: I3fd06bb26f5dd2b98653c0be22a2ff742de485ac
Signed-off-by: Anaadi Mishra <quic_anaadim@quicinc.com>
2024-12-24 12:23:15 +05:30
Anaadi Mishra
8d7f1a22a8 ARM: dts: msm: Update videocc clock node as GenPD provider on Kera
Mark videocc clock node as GenPD provider and disable the video GDSC
regulator nodes for kera platform.
While at it, keep the gdsc's as it is on kera-rumi platform.

Change-Id: I4a41aacbaa7d144f72db48b9af3a336a92ef95aa
Signed-off-by: Anaadi Mishra <quic_anaadim@quicinc.com>
2024-12-24 12:23:15 +05:30
Anaadi Mishra
0a06675a87 ARM: dts: msm: Add support for RPMHCC and DEBUGCC on Kera platform
Add support for rpmh and debug clock controller nodes on Kera platform.
While at it, keep rpmhcc node as dummy for KERA rumi platform.

Change-Id: Ic11513d45bbc9b3f172a411f854a2348af4bfb94
Signed-off-by: Anaadi Mishra <quic_anaadim@quicinc.com>
2024-12-24 12:23:12 +05:30
Anaadi Mishra
202e2bbd82 ARM: dts: msm: Add support for graphics clock controller on KERA
Add support for GPU clock controller and move corresponding
gdsc's from dummy to real on Kera platform.
While at it, add the clocks property to camera and display gdscs.

Change-Id: If3061a7603035e799e7548f0e2a93b7ded0e3005
Signed-off-by: Anaadi Mishra <quic_anaadim@quicinc.com>
2024-12-23 21:33:11 +05:30
Sneh Mankad
3c56793f10 ARM: dts: msm: Add pcie-pdc device for kera
Add PCIe device to wakeup SoC from PCIe clk request gpio.

Change-Id: I6d1e3f123ac1fc6de30fc7ece6def57e44961103
Signed-off-by: Sneh Mankad <quic_smankad@quicinc.com>
2024-12-21 08:16:11 -08:00
Uttkarsh Aggarwal
9f99f6782e ARM: dts: msm: Add pin configuration for USB3 PHY portselect on Kera
TLMM pin is used to notify USB3/DP Combo PHY about the
orientation. Select this pinctrl from the usb_qmp_dp_phy
and ensure it is selecting the "usb0_phy_ps" pin function for Kera.

Change-Id: Ib4c9b61a36473dc6a00cf7a271c54f2245d4f9d8
Signed-off-by: Uttkarsh Aggarwal <quic_uaggarwa@quicinc.com>
2024-12-20 14:12:52 +05:30
QCTECMDR Service
153577d637 Merge "ARM: dts: msm: add reserved mem for secure_etr" 2024-12-19 23:01:17 -08:00
QCTECMDR Service
5a53234366 Merge "bindings: soc: qcom: Document pcie-pdc compatible for kera" 2024-12-19 23:01:17 -08:00
QCTECMDR Service
937768c5ae Merge "ARM: dts: msm: correct tpdms'name for kera" 2024-12-19 23:01:17 -08:00
QCTECMDR Service
2463ab0d22 Merge "ARM: dts: qcom: Add support for Kera IoT platform" 2024-12-19 23:01:17 -08:00
QCTECMDR Service
6f06780153 Merge "ARM: dts: msm: correct apss-tpda's element size" 2024-12-19 23:01:17 -08:00