Lower the GPU bus range for 222Mhz powerlevel for Sun V2 devices.
Change-Id: I09b5cc3019751c8dfa67d1a8fd53f6d122404fdb
Signed-off-by: Carter Cooper <quic_ccooper@quicinc.com>
Update 607/660Mhz GPU max DDR limits for Sun V1 and V2.
Change-Id: I94e3047155c3c1ed1c078090f7ac165c10317099
Signed-off-by: Carter Cooper <quic_ccooper@quicinc.com>
Start the GPU at a slightly higher frequency than the lowest
available frequency on Sun V2 devices.
Change-Id: I212c07af5de4c665ba2ff836c97f2ba1381d8fb8
Signed-off-by: Carter Cooper <quic_ccooper@quicinc.com>
Add the AA SKU to the Sun v2 powerlevels so that it is recognized and
selects the appropriate powerlevel table.
Change-Id: I5bb706e3477efa390a8b40d24f85daabe111a0b8
Signed-off-by: Lynus Vaz <quic_lvaz@quicinc.com>
Add powerlevels on sun v2 GPUs based on the speed bin fuse on the device.
Change-Id: Ia0b35aabce36ab210ed01ea3c8abb90c05e74ac6
Signed-off-by: Lynus Vaz <quic_lvaz@quicinc.com>
Update ACD values with characterized values for Sun v2 GPU. Also disable
ACD on lower levels.
Change-Id: Ic5f0d7adb7a71be16f393ff90a6d0199179276a3
Signed-off-by: Mohammed Mirza Mandayappurath Manzoor <quic_mmandaya@quicinc.com>
Read the gpu speed bin devicetree property on sun devices.
Change-Id: I54c444bc434a2475ffe5126b7452f642f4dc7b2a
Signed-off-by: Lynus Vaz <quic_lvaz@quicinc.com>
All lower GPU frequencies are available and the lowest frequency
is no longer considered 'thermal only'. Remove the tag to allow
the lowest GPU frequency as a normal corner for Sun V2.
Change-Id: I3c2384a0d8d107393d71a3dbf8c22090304e64a7
Signed-off-by: Carter Cooper <quic_ccooper@quicinc.com>
Update the frequency tables for AB and AC SKUs.
Change-Id: I46b22a1ccf28db9bc40ea00483d17f4f97b6c6d4
Signed-off-by: Carter Cooper <quic_ccooper@quicinc.com>
Update bus votes for LOW_SVS_D1 corner to have the better power savings.
Change-Id: I91872df0dffd1be77d53f6b04bc1296163a1e5fa
Signed-off-by: Hareesh Gundu <quic_hareeshg@quicinc.com>
GDSCs were modeled as regulators till now. However,
moving forward, GDSCs will be treated as power domains.
Consequently, replace references to ‘regulators’ with
‘power domains’ for the sun GPU.
Change-Id: I607a511754d56728d5013004d0ae83544f873df6
Signed-off-by: Kamal Agrawal <quic_kamaagra@quicinc.com>
Add supported higher power level to Sun GPU.
Change-Id: Icfbdae6f7b44edea00fbf3374224cb407bd0968d
Signed-off-by: Mohammed Mirza Mandayappurath Manzoor <quic_mmandaya@quicinc.com>
Add supported lower power level to Sun GPU.
Change-Id: I896fe7cd45d1b1a824d3a0d7c47115952d8598ea
Signed-off-by: Mohammed Mirza Mandayappurath Manzoor <quic_mmandaya@quicinc.com>
Add supported higher power level to Sun GPU.
Change-Id: I6b33a69d09285f480bc24acfdd0df462ff25bcfb
Signed-off-by: Mohammed Mirza Mandayappurath Manzoor <quic_mmandaya@quicinc.com>
Add ACD values for supported voltage levels for Sun GPU.
Change-Id: I8361f4026afbf05ba26860307ffc7158b55b8d2f
Signed-off-by: Carter Cooper <quic_ccooper@quicinc.com>
Signed-off-by: Mohammed Mirza Mandayappurath Manzoor <quic_mmandaya@quicinc.com>
Add supporting power levels for AB and AC sku devices.
Change-Id: I233a5779a78cdc22883e1ed8b9b02c73aa0f576d
Signed-off-by: Mohammed Mirza Mandayappurath Manzoor <quic_mmandaya@quicinc.com>
SVS is the highest voltage corner for GMU. The lowest DDR BW
that puts CX at SVS corner is 1555 MHz. This DDR vote puts CX
at a corner high enough such that GMU can run at 650 MHz. This
is to get better GMU performance at no extra power cost.
Change-Id: I919476577e9b2e69161142c93d47e91505ffc222
Signed-off-by: Kamal Agrawal <quic_kamaagra@quicinc.com>
For gen8 targets, frequency limiter violations are published
through cx_host_irq interrupt. Thus, add cx_host_irq for sun
GPU.
Change-Id: Ie7e0c7fc53bdc002261ee05339c3e4c49da83ea0
Signed-off-by: Kamal Agrawal <quic_kamaagra@quicinc.com>
Hardware fence feature requires that we keep soccp from power collapsing
as long as GMU is active.
Change-Id: I3721aefd8cb34edfeba846115132002defa8f385
Signed-off-by: Harshdeep Dhatt <quic_hdhatt@quicinc.com>
This is needed to vote for soccp boot/slumber sequence for
hardware fence feature.
Change-Id: I169d83ed9d5acf66027194bf5fee0825bb5602d2
Signed-off-by: Harshdeep Dhatt <quic_hdhatt@quicinc.com>
Add device tree nodes for coresight CX and GX DBGC blocks
for sun devices. Also, add coresight funnel configuration
for graphics funnel device.
Change-Id: Id0a73ac9ef51e1039b718d5d51a4fc063d218a94
Signed-off-by: Kamal Agrawal <quic_kamaagra@quicinc.com>
KGSL driver doesn't program PDC registers anymore.
Thus, remove the register information from device
tree for sun GPU.
Change-Id: I60c78e00942bb68e311b4c4632e5a3e2ed30dcd6
Signed-off-by: Kamal Agrawal <quic_kamaagra@quicinc.com>
Add support for sunp variant msm-id.
Change-Id: I3dee70f03e360330636290ef665aced0b4f31542
Signed-off-by: Carter Cooper <quic_ccooper@quicinc.com>
Signed-off-by: Hareesh Gundu <quic_hareeshg@quicinc.com>
GDSCs can be modeled as power domain on newer GPUs. This
property provides an option to specify the GDSCs as power
domain.
Change-Id: I2f687b9339accaad701737ccfaf5e41209201229
Signed-off-by: Kamal Agrawal <quic_kamaagra@quicinc.com>
QDSS clock is used in kgsl to program ISDB registers. Add the clock so
that kgsl can vote for it when needed.
Change-Id: I2b71bdc4b9884409c598ba20759c56bff12cdb64
Signed-off-by: Mohammed Mirza Mandayappurath Manzoor <quic_mmandaya@quicinc.com>
Add intermediate supported power levels for GPU and remove unsupported
power levels from the list.
Change-Id: Ie16c06293dc707561f03aa9f1839a8217f163726
Signed-off-by: Mohammed Mirza Mandayappurath Manzoor <quic_mmandaya@quicinc.com>
Enable Sun GPU to perform graphics functionality.
Also add ipc-core property for hwfences support.
Change-Id: Ia01d92e4b2d43a1f8ec24ff63768aab5d7a4e1e3
Signed-off-by: Hareesh Gundu <quic_hareeshg@quicinc.com>
Add the devicetree files for the GPU on Sun devices.
Change-Id: Iaf7a19eb5e2c6c215e838ae1bfa3b01916c804d9
Signed-off-by: Hareesh Gundu <quic_hareeshg@quicinc.com>
