ARM: dts: msm: Add support for Sun GPU
Add the devicetree files for the GPU on Sun devices. Change-Id: Iaf7a19eb5e2c6c215e838ae1bfa3b01916c804d9 Signed-off-by: Hareesh Gundu <quic_hareeshg@quicinc.com>
This commit is contained in:
Hareesh Gundu
4
Kbuild
4
Kbuild
@@ -3,6 +3,10 @@ dtbo-y += gpu/pineapple-gpu.dtbo \
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gpu/pineapple-v2-gpu.dtbo
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endif
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ifeq ($(CONFIG_ARCH_SUN), y)
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dtbo-y += gpu/sun-gpu.dtbo
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endif
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always-y := $(dtb-y) $(dtbo-y)
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subdir-y := $(dts-dirs)
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clean-files := *.dtb *.dtbo
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132
gpu/sun-gpu-pwrlevels.dtsi
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132
gpu/sun-gpu-pwrlevels.dtsi
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@@ -0,0 +1,132 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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&msm_gpu {
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/* Power levels */
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qcom,gpu-pwrlevel-bins {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-pwrlevels-bins";
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qcom,gpu-pwrlevels-0 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,initial-pwrlevel = <9>;
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qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_UNKNOWN)>;
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/* TURBO_L1 */
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <967000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
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qcom,bus-freq = <10>;
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qcom,bus-min = <10>;
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qcom,bus-max = <11>;
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};
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/* TURBO */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <930000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
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qcom,bus-freq = <10>;
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qcom,bus-min = <10>;
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qcom,bus-max = <11>;
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};
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/* NOM_L1 */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <900000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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qcom,bus-freq = <10>;
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qcom,bus-min = <7>;
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qcom,bus-max = <10>;
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};
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/* NOM */
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <832000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
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qcom,bus-freq = <10>;
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qcom,bus-min = <7>;
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qcom,bus-max = <10>;
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};
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/* SVS_L2 */
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <779000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <7>;
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qcom,bus-max = <10>;
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};
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/* SVS_L1 */
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <734000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <6>;
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qcom,bus-max = <10>;
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};
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/* SVS */
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <607000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
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qcom,bus-freq = <6>;
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qcom,bus-min = <4>;
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qcom,bus-max = <7>;
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};
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/* Low_SVS */
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qcom,gpu-pwrlevel@7 {
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reg = <7>;
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qcom,gpu-freq = <443000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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qcom,bus-freq = <4>;
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qcom,bus-min = <2>;
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qcom,bus-max = <6>;
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};
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/* Low_SVS_D1 */
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qcom,gpu-pwrlevel@8 {
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reg = <8>;
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qcom,gpu-freq = <342000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
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qcom,bus-freq = <3>;
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qcom,bus-min = <2>;
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qcom,bus-max = <6>;
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};
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/* Low_SVS_D2 */
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qcom,gpu-pwrlevel@9 {
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reg = <9>;
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qcom,gpu-freq = <222000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
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qcom,bus-freq = <3>;
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qcom,bus-min = <2>;
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qcom,bus-max = <3>;
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};
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};
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};
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};
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26
gpu/sun-gpu.dts
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26
gpu/sun-gpu.dts
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@@ -0,0 +1,26 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/clock/qcom,aop-qmp.h>
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#include <dt-bindings/clock/qcom,gcc-sun.h>
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#include <dt-bindings/clock/qcom,gpucc-sun.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/interconnect/qcom,sun.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "sun-gpu.dtsi"
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#include "sun-gpu-pwrlevels.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. sun";
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compatible = "qcom,sun";
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qcom,msm-id = <618 0x10000>;
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qcom,board-id = <0 0>;
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};
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177
gpu/sun-gpu.dtsi
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177
gpu/sun-gpu.dtsi
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@@ -0,0 +1,177 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
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/* External feature codes */
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#define FC_UNKNOWN 0x0
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/* Pcodes */
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#define PCODE_UNKNOWN 0
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#define SKU_CODE(pcode, featurecode) ((pcode << 16) + featurecode)
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&msm_gpu {
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compatible = "qcom,adreno-gpu-gen8-0-0", "qcom,kgsl-3d0";
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status = "disabled";
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reg = <0x3d00000 0x40000>, <0x3d50000 0x10000>,
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<0x3d61000 0x3000>, <0x3d9e000 0x2000>,
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<0x10900000 0x80000>, <0x10048000 0x8000>,
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<0x10b05000 0x1000>;
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reg-names = "kgsl_3d0_reg_memory", "rscc", "cx_dbgc", "cx_misc",
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"qdss_gfx", "qdss_etr", "qdss_tmc";
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interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "kgsl_3d0_irq";
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clocks = <&gcc GCC_GPU_GEMNOC_GFX_CLK>,
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<&gpucc GPU_CC_AHB_CLK>;
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clock-names = "gcc_gpu_memnoc_gfx",
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"gpu_cc_ahb";
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qcom,gpu-model = "Adreno830";
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qcom,chipid = <0x44050000>;
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qcom,min-access-length = <32>;
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qcom,ubwc-mode = <5>;
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qcom,gpu-qdss-stm = <0x37000000 0x40000>; /* base addr, size */
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qcom,tzone-names = "gpuss-0", "gpuss-1", "gpuss-2", "gpuss-3",
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"gpuss-4", "gpuss-5", "gpuss-6", "gpuss-7";
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interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
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interconnect-names = "gpu_icc_path";
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qcom,bus-table-cnoc =
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<0>, /* Off */
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<100>; /* On */
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qcom,bus-table-ddr =
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<MHZ_TO_KBPS(0, 4)>, /* index=0 */
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<MHZ_TO_KBPS(200, 4)>, /* LowSVS index=1 */
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<MHZ_TO_KBPS(547, 4)>, /* LowSVS index=2 */
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<MHZ_TO_KBPS(1353, 4)>, /* LowSVS index=3 */
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<MHZ_TO_KBPS(1555, 4)>, /* SVS index=4 */
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<MHZ_TO_KBPS(1708, 4)>, /* SVS index=5 */
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<MHZ_TO_KBPS(2092, 4)>, /* SVS index=6 */
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<MHZ_TO_KBPS(2736, 4)>, /* NOM index=7 */
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<MHZ_TO_KBPS(3187, 4)>, /* NOM index=8 */
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<MHZ_TO_KBPS(3686, 4)>, /* TURBO index=9 */
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<MHZ_TO_KBPS(4224, 4)>, /* TURBO_L1 index=10 */
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<MHZ_TO_KBPS(4761, 4)>; /* TURBO_L3 index=11 */
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zap-shader {
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memory-region = <&gpu_microcode_mem>;
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};
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qcom,gpu-mempools {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-mempools";
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/* 4K Page Pool configuration */
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qcom,gpu-mempool@0 {
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reg = <0>;
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qcom,mempool-page-size = <4096>;
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qcom,mempool-reserved = <2048>;
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};
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/* 8K Page Pool configuration */
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qcom,gpu-mempool@1 {
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reg = <1>;
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qcom,mempool-page-size = <8192>;
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qcom,mempool-reserved = <1024>;
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};
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/* 64K Page Pool configuration */
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qcom,gpu-mempool@2 {
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reg = <2>;
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qcom,mempool-page-size = <65536>;
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qcom,mempool-reserved = <256>;
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};
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/* 128K Page Pool configuration */
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qcom,gpu-mempool@3 {
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reg = <3>;
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qcom,mempool-page-size = <131072>;
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qcom,mempool-reserved = <128>;
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};
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/* 256K Page Pool configuration */
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qcom,gpu-mempool@4 {
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reg = <4>;
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qcom,mempool-page-size = <262144>;
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qcom,mempool-reserved = <80>;
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};
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/* 1M Page Pool configuration */
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qcom,gpu-mempool@5 {
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reg = <5>;
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qcom,mempool-page-size = <1048576>;
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qcom,mempool-reserved = <32>;
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};
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};
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};
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&soc {
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kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 {
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compatible = "qcom,kgsl-smmu-v2";
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reg = <0x3da0000 0x40000>;
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vddcx-supply = <&gpu_cc_cx_gdsc>;
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gfx3d_user: gfx3d_user {
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compatible = "qcom,smmu-kgsl-cb";
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iommus = <&kgsl_smmu 0x0 0x000>;
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qcom,iommu-dma = "disabled";
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};
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gfx3d_lpac: gfx3d_lpac {
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compatible = "qcom,smmu-kgsl-cb";
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iommus = <&kgsl_smmu 0x1 0x000>;
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qcom,iommu-dma = "disabled";
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};
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gfx3d_secure: gfx3d_secure {
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compatible = "qcom,smmu-kgsl-cb";
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iommus = <&kgsl_smmu 0x2 0x000>;
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qcom,iommu-dma = "disabled";
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};
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};
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gmu: qcom,gmu@3d37000 {
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compatible = "qcom,gen8-gmu";
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reg = <0x3d37000 0x68000>,
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<0xb5d0000 0x24000>,
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<0x3d40000 0x10000>;
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reg-names = "gmu", "gmu_pdc", "gmu_ao_blk_dec0";
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interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,
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<0 305 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hfi", "gmu";
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regulator-names = "vddcx", "vdd";
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vddcx-supply = <&gpu_cc_cx_gdsc>;
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vdd-supply = <&gx_clkctl_gx_gdsc>;
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clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
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<&gpucc GPU_CC_CXO_CLK>,
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<&gcc GCC_DDRSS_GPU_AXI_CLK>,
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<&gcc GCC_GPU_GEMNOC_GFX_CLK>,
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<&gpucc GPU_CC_AHB_CLK>,
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<&gpucc GPU_CC_HUB_CX_INT_CLK>;
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clock-names = "gmu_clk", "cxo_clk", "axi_clk",
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"memnoc_clk", "ahb_clk", "hub_clk";
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qcom,gmu-freq-table = <500000000 RPMH_REGULATOR_LEVEL_LOW_SVS>,
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<650000000 RPMH_REGULATOR_LEVEL_SVS>;
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qcom,gmu-perf-ddr-bw = <MHZ_TO_KBPS(1353, 4)>;
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iommus = <&kgsl_smmu 0x5 0x000>;
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qcom,iommu-dma = "disabled";
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};
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};
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