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ARM: dts: msm: Add turbo_l3 power level to Sun GPU

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Add supported higher power level to Sun GPU.

Change-Id: I6b33a69d09285f480bc24acfdd0df462ff25bcfb
Signed-off-by: Mohammed Mirza Mandayappurath Manzoor <quic_mmandaya@quicinc.com>
This commit is contained in:
Mohammed Mirza Mandayappurath Manzoor
2024-03-05 10:18:50 -08:00
parent b884d6ef26
commit 300aef810b
1 changed files with 38 additions and 24 deletions
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62
gpu/sun-gpu-pwrlevels.dtsi
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@@ -4,6 +4,7 @@
*/
/* ACD Control register values */
#define ACD_LEVEL_TURBO_L3 0xa02f5ffd
#define ACD_LEVEL_TURBO_L1 0xa8285ffd
#define ACD_LEVEL_NOM_L1 0x88295ffd
#define ACD_LEVEL_NOM 0x88295ffd
@@ -181,12 +182,25 @@
#address-cells = <1>;
#size-cells = <0>;
qcom,initial-pwrlevel = <11>;
qcom,initial-pwrlevel = <12>;
qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_UNKNOWN)>;
/* TURBO_L1 */
/* TURBO_L3 */
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <1050000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
qcom,bus-freq = <11>;
qcom,bus-min = <11>;
qcom,bus-max = <11>;
qcom,acd-level = <ACD_LEVEL_TURBO_L3>;
};
/* TURBO_L1 */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <967000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
@@ -198,8 +212,8 @@
};
/* NOM_L1 */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <900000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
@@ -211,8 +225,8 @@
};
/* NOM */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <832000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
@@ -224,8 +238,8 @@
};
/* SVS_L2 */
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <779000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
@@ -237,8 +251,8 @@
};
/* SVS_L1 */
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <734000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
@@ -250,8 +264,8 @@
};
/* SVS_L0 */
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <660000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
@@ -263,8 +277,8 @@
};
/* SVS */
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-freq = <607000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
@@ -276,8 +290,8 @@
};
/* Low_SVS_L1 */
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-pwrlevel@8 {
reg = <8>;
qcom,gpu-freq = <525000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
@@ -289,8 +303,8 @@
};
/* Low_SVS */
qcom,gpu-pwrlevel@8 {
reg = <8>;
qcom,gpu-pwrlevel@9 {
reg = <9>;
qcom,gpu-freq = <443000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
@@ -302,8 +316,8 @@
};
/* Low_SVS_D0 */
qcom,gpu-pwrlevel@9 {
reg = <9>;
qcom,gpu-pwrlevel@10 {
reg = <10>;
qcom,gpu-freq = <389000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
@@ -315,8 +329,8 @@
};
/* Low_SVS_D1 */
qcom,gpu-pwrlevel@10 {
reg = <10>;
qcom,gpu-pwrlevel@11 {
reg = <11>;
qcom,gpu-freq = <342000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
@@ -328,8 +342,8 @@
};
/* Low_SVS_D2 */
qcom,gpu-pwrlevel@11 {
reg = <11>;
qcom,gpu-pwrlevel@12 {
reg = <12>;
qcom,gpu-freq = <222000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;