Add the TLMM GPIO reserved ranges for the sdxkova platform.
The reserved range is set to <110 6> to ensure proper
allocation and avoid conflicts with other GPIOs.
Change-Id: I6b01f9c6a21f918df078dcbe078be602dd889898
Signed-off-by: Khaja Hussain Shaik Khaji <quic_kshaikkh@quicinc.com>
Newly added optional quirk "qcom,sleep-clk-bcr" adds delay of
200-250us after deasserting the USB3 BCR. This is needed on
some targets where sleep clk is used for BCR demet.
Change-Id: I88370838c29f679f2d2d90f565d3884d48bcdff2
Signed-off-by: Prashanth K <quic_prashk@quicinc.com>
Set RX settings mode to zero for Ultrashort channel
settings for sun PCIe controller.
Change-Id: I50b7896e6dabb2cda069c9242340dee02a225b8c
Signed-off-by: Vivek Pernamitta <quic_vpernami@quicinc.com>
Add idle states for CPUs and CPU clusters, added PSCI device,
to enable CPUs to enter deeper LPMs.
Disabled the idle states till Rumi validations are done.
Additionally. updated APPS RSC device to be in cluster power domain
to handle RSC activities when cluster is powering off.
Change-Id: I0dc50ff04bb480eb9ebdfa0bbaebfdf954c7c41b
Signed-off-by: Sneh Mankad <quic_smankad@quicinc.com>
The tui_test heap will be used by the large_dmabuf test
on sun-vm.
Change-Id: I84e5aee85c03e2cc809acc307509ce00aa74d967
Signed-off-by: Georgi Djakov <quic_c_gdjako@quicinc.com>
When all clients remove DDR bandwidth vote, DDR may power collapse.
As part of its shutdown sequence, it waits for an 'active' signal to
no longer be asserted by the gpu cx gdsc. Thus, if SW votes for the
gdsc to be active, but not for DDR bandwidth, this sequence may
get stuck.
Change-Id: I48d704f08cfe6d17159eb04d02f5ed123809f967
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
APPS needs to place proxy votes to ddr and cnoc when the SOCCP is in D0.
Change-Id: Idfa93910b51c6df033ea010480c1a8adeacd4af5
Signed-off-by: Gokul krishna Krishnakumar <quic_gokukris@quicinc.com>
SOCCP_SOCCP_SPARE_REG0 is used to check D0 status of SOCCP.
TCSR_SOCCP_SLEEP_STATUS is used to check D3 status of SOCCP.
Change-Id: Icee37cddb0b7ef303962cab0d9a8f37a211a05da
Signed-off-by: Gokul krishna Krishnakumar <quic_gokukris@quicinc.com>
Bindings file for WALT cycle counter driver is in incorrect location.
Move it to the correct location where all other bindings files are
present.
Change-Id: I9e8ef0a87ac6b311931535a82ccf3c784bcdc896
Signed-off-by: Sai Harshini Nimmala <quic_snimmala@quicinc.com>
Parrot need to follow non-relocatable absolute addresses for VM due to
firmware constraints. VM kernel load address is the start address of the
vm_mem_region and build system requires the load address of the kernel
to be 2MB aligned.
This patch adjusts the start address of the trust_ui_vm_mem region for
Parrot to align to 2MB. This also means reducing its size by 1MB.
Change-Id: I1816ec5f6ff18f55ecc4dec39958d442151f8cb0
Signed-off-by: Hrishabh Rajput <quic_hrishabh@quicinc.com>
Signed-off-by: Swetha Chikkaboraiah <quic_schikk@quicinc.com>
Binding document to support MPAM(Memory System Resource Partitioning
and Monitoring) MSC(Memory System Component) interface framework added
to support multiple MSC components. Currently SLC(System Level Cache)
MSC support integrated to MSC interface with API support to configure
SLC Capacity and monitors.
Change-Id: I866b0e8cd6106f86535baf004d25e81e406e3e12
Signed-off-by: Avinash Philip <quic_avinashp@quicinc.com>
Vendor prefix qcom was updated for scid-heuristics properties.
Change-Id: I16c9e2197e348eac51d300258e482876bc51302e
Signed-off-by: Avinash Philip <quic_avinashp@quicinc.com>
Add initial device tree support for parrot/ravelin vm target.
This is a snapshot of dtsi files as of KP.1.0
'commit <370d8eab7cc6> ("Merge "ARM: dts: qcom:
Disable cnss-kiwi SOL on anorak platform"")'.
Change-Id: Iaf69c882974f38b69d9edd671d675f14dfb9774d
Signed-off-by: Swetha Chikkaboraiah <quic_schikk@quicinc.com>
Add pmic-glink support and its clients like qti-battery-charger,
altmode, ucsi and pmic-glink-adc support for tuna.
Change-Id: Ib2dd7cee63e6697e744783aabf954b62814b7ad8
Signed-off-by: Kavya Nunna <quic_knunna@quicinc.com>
Add spmi-pmic-arb devices for the primary and secondary SPMI buses
found on tuna. The primary bus operates at 19.2 MHz and is used
for most of the PMICs. The secondary bus operates at 4.8 MHz
and is used exclusively for charging PMICs. Note that the
secondary bus is not used so it is kept disabled.
Add SPMI debug device and associated child devices for the primary
SPMI interface. This provides consumers with unrestricted access
to the PMIC registers on pre-production devices. This helps
make debugging easier.
Change-Id: I9efadb5082389a519f76f7b5db43f0bde84f2239
Signed-off-by: Kavya Nunna <quic_knunna@quicinc.com>
Currently, 4 glink intents are used by sensors channels
Not enough for handling large no. of transactions between aon
and hal. Increase the no. of glink intents such that more
no. of transactions can be supported between aon and hal.
Change-Id: I676021e1f3968639c542a921bd213942cb2c8e2a
Signed-off-by: Sachin Patil <quic_sachpati@quicinc.com>
