ARM: dts: msm: Add CPUIdle and PSCI related devices for tuna
Add idle states for CPUs and CPU clusters, added PSCI device, to enable CPUs to enter deeper LPMs. Disabled the idle states till Rumi validations are done. Additionally. updated APPS RSC device to be in cluster power domain to handle RSC activities when cluster is powering off. Change-Id: I0dc50ff04bb480eb9ebdfa0bbaebfdf954c7c41b Signed-off-by: Sneh Mankad <quic_smankad@quicinc.com>
This commit is contained in:
Sneh Mankad
committed by
Vishvanath Singh
Vishvanath Singh
parent
a4b731a3d6
commit
bfeba3fcee
@@ -130,3 +130,47 @@
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&qupv3_se7_2uart {
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qcom,rumi_platform;
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};
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&GOLD_OFF_CL0 {
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status = "disabled";
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};
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&GOLD_OFF_CL1 {
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status = "disabled";
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};
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&GOLD_OFF_CL2 {
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status = "disabled";
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};
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&GOLD_RAIL_OFF_CL0 {
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status = "disabled";
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};
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&GOLD_RAIL_OFF_CL1 {
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status = "disabled";
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};
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&GOLD_RAIL_OFF_CL2 {
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status = "disabled";
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};
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&GOLD_PLUS_OFF {
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status = "disabled";
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};
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&GOLD_PLUS_RAIL_OFF {
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status = "disabled";
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};
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&CLUSTER_PWR_DN {
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status = "disabled";
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};
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&CX_RET {
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status = "disabled";
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};
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&APSS_OFF {
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status = "disabled";
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};
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207
qcom/tuna.dtsi
207
qcom/tuna.dtsi
@@ -60,7 +60,10 @@
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x0>;
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enable-method = "spin-table"; /* TODO: Update to psci */
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enable-method = "psci";
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cpu-idle-states = <&GOLD_OFF_CL0 &GOLD_RAIL_OFF_CL0>;
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power-domains = <&CPU_PD0>;
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power-domain-names = "psci";
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cpu-release-addr = <0x0 0xE3940000>;
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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@@ -79,7 +82,10 @@
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x100>;
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enable-method = "spin-table"; /* TODO: Update to psci */
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enable-method = "psci";
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cpu-idle-states = <&GOLD_OFF_CL0 &GOLD_RAIL_OFF_CL0>;
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power-domains = <&CPU_PD1>;
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power-domain-names = "psci";
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cpu-release-addr = <0x0 0xE3940000>;
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next-level-cache = <&L2_1>;
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L2_1: l2-cache {
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@@ -94,7 +100,10 @@
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x200>;
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enable-method = "spin-table"; /* TODO: Update to psci */
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enable-method = "psci";
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cpu-idle-states = <&GOLD_OFF_CL1 &GOLD_RAIL_OFF_CL1>;
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power-domains = <&CPU_PD2>;
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power-domain-names = "psci";
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cpu-release-addr = <0x0 0xE3940000>;
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next-level-cache = <&L2_2>;
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L2_2: l2-cache {
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@@ -108,7 +117,10 @@
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x300>;
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enable-method = "spin-table"; /* TODO: Update to psci */
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enable-method = "psci";
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cpu-idle-states = <&GOLD_OFF_CL1 &GOLD_RAIL_OFF_CL1>;
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power-domains = <&CPU_PD3>;
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power-domain-names = "psci";
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cpu-release-addr = <0x0 0xE3940000>;
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next-level-cache = <&L2_3>;
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L2_3: l2-cache {
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@@ -122,7 +134,10 @@
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x400>;
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enable-method = "spin-table"; /* TODO: Update to psci */
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enable-method = "psci";
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cpu-idle-states = <&GOLD_OFF_CL1 &GOLD_RAIL_OFF_CL1>;
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power-domains = <&CPU_PD4>;
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power-domain-names = "psci";
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cpu-release-addr = <0x0 0xE3940000>;
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next-level-cache = <&L2_4>;
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L2_4: l2-cache {
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@@ -136,7 +151,10 @@
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x500>;
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enable-method = "spin-table"; /* TODO: Update to psci */
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enable-method = "psci";
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cpu-idle-states = <&GOLD_OFF_CL2 &GOLD_RAIL_OFF_CL2>;
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power-domains = <&CPU_PD5>;
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power-domain-names = "psci";
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cpu-release-addr = <0x0 0xE3940000>;
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next-level-cache = <&L2_5>;
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L2_5: l2-cache {
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@@ -150,7 +168,10 @@
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x600>;
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enable-method = "spin-table"; /* TODO: Update to psci */
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enable-method = "psci";
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cpu-idle-states = <&GOLD_OFF_CL2 &GOLD_RAIL_OFF_CL2>;
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power-domains = <&CPU_PD6>;
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power-domain-names = "psci";
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cpu-release-addr = <0x0 0xE3940000>;
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next-level-cache = <&L2_6>;
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L2_6: l2-cache {
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@@ -164,7 +185,10 @@
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x700>;
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enable-method = "spin-table"; /* TODO: Update to psci */
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enable-method = "psci";
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cpu-idle-states = <&GOLD_PLUS_OFF &GOLD_PLUS_RAIL_OFF>;
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power-domains = <&CPU_PD7>;
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power-domain-names = "psci";
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cpu-release-addr = <0x0 0xE3940000>;
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next-level-cache = <&L2_7>;
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L2_7: l2-cache {
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@@ -217,6 +241,117 @@
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};
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};
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idle-states {
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entry-method = "psci";
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GOLD_OFF_CL0: gold-cluster0-c3 { /* C3 */
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compatible = "arm,idle-state";
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idle-state-name = "pc";
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entry-latency-us = <400>;
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exit-latency-us = <1100>;
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min-residency-us = <4011>;
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arm,psci-suspend-param = <0x40000003>;
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local-timer-stop;
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};
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GOLD_RAIL_OFF_CL0: gold-cluster0-c4 { /* C4 */
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compatible = "arm,idle-state";
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idle-state-name = "rail-pc";
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entry-latency-us = <550>;
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exit-latency-us = <1050>;
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min-residency-us = <7951>;
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arm,psci-suspend-param = <0x40000004>;
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local-timer-stop;
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};
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GOLD_OFF_CL1: gold-cluster1-c3 { /* C3 */
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compatible = "arm,idle-state";
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idle-state-name = "pc";
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entry-latency-us = <400>;
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exit-latency-us = <1100>;
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min-residency-us = <4011>;
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arm,psci-suspend-param = <0x40000003>;
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local-timer-stop;
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};
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GOLD_RAIL_OFF_CL1: gold-cluster1-c4 { /* C4 */
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compatible = "arm,idle-state";
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idle-state-name = "rail-pc";
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entry-latency-us = <550>;
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exit-latency-us = <1050>;
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min-residency-us = <7951>;
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arm,psci-suspend-param = <0x40000004>;
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local-timer-stop;
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};
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GOLD_OFF_CL2: gold-cluster2-c3 { /* C3 */
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compatible = "arm,idle-state";
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idle-state-name = "pc";
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entry-latency-us = <400>;
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exit-latency-us = <1100>;
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min-residency-us = <4011>;
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arm,psci-suspend-param = <0x40000003>;
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local-timer-stop;
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};
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GOLD_RAIL_OFF_CL2: gold-cluster2-c4 { /* C4 */
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compatible = "arm,idle-state";
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idle-state-name = "rail-pc";
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entry-latency-us = <550>;
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exit-latency-us = <1050>;
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min-residency-us = <7951>;
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arm,psci-suspend-param = <0x40000004>;
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local-timer-stop;
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};
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GOLD_PLUS_OFF: gold-plus-c3 { /* C3 */
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compatible = "arm,idle-state";
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idle-state-name = "pc";
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entry-latency-us = <450>;
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exit-latency-us = <1200>;
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min-residency-us = <6230>;
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arm,psci-suspend-param = <0x40000003>;
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local-timer-stop;
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};
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GOLD_PLUS_RAIL_OFF: gold-plus-cluster3-c4 { /* C4 */
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compatible = "arm,idle-state";
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idle-state-name = "rail-pc";
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entry-latency-us = <500>;
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exit-latency-us = <1350>;
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min-residency-us = <7480>;
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arm,psci-suspend-param = <0x40000004>;
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local-timer-stop;
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};
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CLUSTER_PWR_DN: cluster-d4 { /* D4 */
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compatible = "domain-idle-state";
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idle-state-name = "l3-off";
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entry-latency-us = <750>;
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exit-latency-us = <2350>;
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min-residency-us = <9144>;
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arm,psci-suspend-param = <0x41000044>;
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};
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CX_RET: cx-ret { /* Cx Ret */
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compatible = "domain-idle-state";
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idle-state-name = "cx-ret";
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entry-latency-us = <1561>;
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exit-latency-us = <2801>;
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min-residency-us = <8550>;
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arm,psci-suspend-param = <0x41001344>;
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};
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APSS_OFF: cluster-e3 { /* E3 */
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compatible = "domain-idle-state";
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idle-state-name = "llcc-off";
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entry-latency-us = <2800>;
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exit-latency-us = <4400>;
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min-residency-us = <10150>;
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arm,psci-suspend-param = <0x4100b344>;
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};
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};
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soc: soc { };
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};
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@@ -246,6 +381,56 @@
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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CPU_PD0: cpu-pd0 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD1: cpu-pd1 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD2: cpu-pd2 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD3: cpu-pd3 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD4: cpu-pd4 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD5: cpu-pd5 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD6: cpu-pd6 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD7: cpu-pd7 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CLUSTER_PD: cluster-pd {
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#power-domain-cells = <0>;
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domain-idle-states = <&CLUSTER_PWR_DN &CX_RET &APSS_OFF>;
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};
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};
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intc: interrupt-controller@17100000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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@@ -336,6 +521,7 @@
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&CLUSTER_PD>;
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apps_rsc_drv2: drv@2 {
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qcom,drv-id = <2>;
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@@ -355,6 +541,11 @@
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};
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};
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cluster-device {
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compatible = "qcom,lpm-cluster-dev";
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power-domains = <&CLUSTER_PD>;
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};
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cam_rsc: rsc@adc8000 {
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label = "cam_rsc";
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compatible = "qcom,rpmh-rsc";
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