Add binding documentation for the SPMI debug bus found on SPMI
PMIC arbiter version 5 and above. This debug bus has read and
write access to all PMIC peripherals regardless of ownership
configurations. It cannot be used on production devices because
it is disabled by an eFuse.
This is a snapshot of the file qcom,spmi-pmic-arb-debug.txt
taken as of qcom-6.1 commit b522c3b6d065 ("dt-bindings: spmi:
spmi-pmic-arb-debug: define enable fuse property")
which was then converted to yaml.
Change-Id: I344ddea23ecb09bede5cbdb19197ab52b24dda44
Signed-off-by: David Collins <quic_collinsd@quicinc.com>
Add documentation for the qcom,can-sleep property. This is used
for slow SPMI busses which may sleep during transactions.
Change-Id: Ib07ffa28a0aa167571501e2493f5f03ad575755e
Signed-off-by: David Collins <quic_collinsd@quicinc.com>
Add documentatio for qdss component coresight-remote-etm. correct
the format of qcom,coresight-csr.yaml.
Change-Id: I024a7245997f51a02118d0abf8bd9932763772fb
Signed-off-by: Yuanfang Zhang <quic_yuanfang@quicinc.com>
Some GDSCs are enabled from bootloaders and need the proxy-consumer to
ensure they stay on until after their associated CC has probed and
enabled clocks that depend on them.
Change-Id: I6801742fb80d62b16153a0973696b82972a22806
Signed-off-by: Mike Tipton <quic_mdtipton@quicinc.com>
Enable cluster 0 cores from the command line instead of just
core 0.
Change-Id: I26b97122d353b3979467109babfded9a095b207d
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
With 16GB of DDR, existing drivers were trying to use 6Mb as follows:
2Mb: dma_atomic_pool_init(GFP_KERNEL)
2Mb: dma_atomic_pool_init(GFP_KERNEL | GFP_DMA32)
2Mb: qcom_iommu_util::dma_atomic_pool_init
Increase the reserved size to 12Mb to leave a small margin.
Change-Id: Id9bdfcca7560d40bddf3c9c526f9e3ee69ba9174
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
Add the device tree properties to the smem reserved memory region that
to match allows the smem driver to match and probe accordingly.
Change-Id: I4e0bdf3d26a9d0f7cf15a569e08988dddadf8183
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Signed-off-by: Chris Lew <quic_clew@quicinc.com>
Switch to enable SMMU for the USB controller on sun.
Change-Id: I9b43a167beb2ab971ce48bbc5f03bf62512addc2
Signed-off-by: Ronak Vijay Raheja <quic_rraheja@quicinc.com>
Add the psci node and change the cpu enable method to psci
on the sun SoC.
Change-Id: I86f747a87169172ac215885c6de0e19be921f99f
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Change the sun rumi dt file to compile as an overlay.
Change-Id: I56dcc5349eac12c660981da0fc75f0173b27197a
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Adjust arch timer and memtimer frequencies on the sun RUMI to stop
IRQ storms during boot.
Change-Id: Ic34a125763701ec115db82cd5ed5259fb3bd9a28
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Add tz-log node for Sun which gets updated by Resource Manager.
With out this node, device tree overlay fails.
Change-Id: I9d54da4cf32272176e12d3cd49bc21f20e688f30
Signed-off-by: Satya Durga Srinivasu Prabhala <quic_satyap@quicinc.com>
Add stdout to chosen node for sun SoC and set maxcpus to 1.
Change-Id: I2633e4f96f3f9cbc047334200fc42921a5f5d6f7
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Add interconnect device bindings for Pineapple SoC. These devices
can be used to describe any RPMH and NoC based interconnect devices.
Change-Id: I5475ae5c1d6457a71b670cd17ddc53ad71566ae8
Signed-off-by: Xubin Bai <quic_xubibai@quicinc.com>
Add documentation for qcom,ufs-phy-qrbtc-sdm845 rumi phy driver.
Change-Id: I3366aea0afbe5fec71ddc953f86ce125e42d93f8
Signed-off-by: Bao D. Nguyen <quic_nguyenb@quicinc.com>
