Merge "ARM: dts: msm: Add USB device nodes for sun"
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bindings/usb/qcom,usb-ssphy-qmp.yaml
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229
bindings/usb/qcom,usb-ssphy-qmp.yaml
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@@ -0,0 +1,229 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/usb/qcom,usb-ssphy-qmp.yaml##
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. SuperSpeed USB QMP PHY
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maintainers:
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- Ronak Vijay Raheja <quic_rraheja@quicinc.com>
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properties:
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compatible:
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items:
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- enum:
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- qcom,usb-ssphy-qmp
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- qcom,usb-ssphy-qmp-v1
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- qcom,usb-ssphy-qmp-v2
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- qcom,usb-ssphy-qmp-usb3-or-dp
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- qcom,usb-ssphy-qmp-dp-combo
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reg:
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description: |
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Address and length of the register set for the device. Required regs
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are::
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- qmp_phy_base:: QMP PHY Base register set
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Optional regs are::
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- tcsr_usb3_dp_phymode:: top-level CSR register to be written to
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select super speed usb qmp phy
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- pcs_clamp_enable_reg:: Clamps the phy data inputs and enables USB3
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autonomous mode.
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- vls_clamp_reg:: top-level CSR register to be written to enable phy
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vls clamp which allows phy to detect autonomous mode.
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reg-names:
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minItems: 1
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items:
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- const: qmp_phy_base # required
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- const: tcsr_usb3_dp_phymode
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- const: pcs_clamp_enable_reg
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- const: vls_clamp_reg
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vdd-supply:
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description: phandle to the Vdd supply for SSPHY digital circuit operation
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core-supply:
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description: phandle to the high-voltage analog supply for SSPHY
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usb3_dp_phy_gdsc-supply:
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description: |
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phandle to the GDSC regulator device tree node related to USB QMP DP PHY.
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clocks:
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minItems: 1
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items:
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- description: GCC_USB3_PRIM_PHY_AUX_CLK clk
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- description: GCC_USB3_PRIM_PHY_PIPE_CLK clk
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- description: GCC_USB3_PRIM_PHY_PIPE_CLK_SRC clk
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- description: usb3_phy_wrapper_gcc_usb30_pipe_clk clk
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- description: RPMH_CXO_PAD_CLK clk
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- description: TCSR_USB3_CLKREF_EN clk
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- description: GCC_USB3_PRIM_PHY_COM_AUX_CLK clk
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clock-names:
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minItems: 2
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items:
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- const: aux_clk # required
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- const: pipe_clk # required
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- const: pipe_clk_mux
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- const: pipe_clk_ext_src
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- const: ref_clk_src
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- const: ref_clk
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- const: com_aux_clk
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qcom,vdd-voltage-level:
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description: |
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This property must be a list of three integer values (no, min, max) where
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each value represents either a voltage in microvolts or a value
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corresponding to voltage corner.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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resets:
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description: |
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Reset specifier pair consists of phandle for the reset controller and
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reset lines used by this controller.
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reset-names:
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description: |
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reset signal name strings sorted in the same order as the resets
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property.
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qcom,qmp-phy-init-seq:
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description: |
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QMP PHY initialization sequence with reg offset, its value, delay after
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register write.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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qcom,qmp-phy-reg-offset:
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description: |
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Provides important phy register offsets in an order defined in the phy
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driver. Provide below mentioned register offsets in order for non USB DP
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combo PHY::
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- USB3_PHY_PCS_STATUS
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- USB3_PHY_AUTONOMOUS_MODE_CTRL
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- USB3_PHY_LFPS_RXTERM_IRQ_CLEAR
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- USB3_PHY_POWER_DOWN_CONTROL
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- USB3_PHY_SW_RESET
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- USB3_PHY_START
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In addion to above following set of registers offset needed for USB DP
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combo PHY in mentioned order::
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- USB3_DP_DP_PHY_PD_CTL
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- USB3_DP_COM_POWER_DOWN_CTRL
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- USB3_DP_COM_SW_RESET
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- USB3_DP_COM_RESET_OVRD_CTRL
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- USB3_DP_COM_PHY_MODE_CTRL
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- USB3_DP_COM_TYPEC_CTRL
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- USB3_DP_COM_SWI_CTRL
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Optional register for enabling/disabling VLS clamp if available::
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- USB3_PCS_MISC_CLAMP_ENABLE
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Optional register for configuring USB Type-C port select if available::
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- USB3_PHY_PCS_MISC_TYPEC_CTRL
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$ref: /schemas/types.yaml#/definitions/uint32-array
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qcom,vbus-valid-override:
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description: |
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If present, indicates VBUS pin is not connected to the USB PHY and the
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controller must rely on external VBUS notification in order to manually
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relay the notification to the SSPHY.
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qcom,vdd-max-load-uA:
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description: |
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If present, indicates the maximum current (in uA) the PHY is expected to
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draw from the vdd power supply.
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qcom,core-voltage-level:
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description: |
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This property must be a list of three integer values (no, min, max) where
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each value represents either a voltage in microvolts or a value
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corresponding to voltage corner.
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qcom,core-max-load-uA:
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description: |
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If present, indicates the maximum current (in uA) the PHY is expected to
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draw from the core power supply.
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qcom,link-training-reset:
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description: |
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This property indicates to start link training timer to reset the elastic
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buffer based on rx equalization value.
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extcon:
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description: |
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phandle to external connector devices which provide type-C based
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"USB-HOST" cable events. This phandle is used for notifying number of
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lanes used in case of USB+DP concurrent mode to driver.
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required:
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- compatible
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- reg
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- reg-names
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- vdd-supply
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- core-supply
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- clocks
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- clock-names
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- qcom,vdd-voltage-level
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- resets
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- reset-names
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- qcom,qmp-phy-init-seq
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- qcom,qmp-phy-reg-offset
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,gcc-sun.h>
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#include <dt-bindings/clock/qcom,tcsrcc-sun.h>
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#include <dt-bindings/phy/qcom,usb3-4nm-qmp-combo.h>
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usb_qmp_dp_phy: ssphy@88e8000 {
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compatible = "qcom,usb-ssphy-qmp-dp-combo";
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reg = <0x88e8000 0x3000>;
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reg-names = "qmp_phy_base";
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vdd-supply = <&pm_v6g_l3>;
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qcom,vdd-voltage-level = <0 912000 912000>;
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qcom,vdd-max-load-uA = <47000>;
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core-supply = <&pm_v8_l3>;
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usb3_dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>;
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clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
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<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
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<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>,
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<&usb3_phy_wrapper_gcc_usb30_pipe_clk>,
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<&rpmhcc RPMH_CXO_PAD_CLK>,
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<&tcsrcc TCSR_USB3_CLKREF_EN>,
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<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
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clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
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"pipe_clk_ext_src", "ref_clk_src",
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"ref_clk", "com_aux_clk";
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resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
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<&gcc GCC_USB3_PHY_PRIM_BCR>;
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reset-names = "global_phy_reset", "phy_reset";
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pinctrl-names = "default";
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pinctrl-0 = <&usb3phy_portselect_default>;
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qcom,qmp-phy-reg-offset =
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<USB3_DP_PCS_PCS_STATUS1
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USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL
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USB3_DP_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
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USB3_DP_PCS_POWER_DOWN_CONTROL
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USB3_DP_PCS_SW_RESET
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USB3_DP_PCS_START_CONTROL
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0xffff /* USB3_PHY_PCS_MISC_TYPEC_CTRL */
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USB3_DP_COM_POWER_DOWN_CTRL
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USB3_DP_COM_SW_RESET
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USB3_DP_COM_RESET_OVRD_CTRL
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USB3_DP_COM_PHY_MODE_CTRL
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USB3_DP_COM_TYPEC_CTRL
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USB3_DP_PCS_AON_CLAMP_ENABLE>;
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qcom,qmp-phy-init-seq =
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/* <reg_offset, value> */
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<USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xC0
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USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x01
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USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x02>;
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};
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...
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@@ -21,3 +21,31 @@
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&qupv3_se7_2uart {
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qcom,rumi_platform;
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};
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&soc {
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usb_nop_phy: usb_nop_phy {
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compatible = "usb-nop-xceiv";
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};
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usb_emuphy: phy@a784000 {
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compatible = "qcom,usb-emu-phy";
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reg = <0x0a784000 0x9500>;
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qcom,emu-init-seq = <0xfffff 0x4
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0xffff0 0x4
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0x100000 0x20
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0x0 0x20
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0x000101F0 0x20
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0x00100000 0x3c
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0x0 0x3c
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0x0 0x4>;
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};
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};
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&usb0 {
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dwc3@a600000 {
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usb-phy = <&usb_emuphy>, <&usb_nop_phy>;
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dr_mode = "peripheral";
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maximum-speed = "high-speed";
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};
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};
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59
qcom/sun-usb.dtsi
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59
qcom/sun-usb.dtsi
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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&soc {
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usb0: ssusb@a600000 {
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compatible = "qcom,dwc-usb3-msm";
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reg = <0xa600000 0x100000>;
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reg-names = "core_base";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
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<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_PRIM_SLEEP_CLK>;
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clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
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"utmi_clk", "sleep_clk";
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resets = <&gcc GCC_USB30_PRIM_BCR>;
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reset-names = "core_reset";
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interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pwr_event_irq";
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qcom,dis-sending-cm-l1-quirk;
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qcom,core-clk-rate = <200000000>;
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qcom,core-clk-rate-hs = <66666667>;
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qcom,core-clk-rate-disconnected = <133333333>;
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dwc3@a600000 {
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compatible = "snps,dwc3";
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reg = <0xa600000 0xd93c>;
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iommus = <&apps_smmu 0x40 0x0>;
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qcom,iommu-dma = "bypass";
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qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
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dma-coherent;
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interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
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snps,disable-clk-gating;
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snps,has-lpm-erratum;
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snps,hird-threshold = /bits/ 8 <0x0>;
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snps,is-utmi-l1-suspend;
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snps,dis-u1-entry-quirk;
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snps,dis-u2-entry-quirk;
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snps,dis_u2_susphy_quirk;
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snps,ssp-u3-u0-quirk;
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tx-fifo-resize;
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dr_mode = "otg";
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maximum-speed = "super-speed-plus";
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usb-role-switch;
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};
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};
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};
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@@ -968,6 +968,7 @@
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#include "sun-pinctrl.dtsi"
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#include "sun-regulators.dtsi"
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#include "sun-qupv3.dtsi"
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#include "sun-usb.dtsi"
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&qupv3_se7_2uart {
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status = "ok";
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