From 86f0caef7cf0c1866378fa34edbdea6719a1ac0b Mon Sep 17 00:00:00 2001 From: Ronak Vijay Raheja Date: Wed, 28 Jun 2023 18:24:46 -0700 Subject: [PATCH 1/2] dt-bindings: Add USB QMP SSPHY bindings Add SuperSpeed USB QMP PHY bindings used on MSM platforms. Change-Id: Iad3f4a10b6425d3814446f882b086ca7dba96d01 Signed-off-by: Ronak Vijay Raheja --- bindings/usb/qcom,usb-ssphy-qmp.yaml | 229 +++++++++++++++++++++++++++ 1 file changed, 229 insertions(+) create mode 100644 bindings/usb/qcom,usb-ssphy-qmp.yaml diff --git a/bindings/usb/qcom,usb-ssphy-qmp.yaml b/bindings/usb/qcom,usb-ssphy-qmp.yaml new file mode 100644 index 00000000..13465acc --- /dev/null +++ b/bindings/usb/qcom,usb-ssphy-qmp.yaml @@ -0,0 +1,229 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/qcom,usb-ssphy-qmp.yaml## +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SuperSpeed USB QMP PHY + +maintainers: + - Ronak Vijay Raheja + +properties: + compatible: + items: + - enum: + - qcom,usb-ssphy-qmp + - qcom,usb-ssphy-qmp-v1 + - qcom,usb-ssphy-qmp-v2 + - qcom,usb-ssphy-qmp-usb3-or-dp + - qcom,usb-ssphy-qmp-dp-combo + + reg: + description: | + Address and length of the register set for the device. Required regs + are:: + - qmp_phy_base:: QMP PHY Base register set + Optional regs are:: + - tcsr_usb3_dp_phymode:: top-level CSR register to be written to + select super speed usb qmp phy + - pcs_clamp_enable_reg:: Clamps the phy data inputs and enables USB3 + autonomous mode. + - vls_clamp_reg:: top-level CSR register to be written to enable phy + vls clamp which allows phy to detect autonomous mode. + + reg-names: + minItems: 1 + items: + - const: qmp_phy_base # required + - const: tcsr_usb3_dp_phymode + - const: pcs_clamp_enable_reg + - const: vls_clamp_reg + + vdd-supply: + description: phandle to the Vdd supply for SSPHY digital circuit operation + + core-supply: + description: phandle to the high-voltage analog supply for SSPHY + + usb3_dp_phy_gdsc-supply: + description: | + phandle to the GDSC regulator device tree node related to USB QMP DP PHY. + + clocks: + minItems: 1 + items: + - description: GCC_USB3_PRIM_PHY_AUX_CLK clk + - description: GCC_USB3_PRIM_PHY_PIPE_CLK clk + - description: GCC_USB3_PRIM_PHY_PIPE_CLK_SRC clk + - description: usb3_phy_wrapper_gcc_usb30_pipe_clk clk + - description: RPMH_CXO_PAD_CLK clk + - description: TCSR_USB3_CLKREF_EN clk + - description: GCC_USB3_PRIM_PHY_COM_AUX_CLK clk + + clock-names: + minItems: 2 + items: + - const: aux_clk # required + - const: pipe_clk # required + - const: pipe_clk_mux + - const: pipe_clk_ext_src + - const: ref_clk_src + - const: ref_clk + - const: com_aux_clk + + qcom,vdd-voltage-level: + description: | + This property must be a list of three integer values (no, min, max) where + each value represents either a voltage in microvolts or a value + corresponding to voltage corner. + $ref: /schemas/types.yaml#/definitions/uint32-array + + resets: + description: | + Reset specifier pair consists of phandle for the reset controller and + reset lines used by this controller. + + reset-names: + description: | + reset signal name strings sorted in the same order as the resets + property. + + qcom,qmp-phy-init-seq: + description: | + QMP PHY initialization sequence with reg offset, its value, delay after + register write. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,qmp-phy-reg-offset: + description: | + Provides important phy register offsets in an order defined in the phy + driver. Provide below mentioned register offsets in order for non USB DP + combo PHY:: + - USB3_PHY_PCS_STATUS + - USB3_PHY_AUTONOMOUS_MODE_CTRL + - USB3_PHY_LFPS_RXTERM_IRQ_CLEAR + - USB3_PHY_POWER_DOWN_CONTROL + - USB3_PHY_SW_RESET + - USB3_PHY_START + In addion to above following set of registers offset needed for USB DP + combo PHY in mentioned order:: + - USB3_DP_DP_PHY_PD_CTL + - USB3_DP_COM_POWER_DOWN_CTRL + - USB3_DP_COM_SW_RESET + - USB3_DP_COM_RESET_OVRD_CTRL + - USB3_DP_COM_PHY_MODE_CTRL + - USB3_DP_COM_TYPEC_CTRL + - USB3_DP_COM_SWI_CTRL + Optional register for enabling/disabling VLS clamp if available:: + - USB3_PCS_MISC_CLAMP_ENABLE + Optional register for configuring USB Type-C port select if available:: + - USB3_PHY_PCS_MISC_TYPEC_CTRL + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,vbus-valid-override: + description: | + If present, indicates VBUS pin is not connected to the USB PHY and the + controller must rely on external VBUS notification in order to manually + relay the notification to the SSPHY. + + qcom,vdd-max-load-uA: + description: | + If present, indicates the maximum current (in uA) the PHY is expected to + draw from the vdd power supply. + + qcom,core-voltage-level: + description: | + This property must be a list of three integer values (no, min, max) where + each value represents either a voltage in microvolts or a value + corresponding to voltage corner. + + qcom,core-max-load-uA: + description: | + If present, indicates the maximum current (in uA) the PHY is expected to + draw from the core power supply. + + qcom,link-training-reset: + description: | + This property indicates to start link training timer to reset the elastic + buffer based on rx equalization value. + + extcon: + description: | + phandle to external connector devices which provide type-C based + "USB-HOST" cable events. This phandle is used for notifying number of + lanes used in case of USB+DP concurrent mode to driver. + +required: + - compatible + - reg + - reg-names + - vdd-supply + - core-supply + - clocks + - clock-names + - qcom,vdd-voltage-level + - resets + - reset-names + - qcom,qmp-phy-init-seq + - qcom,qmp-phy-reg-offset + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + usb_qmp_dp_phy: ssphy@88e8000 { + compatible = "qcom,usb-ssphy-qmp-dp-combo"; + reg = <0x88e8000 0x3000>; + reg-names = "qmp_phy_base"; + + vdd-supply = <&pm_v6g_l3>; + qcom,vdd-voltage-level = <0 912000 912000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&pm_v8_l3>; + usb3_dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, + <&rpmhcc RPMH_CXO_PAD_CLK>, + <&tcsrcc TCSR_USB3_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", + "pipe_clk_ext_src", "ref_clk_src", + "ref_clk", "com_aux_clk"; + + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, + <&gcc GCC_USB3_PHY_PRIM_BCR>; + reset-names = "global_phy_reset", "phy_reset"; + + pinctrl-names = "default"; + pinctrl-0 = <&usb3phy_portselect_default>; + qcom,qmp-phy-reg-offset = + ; + + qcom,qmp-phy-init-seq = + /* */ + ; + }; +... From de8649c8e19b022f35b0661e7d8bc067d6d6c19e Mon Sep 17 00:00:00 2001 From: Ronak Vijay Raheja Date: Thu, 1 Jun 2023 15:22:45 -0700 Subject: [PATCH 2/2] ARM: dts: msm: Add USB device nodes for sun Enable USB related properties for USB functionality on sun. Change-Id: Ibb522859494c0e939b46a6b790448fc2e62bd37e Signed-off-by: Ronak Vijay Raheja --- qcom/sun-rumi.dtsi | 28 ++++++++++++++++++++++ qcom/sun-usb.dtsi | 59 ++++++++++++++++++++++++++++++++++++++++++++++ qcom/sun.dtsi | 1 + 3 files changed, 88 insertions(+) create mode 100644 qcom/sun-usb.dtsi diff --git a/qcom/sun-rumi.dtsi b/qcom/sun-rumi.dtsi index 485d3902..3d04c49f 100644 --- a/qcom/sun-rumi.dtsi +++ b/qcom/sun-rumi.dtsi @@ -21,3 +21,31 @@ &qupv3_se7_2uart { qcom,rumi_platform; }; + +&soc { + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + usb_emuphy: phy@a784000 { + compatible = "qcom,usb-emu-phy"; + reg = <0x0a784000 0x9500>; + + qcom,emu-init-seq = <0xfffff 0x4 + 0xffff0 0x4 + 0x100000 0x20 + 0x0 0x20 + 0x000101F0 0x20 + 0x00100000 0x3c + 0x0 0x3c + 0x0 0x4>; + }; +}; + +&usb0 { + dwc3@a600000 { + usb-phy = <&usb_emuphy>, <&usb_nop_phy>; + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + }; +}; diff --git a/qcom/sun-usb.dtsi b/qcom/sun-usb.dtsi new file mode 100644 index 00000000..37dcfab2 --- /dev/null +++ b/qcom/sun-usb.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + usb0: ssusb@a600000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xa600000 0x100000>; + reg-names = "core_base"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk"; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + reset-names = "core_reset"; + + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event_irq"; + + qcom,dis-sending-cm-l1-quirk; + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,core-clk-rate-disconnected = <133333333>; + + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0xa600000 0xd93c>; + + iommus = <&apps_smmu 0x40 0x0>; + qcom,iommu-dma = "bypass"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + dma-coherent; + + interrupts = ; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,is-utmi-l1-suspend; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_u2_susphy_quirk; + snps,ssp-u3-u0-quirk; + tx-fifo-resize; + dr_mode = "otg"; + maximum-speed = "super-speed-plus"; + usb-role-switch; + }; + }; +}; diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index 6f0902af..4588dbc9 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -899,6 +899,7 @@ #include "sun-pinctrl.dtsi" #include "sun-regulators.dtsi" #include "sun-qupv3.dtsi" +#include "sun-usb.dtsi" &qupv3_se7_2uart { status = "ok";