Merge "dt-bindings: clock: Add Clock Controllers bindings for Pineapple"
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76
bindings/clock/qcom,camcc-pineapple.yaml
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76
bindings/clock/qcom,camcc-pineapple.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,camcc-pineapple.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. Camera Clock & Reset Controller Binding for PINEAPPLE
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maintainers:
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- Xubin Bai <quic_xubibai@quicinc.com>
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description: |
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Camera clock control module which supports the clocks, resets and
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power domains on PINEAPPLE.
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See also:
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- dt-bindings/clock/qcom,camcc-pineapple.h
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properties:
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compatible:
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enum:
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- qcom,pineapple-camcc
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- qcom,pineapple-camcc-v2
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clocks:
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items:
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- description: Board XO source
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- description: Sleep clock source
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clock-names:
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items:
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- const: bi_tcxo
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- const: sleep_clk
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qcom,cam_crm-crmc:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: Phandle pointer to the CESTA crmc node
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vdd_mm-supply:
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description: Phandle pointer to the vdd_mm logic rail supply
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vdd_mx-supply:
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description: Phandle pointer to the vdd_mx logic rail supply
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vdd_mxc-supply:
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description: Phandle pointer to the vdd_mxc logic rail supply
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required:
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- compatible
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- clocks
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- clock-names
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allOf:
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- $ref: "qcom,gcc.yaml#"
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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camcc: clock-controller@ade0000 {
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compatible = "qcom,pineapple-camcc", "syscon";
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reg = <0xade0000 0x20000>;
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reg-name = "cc_base";
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vdd_mm-supply = <&VDD_MM_LEVEL>;
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vdd_mx-supply = <&VDD_MX_LEVEL>;
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vdd_mxc-supply = <&VDD_MXC_LEVEL>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&sleep_clk>;
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clock-names = "bi_tcxo",
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"sleep_clk";
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qcom,cam_crm-crmc = <&camcc_crmc>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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...
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82
bindings/clock/qcom,debugcc.yaml
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82
bindings/clock/qcom,debugcc.yaml
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@@ -0,0 +1,82 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,debugcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. Debug Clock Controller Binding
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maintainers:
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- Xubin Bai <quic_xubibai@quicinc.com>
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description: |
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Debug Clock Controller module which support debug clock controllers.
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properties:
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compatible:
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enum:
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- qcom,pineapple-debugcc
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clocks:
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items:
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- description: Board XO source
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clock-names:
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items:
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- const: xo_clk_src
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qcom,gcc:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: phandle to the GCC device node
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qcom,gpucc:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: phandle to the GPU CC device node
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qcom,videocc:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: phandle to the Video CC device node
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qcom,dispcc:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: phandle to the Display CC device node
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qcom,camcc:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: phandle to the Camera CC device node
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qcom,apsscc:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: phandle to the APSS CC device node
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qcom,mccc:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: phandle to the Memory Controller CC device node
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required:
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- compatible
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- clocks
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- clock-names
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allOf:
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- $ref: "qcom,gcc.yaml#"
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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debugcc: qcom,cc-debug {
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compatible = "qcom,pineapple-debugcc";
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qcom,gcc = <&gcc>;
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qcom,gpucc = <&gpucc>;
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qcom,videocc = <&videocc>;
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qcom,dispcc = <&dispcc>;
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qcom,camcc = <&camcc>;
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qcom,apsscc = <&apsscc>;
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qcom,mccc = <&mccc>;
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clock-names = "xo_clk_src";
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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#clock-cells = <1>;
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};
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...
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@@ -4,19 +4,20 @@
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$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250/SM8350
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title: Qualcomm Technologies, Inc. Display Clock & Reset Controller Binding for SM8x50
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maintainers:
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- Jonathan Marek <jonathan@marek.ca>
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description: |
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Qualcomm display clock control module which supports the clocks, resets and
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power domains on SM8150/SM8250/SM8350.
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Display clock control module which supports the clocks, resets and
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power domains on SM8x50.
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See also:
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dt-bindings/clock/qcom,dispcc-sm8150.h
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dt-bindings/clock/qcom,dispcc-sm8250.h
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dt-bindings/clock/qcom,dispcc-sm8350.h
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dt-bindings/clock/qcom,dispcc-pineapple.h
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properties:
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compatible:
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@@ -25,6 +26,7 @@ properties:
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- qcom,sm8150-dispcc
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- qcom,sm8250-dispcc
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- qcom,sm8350-dispcc
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- qcom,pineapple-dispcc
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clocks:
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items:
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@@ -4,13 +4,13 @@
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$id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Graphics Clock & Reset Controller Binding
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title: Qualcomm Technologies, Inc. Graphics Clock & Reset Controller Binding
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maintainers:
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- Taniya Das <tdas@codeaurora.org>
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description: |
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Qualcomm graphics clock control module which supports the clocks, resets and
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Graphics clock control module which supports the clocks, resets and
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power domains on Qualcomm SoCs.
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See also:
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@@ -21,6 +21,7 @@ description: |
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dt-bindings/clock/qcom,gpucc-sm6350.h
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dt-bindings/clock/qcom,gpucc-sm8150.h
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dt-bindings/clock/qcom,gpucc-sm8250.h
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dt-bindings/clock/qcom,gpucc-pineapple.h
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properties:
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compatible:
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@@ -33,6 +34,7 @@ properties:
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- qcom,sm6350-gpucc
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- qcom,sm8150-gpucc
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- qcom,sm8250-gpucc
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- qcom,pineapple-gpucc
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clocks:
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items:
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44
bindings/clock/qcom,tcsrcc.yaml
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44
bindings/clock/qcom,tcsrcc.yaml
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@@ -0,0 +1,44 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,tcsrcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. Top-Level CSR Clock & Reset Controller Binding
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maintainers:
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- Xubin Bai <quic_xubibai@quicinc.com>
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description: |
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Top-Level CSR Clock & Reset Controller Binding
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See also:
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- dt-bindings/clock/qcom,tcsrcc-pineapple.h
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properties:
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compatible:
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enum:
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- qcom,pineapple-tcsrcc
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required:
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- compatible
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- reg
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- reg-name
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allOf:
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- $ref: "qcom,gcc.yaml#"
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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tcsrcc: clock-controller@1f40000 {
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compatible = "qcom,pineapple-tcsrcc", "syscon";
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reg = <0x1f40000 0xc0000>;
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reg-name = "cc_base";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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...
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@@ -4,13 +4,13 @@
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$id: http://devicetree.org/schemas/clock/qcom,videocc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Video Clock & Reset Controller Binding
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title: Qualcomm Technologies, Inc. Video Clock & Reset Controller Binding
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maintainers:
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- Taniya Das <tdas@codeaurora.org>
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description: |
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Qualcomm video clock control module which supports the clocks, resets and
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Video clock control module which supports the clocks, resets and
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power domains on Qualcomm SoCs.
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See also:
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@@ -19,6 +19,7 @@ description: |
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dt-bindings/clock/qcom,videocc-sdm845.h
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dt-bindings/clock/qcom,videocc-sm8150.h
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dt-bindings/clock/qcom,videocc-sm8250.h
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dt-bindings/clock/qcom,videocc-pineapple.h
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properties:
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compatible:
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@@ -28,6 +29,8 @@ properties:
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- qcom,sdm845-videocc
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- qcom,sm8150-videocc
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- qcom,sm8250-videocc
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- qcom,pineapple-videocc
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- qcom,pineapple-videocc-v2
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clocks:
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items:
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