diff --git a/bindings/clock/qcom,camcc-pineapple.yaml b/bindings/clock/qcom,camcc-pineapple.yaml new file mode 100644 index 00000000..205a0ded --- /dev/null +++ b/bindings/clock/qcom,camcc-pineapple.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,camcc-pineapple.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Camera Clock & Reset Controller Binding for PINEAPPLE + +maintainers: + - Xubin Bai + +description: | + Camera clock control module which supports the clocks, resets and + power domains on PINEAPPLE. + + See also: + - dt-bindings/clock/qcom,camcc-pineapple.h + +properties: + compatible: + enum: + - qcom,pineapple-camcc + - qcom,pineapple-camcc-v2 + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + + clock-names: + items: + - const: bi_tcxo + - const: sleep_clk + + qcom,cam_crm-crmc: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle pointer to the CESTA crmc node + + vdd_mm-supply: + description: Phandle pointer to the vdd_mm logic rail supply + + vdd_mx-supply: + description: Phandle pointer to the vdd_mx logic rail supply + + vdd_mxc-supply: + description: Phandle pointer to the vdd_mxc logic rail supply + +required: + - compatible + - clocks + - clock-names + +allOf: + - $ref: "qcom,gcc.yaml#" + +unevaluatedProperties: false + +examples: + - | + #include + camcc: clock-controller@ade0000 { + compatible = "qcom,pineapple-camcc", "syscon"; + reg = <0xade0000 0x20000>; + reg-name = "cc_base"; + vdd_mm-supply = <&VDD_MM_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + vdd_mxc-supply = <&VDD_MXC_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>; + clock-names = "bi_tcxo", + "sleep_clk"; + qcom,cam_crm-crmc = <&camcc_crmc>; + #clock-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/bindings/clock/qcom,debugcc.yaml b/bindings/clock/qcom,debugcc.yaml new file mode 100644 index 00000000..d22c7d7d --- /dev/null +++ b/bindings/clock/qcom,debugcc.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,debugcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Debug Clock Controller Binding + +maintainers: + - Xubin Bai + +description: | + Debug Clock Controller module which support debug clock controllers. + +properties: + compatible: + enum: + - qcom,pineapple-debugcc + + clocks: + items: + - description: Board XO source + + clock-names: + items: + - const: xo_clk_src + + qcom,gcc: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the GCC device node + + qcom,gpucc: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the GPU CC device node + + qcom,videocc: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the Video CC device node + + qcom,dispcc: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the Display CC device node + + qcom,camcc: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the Camera CC device node + + qcom,apsscc: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the APSS CC device node + + qcom,mccc: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the Memory Controller CC device node + +required: + - compatible + - clocks + - clock-names + +allOf: + - $ref: "qcom,gcc.yaml#" + +unevaluatedProperties: false + +examples: + - | + #include + debugcc: qcom,cc-debug { + compatible = "qcom,pineapple-debugcc"; + qcom,gcc = <&gcc>; + qcom,gpucc = <&gpucc>; + qcom,videocc = <&videocc>; + qcom,dispcc = <&dispcc>; + qcom,camcc = <&camcc>; + qcom,apsscc = <&apsscc>; + qcom,mccc = <&mccc>; + clock-names = "xo_clk_src"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + #clock-cells = <1>; + }; +... diff --git a/bindings/clock/qcom,dispcc-sm8x50.yaml b/bindings/clock/qcom,dispcc-sm8x50.yaml index 7a8d375e..b8b5a7d4 100644 --- a/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -4,19 +4,20 @@ $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250/SM8350 +title: Qualcomm Technologies, Inc. Display Clock & Reset Controller Binding for SM8x50 maintainers: - Jonathan Marek description: | - Qualcomm display clock control module which supports the clocks, resets and - power domains on SM8150/SM8250/SM8350. + Display clock control module which supports the clocks, resets and + power domains on SM8x50. See also: dt-bindings/clock/qcom,dispcc-sm8150.h dt-bindings/clock/qcom,dispcc-sm8250.h dt-bindings/clock/qcom,dispcc-sm8350.h + dt-bindings/clock/qcom,dispcc-pineapple.h properties: compatible: @@ -25,6 +26,7 @@ properties: - qcom,sm8150-dispcc - qcom,sm8250-dispcc - qcom,sm8350-dispcc + - qcom,pineapple-dispcc clocks: items: diff --git a/bindings/clock/qcom,gpucc.yaml b/bindings/clock/qcom,gpucc.yaml index a7d0af1b..9dca30b1 100644 --- a/bindings/clock/qcom,gpucc.yaml +++ b/bindings/clock/qcom,gpucc.yaml @@ -4,13 +4,13 @@ $id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Graphics Clock & Reset Controller Binding +title: Qualcomm Technologies, Inc. Graphics Clock & Reset Controller Binding maintainers: - Taniya Das description: | - Qualcomm graphics clock control module which supports the clocks, resets and + Graphics clock control module which supports the clocks, resets and power domains on Qualcomm SoCs. See also: @@ -21,6 +21,7 @@ description: | dt-bindings/clock/qcom,gpucc-sm6350.h dt-bindings/clock/qcom,gpucc-sm8150.h dt-bindings/clock/qcom,gpucc-sm8250.h + dt-bindings/clock/qcom,gpucc-pineapple.h properties: compatible: @@ -33,6 +34,7 @@ properties: - qcom,sm6350-gpucc - qcom,sm8150-gpucc - qcom,sm8250-gpucc + - qcom,pineapple-gpucc clocks: items: diff --git a/bindings/clock/qcom,tcsrcc.yaml b/bindings/clock/qcom,tcsrcc.yaml new file mode 100644 index 00000000..383fe3b6 --- /dev/null +++ b/bindings/clock/qcom,tcsrcc.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,tcsrcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Top-Level CSR Clock & Reset Controller Binding + +maintainers: + - Xubin Bai + +description: | + Top-Level CSR Clock & Reset Controller Binding + + See also: + - dt-bindings/clock/qcom,tcsrcc-pineapple.h + +properties: + compatible: + enum: + - qcom,pineapple-tcsrcc + +required: + - compatible + - reg + - reg-name + +allOf: + - $ref: "qcom,gcc.yaml#" + +unevaluatedProperties: false + +examples: + - | + #include + tcsrcc: clock-controller@1f40000 { + compatible = "qcom,pineapple-tcsrcc", "syscon"; + reg = <0x1f40000 0xc0000>; + reg-name = "cc_base"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + +... diff --git a/bindings/clock/qcom,videocc.yaml b/bindings/clock/qcom,videocc.yaml index 3cdbcebd..17037da9 100644 --- a/bindings/clock/qcom,videocc.yaml +++ b/bindings/clock/qcom,videocc.yaml @@ -4,13 +4,13 @@ $id: http://devicetree.org/schemas/clock/qcom,videocc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Video Clock & Reset Controller Binding +title: Qualcomm Technologies, Inc. Video Clock & Reset Controller Binding maintainers: - Taniya Das description: | - Qualcomm video clock control module which supports the clocks, resets and + Video clock control module which supports the clocks, resets and power domains on Qualcomm SoCs. See also: @@ -19,6 +19,7 @@ description: | dt-bindings/clock/qcom,videocc-sdm845.h dt-bindings/clock/qcom,videocc-sm8150.h dt-bindings/clock/qcom,videocc-sm8250.h + dt-bindings/clock/qcom,videocc-pineapple.h properties: compatible: @@ -28,6 +29,8 @@ properties: - qcom,sdm845-videocc - qcom,sm8150-videocc - qcom,sm8250-videocc + - qcom,pineapple-videocc + - qcom,pineapple-videocc-v2 clocks: items: