GLINK PKT provides a userspace interface to RPMSG GLINK through
character device node. Add the nodes and corresponding channel
devices to enable GLINK communication from userspace.
Change-Id: I0b7c9b273df3201113095fba9c70d10599b8faf7
Signed-off-by: Kishore Kumar Ravi <quic_kiskum@quicinc.com>
Add the smp2p sleepstate and qsee_ipc_irq_bridge
nodes for sun.
Change-Id: Iecdde69fe89d883c87ea9cd527a6753355d2327d
Signed-off-by: Kishore Kumar Ravi <quic_kiskum@quicinc.com>
Add dts entries for smcinvoke and
qtee shmbridge driver in sun vm.
Change-Id: I5ce5eddf5854735a676e1bf1bb0c5dfa67d569b6
Signed-off-by: Anmolpreet Kaur <quic_anmolpre@quicinc.com>
The mvs0c_gdsc needs to be enabled first for mvs0_gdsc to turn on
reliably, so list it as a parent to enforce this relationship.
Change-Id: I2b6cf6861d1bf8ddb8eb764be3ba175edee9e3db
Signed-off-by: Mike Tipton <quic_mdtipton@quicinc.com>
Needed for SPU pil on sun dtsi.
Remoteproc-spss, spcom and spss_utils are disabled.
Change-Id: I97519bacccee2f7094edbcf32e3fdac29d67ac77
Signed-off-by: Nurit Lichtenstein <quic_nuritl@quicinc.com>
Add an SPMI debug device and associated PMIC child devices for the
primary SPMI interface. This provides consumers with unrestricted
access to the PMIC registers on pre-production devices. This helps
to simplify debugging.
Change-Id: I920a3655e0e257ee819c7227e154d27ee43f3250
Signed-off-by: David Collins <quic_collinsd@quicinc.com>
Add SMB and IDT charger PMIC devices inside of the pmic-glink-debug
device. These are interfaced over I2C and an SPMI bridge bus. This
ensures that software is able to access the registers of these PMICs.
Change-Id: I7afc56cb78a353960cb7db98ce5d9b51a05db9fe
Signed-off-by: David Collins <quic_collinsd@quicinc.com>
Add PMIC Glink ADC channel nodes for Sun MTP and QRD boards.
This exposes an interface for software to read PMIC charger ADC
channels for input current, charge current, and die temperature.
This is useful for PMICs connected via I2C which are only
accessible to charger firmware.
Change-Id: Ie8a9a0690b9937f9c0c541123c28e544ba3495ec
Signed-off-by: David Collins <quic_collinsd@quicinc.com>
Disable software DRV (L1SS sleep) with PCIe instance
on sun platform as ADSP subsystem (software DRV component)
doesn't support this functionality.
Only CESTA based hardware DRV is supported.
Change-Id: I75368fab37e8bcaaa3c65320b6fdd37e023d3297
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
These clock phandles are necessary to ensure the clock devices probe
before debugcc. Debugcc needs its parent clock devices to probe first,
otherwise it'll invalidate their associated mux_sels during
clk_debug_mux_init() and they can't be measured.
Change-Id: I30d1a9e24ae1ac5a9efc7d8f8e0740ebdce8e1b0
Signed-off-by: Mike Tipton <quic_mdtipton@quicinc.com>
Add the missing phy gdsc node in the pcie dt node for sun.
Change-Id: I0257c6123d4d3e8fe2740569bd4def68fa3c92a8
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Add PMIC Glink devices and their client devices. The PMIC Glink
device with name PMIC_RTR_ADSP_APPS supports the clients: ucsi,
altmode, and battery_charger. The PMIC Glink device with name
PMIC_LOGS_ADSP_APPS supports the clients: battery_debug,
pmic_glink_debug, charger_ulog_glink, and glink_adc.
Change-Id: Ib5a15c136c77c8368d4a561f266a1588c4649893
Signed-off-by: David Collins <quic_collinsd@quicinc.com>
Describe the communication channel used to communicate with the
firmware which supports onlining and offlining of memory.
Keep the device in a disabled state for now until a conflict
between THP and memory-hotplug features can be resolved.
Change-Id: I3d74d9d3d58d379b2a91ee976a72dddfb7a221c6
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
Add ufs support for mtp/cdp/qrd sun platforms.
Enable ufs's smmu fastmap attribute.
Enable ufs host and device resets.
Change-Id: I7e4194a48c022284308c3debd6e18be40289693b
Signed-off-by: Bao D. Nguyen <quic_nguyenb@quicinc.com>
Add nodes to enable qcom dcvs, bwmon and memlat
on sun.
Change-Id: I515aa98f01b29fb51be11db33930f96193d13401
Signed-off-by: Amir Vajid <quic_avajid@quicinc.com>
Add nodes to enable scmi communication to cpucp on sun.
Change-Id: I574949e32e397047701f836d54115f56414ea023
Signed-off-by: Amir Vajid <quic_avajid@quicinc.com>
Describe the available dma-buf memory pools on sun-vm.
Change-Id: I205b826849f36078d05a92492238d80a884aa65a
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
Describe the register, interrupts, and settings of the arm-smmu device.
Change-Id: I0ca4c90e2f767ed6240dd6ad6fc6cc8e7f6c278d
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
This change adds system low power violators device node.
Change-Id: Ie4b7923c2ef96d6d762275b7241948e120230163
Signed-off-by: Minghao Zhang <quic_minghao@quicinc.com>
Add initial device trees to support Sun QRD sku1 and sku2 SoC
and it's platforms.
Change-Id: Ibf28cbc9f33f19908c4d8ac1b431d17632c43e6b
Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
Remove fixed-factor-clock and enable device node for rpmh
clocks under apps_rsc in place of fixed clocks.
Change-Id: I9c4d242882f29f616574e339581722b65f27a74f
Signed-off-by: Xubin Bai <quic_xubibai@quicinc.com>
Add RPMH_CXO_CLK as ref_clk to UFS for Sun on pre-sil.
On Rumi ref_clk is to UFS PHY is 19.2MHz and actual device
it is 38.4MHz.
Also update correct gcc header file for sun.
Change-Id: I78ed60095e5229405e7962f4676bfab7b7556676
Signed-off-by: Vivek Aknurwar <quic_viveka@quicinc.com>
Describe the properties of the memory region virtio-mem supports.
Change-Id: Ifdc420d25c4fcf1acc93ccd82a80c89857b3c427
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
Describe the message queues and capabilities of the mem-buf device.
Change-Id: I9ff137c3cfee8d5f9e56930bf8ca9a81066e0150
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
Add device_type property for the pcie devicetree nodes
in sun.
This is needed to make sure that the pcie devicetree node
is associated with the pci bus when ranges property gets
parsed by the of/address.c driver.
And this change is mandatory for pci devicetree nodes with
the introduction of the following change in of/address.c
upstream commit <3d5089c4263d> "of/address: Add support
for 3 address cell bus".
Without this change, BAR address allocation failure will
happen as error logs below as the flags cell in ranges
property in devicetree will be read wrong.
pci-msm 1c00000.qcom,pcie:err 0x0060200000..0x00602fffff -> 0x0060200000.
pci-msm 1c00000.qcom,pcie:err 0x0060300000..0x0063ffffff -> 0x0060300000.
pci-msm 1c00000.qcom,pcie: non-prefetchable memory resource required.
pci 0000:00:00.0: BAR 0: no space for [mem size 0x00001000 64bit].
pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x00001000 64bit].
Change-Id: I8b1591ea83784ffc19c928e1af73117657ac7f15
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Add device_type property for the pcie devicetree nodes
in pineapple.
This is needed to make sure that the pcie devicetree node
is associated with the pci bus when ranges property gets
parsed by the of/address.c driver.
And this change is mandatory for pci devicetree nodes with
the introduction of the following change in of/address.c
upstream commit <3d5089c4263d> "of/address: Add support
for 3 address cell bus".
Without this change, BAR address allocation failure will
happen as error logs below as the flags cell in ranges
property in devicetree will be read wrong.
pci-msm 1c00000.qcom,pcie:err 0x0060200000..0x00602fffff -> 0x0060200000.
pci-msm 1c00000.qcom,pcie:err 0x0060300000..0x0063ffffff -> 0x0060300000.
pci-msm 1c00000.qcom,pcie: non-prefetchable memory resource required.
pci 0000:00:00.0: BAR 0: no space for [mem size 0x00001000 64bit].
pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x00001000 64bit].
Change-Id: I212e023880ed8373eb17379754da84b6947d1171
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Update enable-method to PSCI. Add idle-states node and
update cpu node to include appropriate idle state.
Disabled all idle-states for rumi.
Change-Id: I313d52c60081ef1d568781e33d0f2fed1a1f2de4
Signed-off-by: Rashid Zafar <quic_rzafar@quicinc.com>
Add a regulator over-current (OCP) notifier device along with
supply properties to map from PMIC peripherals to specific
regulator devices. This provides a mechanism to notify
consumers of a particular regulator when OCP occurs.
Change-Id: I17ee6af65492ece062722c41f97f3ea052970a25
Signed-off-by: David Collins <quic_collinsd@quicinc.com>
Add a fixed regulator device for the DBO3 buck-boost regulator.
It is enabled via PM8550 GPIO 9 and outputs 3.6 V.
Change-Id: Iff6e0e1cceed6ad369fb67aca3926f5a808cf3e6
Signed-off-by: David Collins <quic_collinsd@quicinc.com>
Add a PMIC PON log parser device which reads the log stored in
PMK8550 SDAM5 and SDAM6.
Change-Id: I944df2186b27ebb42cf2d4dc8f51dbf7b40cea9b
Signed-off-by: David Collins <quic_collinsd@quicinc.com>
With the recent kernel upgrade to 6.4, swiotlb_init() path is taken
because of the new kernel config CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC,
which is enabled by default. But this should not done for trusted VMs
supported on Sun and Pineapple VMs, as these VMs would be using carveout
swiotlb memory set up separately by virtio mmio driver through the
feature CONFIG_SWIOTLB_NONLINEAR. Hence, add swiotlb=noforce kernel
command line to disable generic swiotlb setup/init for VMs. Without
this option set, VM boot up failure is observed.
Change-Id: Ia35cd9a2f95f41b0b0daa6cf75799fd4432a95bd
Signed-off-by: Sahitya Tummala <quic_stummala@quicinc.com>
