Add the nodes for enable qrtr communication between primary vm and
oemvm on sun.
This adds platform devices and vdevice descriptions to start the
qrtr gunyah transport on both primary vm and oemvm device trees. This
also adds the device tree node to configure qrtr as node id 21 on oem
vm.
Change-Id: I1575853a67fe9edbcb751dbb71062b6da624d9be
Signed-off-by: Kishore Kumar Ravi <quic_kiskum@quicinc.com>
Enable the UFS MCQ feature on the Sun platforms.
Change-Id: I6d58bb14ea085cfd792cfea0073cccfa8be38edb
Signed-off-by: Bao D. Nguyen <quic_nguyenb@quicinc.com>
Add GSI related registers dt entry to sun to support GSI functions.
Change-Id: I0920fc27e827952d55d87a59b093d945830868d5
Signed-off-by: Elson Roy Serrao <quic_eserrao@quicinc.com>
From Armv8.6 the counter operates at a higher fixed frequency of 1GHz.
This implies a resolution of 1ns. Change cpu arch timer frequency to 1ns
from 52ns (19.2Mhz) resolution.
Change-Id: Ib0bfe643edbd4de568cf30ebaa1ec1175111352e
Signed-off-by: Murali Nalajala <quic_mnalajal@quicinc.com>
Update the L11B and S7I regulator max voltage limits to match
the latest guideline.
Change-Id: Ia36cdbe8ad6526070e43325ff3cdb2cc6bfc58f0
Signed-off-by: David Collins <quic_collinsd@quicinc.com>
Disable tpdm ddr-ubwcp, because the clocks associated with it are
not enabled.
Change-Id: I4bebde68995bc9831c067ca25978fae858b7536c
Signed-off-by: Yuanfang Zhang <quic_yuanfang@quicinc.com>
Current setting votes for 912mV for the QMP PHY vdd rail, which is above
what is recommended from the power grid. Set the vdd operating voltage to
880mV to match what is suggested, in order to maintain the regulator
numbers expected for the rail.
Change-Id: Iaefd58656c72427933e45000db21f55bc5de979c
Signed-off-by: Wesley Cheng <quic_wcheng@quicinc.com>
Arch timer and memtimer frequencies were set incorrectly for
silicon, so set to 1 GHz.
Change-Id: I309c1d79712145a4c86d168d923f91d6a6792142
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Add device tree node for measure nodes and enable
debug cc driver on Sun.
Change-Id: I5475161d0f1d7ce488b6372d19ba1212dea238f5
Signed-off-by: Vivek Aknurwar <quic_viveka@quicinc.com>
Add bindings for llcc_perfmon tool, populate llcc_perfmon
as child node of llcc cache-controller node.
Change-Id: Ib65da3295569297697cc039d39f3aef95887e482
Signed-off-by: Aman Kanwar <quic_akanwar@quicinc.com>
The "capacity-dmips-mhz" and "dynamic-power-coefficient" are
used to build Energy Model and subsequently capacity values are derived
from them which in turn is used by EAS to take placement decisions.
Add these to sun devicetree.
Change-Id: If96b00b5ba1e211867ba9b44c5af5f2c9e65200f
Signed-off-by: Sai Harshini Nimmala <quic_snimmala@quicinc.com>
Add gclk cycle counter register information to devicetree in a
separate node for use by associated driver.
Change-Id: Ie27724dc04703d496a652729d61e03e0f4ff0115
Signed-off-by: Sai Harshini Nimmala <quic_snimmala@quicinc.com>
Add cpufreq cycle counter register information to devicetree in a
separate node for use by associated driver.
Change-Id: If1b45003a1ce4faca372db2954293493bc45bbb6
Signed-off-by: Sai Harshini Nimmala <quic_snimmala@quicinc.com>
Adding a new node to devicetree for cycle counter driver. Add related
bindings file.
Change-Id: I381c5c693d96a054de1b3db5f9cd7ad8e4aa382b
Signed-off-by: Sai Harshini Nimmala <quic_snimmala@quicinc.com>
