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Merge "ARM: dts: msm: sun: Add capacity related information"

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qctecmdr
2023-11-15 17:05:22 -08:00
committed by Gerrit - the friendly Code Review server
parent 63e7cec2dd 5f39e6b141
commit f6f25cde63
5 changed files with 106 additions and 0 deletions
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24
qcom/pineapple-walt.dtsi Normal file
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@@ -0,0 +1,24 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&soc {
walt {
#address-cells = <1>;
#size-cells = <1>;
ranges;
qcom,cycle-cntr {
compatible = "qcom,epss";
reg = <0x17D91000 0x1000>,
<0x17D92000 0x1000>,
<0x17D93000 0x1000>,
<0x17D94000 0x1000>;
reg-names = "freq-domain0",
"freq-domain1",
"freq-domain2",
"freq-domain3";
};
};
};

1
qcom/pineapple.dtsi
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@@ -3432,6 +3432,7 @@
#include "pineapple-pcie.dtsi"
#include "msm-rdbg.dtsi"
#include "pineapple-thermal.dtsi"
#include "pineapple-walt.dtsi"
&qupv3_se15_2uart {
status = "ok";

44
qcom/qcom,cycle-cntr.yaml Normal file
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@@ -0,0 +1,44 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom,cycle-cntr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. (QTI) Cycle Counter Driver
maintainers:
- Sai Harshini Nimmala <quic_snimmala@quicinc.com>
description: |
The various cycle counter drivers are used to read the cycle counter registers of the appropriate HW used in the Qualcomm Technologies, Inc. SoC.
properties:
compatible:
oneOf:
- description: OSM cpufreq HW
items:
- const: qcom,cycle-cntr-hw
- description: EPSS cpufreq HW
items:
- const: qcom,epss
- description: NCC GCLK HW
items:
- const: qcom,gclk
reg:
items:
- description: Frequency domain 0 register region
- description: Frequency domain 1 register region
- description: Frequency domain 2 register region
- description: Frequency domain 3 register region
reg-names:
items:
- const: freq-domain0
- const: freq-domain1
- const: freq-domain2
- const: freq-domain3
additionalProperties: false

20
qcom/sun-walt.dtsi Normal file
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@@ -0,0 +1,20 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&soc {
walt {
#address-cells = <1>;
#size-cells = <1>;
ranges;
qcom,cycle-cntr {
compatible = "qcom,gclk";
reg = <0x18880400 0x8>,
<0x19880400 0x8>;
reg-names = "freq-domain0",
"freq-domain1";
};
};
};

17
qcom/sun.dtsi
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@@ -60,6 +60,8 @@
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
#cooling-cells = <2>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <238>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
@@ -76,6 +78,8 @@
power-domains = <&CPU_PD1>;
power-domain-names = "psci";
#cooling-cells = <2>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <238>;
next-level-cache = <&L2_0>;
};
@@ -88,6 +92,8 @@
power-domains = <&CPU_PD2>;
power-domain-names = "psci";
#cooling-cells = <2>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <238>;
next-level-cache = <&L2_0>;
};
@@ -100,6 +106,8 @@
power-domains = <&CPU_PD3>;
power-domain-names = "psci";
#cooling-cells = <2>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <238>;
next-level-cache = <&L2_0>;
};
@@ -112,6 +120,8 @@
power-domains = <&CPU_PD4>;
power-domain-names = "psci";
#cooling-cells = <2>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <238>;
next-level-cache = <&L2_0>;
};
@@ -124,6 +134,8 @@
power-domains = <&CPU_PD5>;
power-domain-names = "psci";
#cooling-cells = <2>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <238>;
next-level-cache = <&L2_0>;
};
@@ -136,6 +148,8 @@
power-domains = <&CPU_PD6>;
power-domain-names = "psci";
#cooling-cells = <2>;
capacity-dmips-mhz = <1894>;
dynamic-power-coefficient = <588>;
next-level-cache = <&L2_6>;
L2_6: l2-cache {
compatible = "arm,arch-cache";
@@ -152,6 +166,8 @@
power-domains = <&CPU_PD7>;
power-domain-names = "psci";
#cooling-cells = <2>;
capacity-dmips-mhz = <1894>;
dynamic-power-coefficient = <588>;
next-level-cache = <&L2_6>;
};
@@ -3217,6 +3233,7 @@
#include "sun-thermal.dtsi"
#include "sun-pcie.dtsi"
#include "msm-rdbg.dtsi"
#include "sun-walt.dtsi"
&qupv3_se7_2uart {
status = "ok";