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Merge "ARM: dts: msm: Enable clock rpmh device node for Sun"

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This commit is contained in:
qctecmdr
2023-10-23 19:23:17 -07:00
committed by Gerrit - the friendly Code Review server
parent b7633075ed ad62d3ca63
commit 2e40ed6c51
3 changed files with 30 additions and 26 deletions
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24
qcom/sun-rumi.dtsi
View File

@@ -4,7 +4,8 @@
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/qcom,gcc-pineapple.h>
#include <dt-bindings/clock/qcom,gcc-sun.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
#include "sun-pmic-overlay.dtsi"
@@ -141,6 +142,27 @@
vdda-qref-supply = <&pm_v8i_l3>;
vdda-qref-max-microamp = <30000>;
clock-names =
"core_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro",
"core_clk_ice",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
"rx_lane1_sync_clk";
clocks =
<&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_UFS_PHY_AHB_CLK>,
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
qcom,disable-lpm;
status = "ok";

31
qcom/sun.dtsi
View File

@@ -656,9 +656,15 @@
<CONTROL_TCS 0>,
<FAST_PATH_TCS 1>;
};
apps_bcm_voter: bcm_voter {
compatible = "qcom,bcm-voter";
};
rpmhcc: clock-controller {
compatible = "qcom,sun-rpmh-clk";
#clock-cells = <1>;
};
};
};
@@ -713,31 +719,6 @@
};
};
cxo: bi_tcxo {
compatible = "fixed-factor-clock";
clocks = <&xo_board>;
clock-mult = <1>;
clock-div = <4>;
#clock-cells = <0>;
clock-output-names = "bi_tcxo";
};
cxo_a: bi_tcxo_ao {
compatible = "fixed-factor-clock";
clocks = <&xo_board>;
clock-mult = <1>;
clock-div = <4>;
#clock-cells = <0>;
clock-output-names = "bi_tcxo_ao";
};
rpmhcc: clock-controller {
compatible = "fixed-clock";
clock-output-names = "rpmh_clocks";
clock-frequency = <19200000>;
#clock-cells = <1>;
};
cambistmclkcc: clock-controller@1760000 {
compatible = "qcom,sun-cambistmclkcc", "syscon";
reg = <0x1760000 0x6000>;