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ARM: dts: msm: Add device_type property for pcie nodes

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Add device_type property for the pcie devicetree nodes
in pineapple.

This is needed to make sure that the pcie devicetree node
is associated with the pci bus when ranges property gets
parsed by the of/address.c driver.

And this change is mandatory for pci devicetree nodes with
the introduction of the following change in of/address.c
upstream commit <3d5089c4263d> "of/address: Add support
for 3 address cell bus".

Without this change, BAR address allocation failure will
happen as error logs below as the flags cell in ranges
property in devicetree will be read wrong.
pci-msm 1c00000.qcom,pcie:err 0x0060200000..0x00602fffff -> 0x0060200000.
pci-msm 1c00000.qcom,pcie:err 0x0060300000..0x0063ffffff -> 0x0060300000.
pci-msm 1c00000.qcom,pcie: non-prefetchable memory resource required.
pci 0000:00:00.0: BAR 0: no space for [mem size 0x00001000 64bit].
pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x00001000 64bit].

Change-Id: I212e023880ed8373eb17379754da84b6947d1171
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
This commit is contained in:
Prudhvi Yarlagadda
2023-10-09 17:46:14 -07:00
parent 91593b8c04
commit 616915f5a1
1 changed files with 2 additions and 0 deletions
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2
qcom/pineapple-pcie.dtsi
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@@ -9,6 +9,7 @@
&soc {
pcie0: qcom,pcie@1c00000 {
compatible = "qcom,pci-msm";
device_type = "pci";
reg = <0x01c00000 0x3000>,
<0x01c06000 0x2000>,
@@ -303,6 +304,7 @@
pcie1: qcom,pcie@1c08000 {
compatible = "qcom,pci-msm";
device_type = "pci";
reg = <0x01c08000 0x3000>,
<0x01c0e000 0x2000>,