From 616915f5a1e14f25c22a3d8e02a5d946c39052ab Mon Sep 17 00:00:00 2001 From: Prudhvi Yarlagadda Date: Mon, 9 Oct 2023 17:46:14 -0700 Subject: [PATCH] ARM: dts: msm: Add device_type property for pcie nodes Add device_type property for the pcie devicetree nodes in pineapple. This is needed to make sure that the pcie devicetree node is associated with the pci bus when ranges property gets parsed by the of/address.c driver. And this change is mandatory for pci devicetree nodes with the introduction of the following change in of/address.c upstream commit <3d5089c4263d> "of/address: Add support for 3 address cell bus". Without this change, BAR address allocation failure will happen as error logs below as the flags cell in ranges property in devicetree will be read wrong. pci-msm 1c00000.qcom,pcie:err 0x0060200000..0x00602fffff -> 0x0060200000. pci-msm 1c00000.qcom,pcie:err 0x0060300000..0x0063ffffff -> 0x0060300000. pci-msm 1c00000.qcom,pcie: non-prefetchable memory resource required. pci 0000:00:00.0: BAR 0: no space for [mem size 0x00001000 64bit]. pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x00001000 64bit]. Change-Id: I212e023880ed8373eb17379754da84b6947d1171 Signed-off-by: Prudhvi Yarlagadda --- qcom/pineapple-pcie.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/pineapple-pcie.dtsi b/qcom/pineapple-pcie.dtsi index 8b4b17b7..b5368905 100644 --- a/qcom/pineapple-pcie.dtsi +++ b/qcom/pineapple-pcie.dtsi @@ -9,6 +9,7 @@ &soc { pcie0: qcom,pcie@1c00000 { compatible = "qcom,pci-msm"; + device_type = "pci"; reg = <0x01c00000 0x3000>, <0x01c06000 0x2000>, @@ -303,6 +304,7 @@ pcie1: qcom,pcie@1c08000 { compatible = "qcom,pci-msm"; + device_type = "pci"; reg = <0x01c08000 0x3000>, <0x01c0e000 0x2000>,