Commit Graph

1561 Commits

Author SHA1 Message Date
QCTECMDR Service
eb141530ac Merge "ARM: dts: qcom: Add support for cache-controller for Tuna" 2024-09-11 14:27:32 -07:00
QCTECMDR Service
5d5e85d97d Merge "ARM: dts: msm: Add eMMC & SD card support for sdxkova platforms" 2024-09-11 11:06:49 -07:00
Sneh Mankad
d3e5b0e0ad ARM: dts: msm: Modify PDC node for Tuna
This change corrects the PDC irq mapping configuration.

Change-Id: I85df1a464a56f2b32c83a26deecaab6f504fcb0d
Signed-off-by: Sneh Mankad <quic_smankad@quicinc.com>
2024-09-11 18:42:47 +05:30
Khaja Hussain Shaik Khaji
164a485a57 ARM: dts: msm: Add shared imem node for sdxkova SoC
Add shared internal memory nodes for sdxkova SoC.

Change-Id: I0565f4c6d87e2d3bcb016797815ba004f232d47c
Signed-off-by: Khaja Hussain Shaik Khaji <quic_kshaikkh@quicinc.com>
2024-09-11 04:48:46 -07:00
Khaja Hussain Shaik Khaji
77c254d1e8 ARM: dts: msm: Remove PDC dependency for TLMM node for sdxkova
This change removes the dependency of TLMM with PDC so that
it can probe without PDC. We can re-enable PDC dependency
once we validate PDC changes.

Change-Id: I3b78b6a5418ecf98675d31a8b5e47bdeeeedbd6b
Signed-off-by: Khaja Hussain Shaik Khaji <quic_kshaikkh@quicinc.com>
2024-09-11 17:12:17 +05:30
Ankit Sharma
7704cdcbcb ARM: dts: msm: tuna: Add a node for cpufreq cycle counter driver
Add cpufreq cycle counter register information to devicetree in a
separate node for use by associated driver.

Change-Id: I5c57507acf6d4488402424619ac9d2ad356fb308
Signed-off-by: Ankit Sharma <quic_anshar@quicinc.com>
2024-09-11 16:46:20 +05:30
Prakash Yadachi
63e44205fa ARM: dts: msm: Change ATID value of SNOC from 125 to 108
Change ATID value of SNOC from 125 to 108.

Change-Id: I74723aea491498ccbcc16da07154b9572a6d7974
Signed-off-by: Prakash Yadachi <quic_pyadachi@quicinc.com>
2024-09-11 14:53:31 +05:30
Sarthak Garg
c96dc22e54 ARM: dts: msm: Add eMMC & SD card support for sdxkova platforms
Add eMMC & SD card support for sdxkova platforms.

Change-Id: Ie472ffe3549052976f2901f5936067c109c98406
Signed-off-by: Sarthak Garg <quic_sartgarg@quicinc.com>
2024-09-10 23:41:49 -07:00
QCTECMDR Service
70ff8be250 Merge "ARM: dts: msm: Add scm nodes to sdxkova SoC" 2024-09-10 23:35:07 -07:00
Sachin Gupta
2540d2b415 ARM: dts: msm: Update dll_usr_ctl for sun
This change will update dll_usr_ctl to the recommended value.

Change-Id: I345b59546faf950645c0f173ac145e40124170f1
Signed-off-by: Sachin Gupta <quic_sachgupt@quicinc.com>
2024-09-11 10:42:31 +05:30
QCTECMDR Service
9d20226774 Merge "ARM: dts: msm: Move APSS RSC clients under APSS RSC node for sdxkova" 2024-09-10 20:01:35 -07:00
QCTECMDR Service
2299c32e5f Merge "ARM: dts: msm: Enable ICE driver and tmecom-qmp-client for tuna" 2024-09-10 20:01:35 -07:00
Patrick Daly
ebb646f4b7 ARM: dts: msm: Align rcu expedited parameters for sunvm
Use the same rcu configuration values on both PVM and QTVM.
This reduces latency of synchronize_rcu().

Change-Id: If023ae452c56e6172c33ccb2b14767376f86268b
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
2024-09-10 15:35:01 -07:00
Khaja Hussain Shaik Khaji
9c810cff96 ARM: dts: msm: Add scm nodes to sdxkova SoC
Add scm driver nodes for sdxkova SoC.

Change-Id: I7bdf4d7e6a7c81fab3055d543877e7380ea50585
Signed-off-by: Khaja Hussain Shaik Khaji <quic_kshaikkh@quicinc.com>
2024-09-10 22:02:37 +05:30
Keval Kulkarni
59f43a1541 ARM: dts: msm: Added arch_timer in sdxkova SoC DT
Upsteam DT does not have phandle for the armv8-timer node,
hence DT overlay is failing during ABL as phandle is necessary
for the overlay. Hence removed the timer node which was included
via upstream DT and added it along with a phandle.

Change-Id: Iba5b3ec985814fa44125c5918900dbf87cb45a6b
Signed-off-by: Keval Kulkarni <quic_kevalbha@quicinc.com>
2024-09-10 15:56:30 +05:30
Sarthak Garg
5b16785b02 ARM: dts: msm: Add eMMC & SD card support for sdxkova
Add eMMC & SD card support for sdxkova.

Change-Id: I0ff97235e8dc6e8fcbe80a5ae811b3832130a75c
Signed-off-by: Sarthak Garg <quic_sartgarg@quicinc.com>
2024-09-10 14:50:56 +05:30
Raghavendra Kakarla
39e309e42b ARM: dts: msm: Move APSS RSC clients under APSS RSC node for sdxkova
This change moves the APSS RSC clients under APSS RSC node
as child nodes. Earlier those were wrongly added under SOC.

Change-Id: I7e04b78a138eae18384a4ee976ff2bc0018ea30d
Signed-off-by: Raghavendra Kakarla <quic_rkakarla@quicinc.com>
2024-09-10 12:36:43 +05:30
Ravi Kumar Bokka
ee323e7dc1 ARM: dts: msm: Enable ICE driver and tmecom-qmp-client for tuna
This change adds dts entries for ICE(Inline Crypto Engine) and
tmecom-qmp-client driver for tuna target.

Test: Tested build compilation.

Change-Id: I307ced985dc5e22ecea321cac555b91858f5311a
Signed-off-by: Ravi Kumar Bokka <quic_c_rbokka@quicinc.com>
2024-09-10 11:10:59 +05:30
QCTECMDR Service
88be481e76 Merge "ARM: dts: msm: Update interconnect params for QUP and UART dt node" 2024-09-09 18:28:22 -07:00
QCTECMDR Service
224ebce9be Merge "ARM: dts: msm: Add smp2p node for tuna" 2024-09-09 15:13:42 -07:00
QCTECMDR Service
75af5a0306 Merge "ARM: dts: msm: add ice wrapped key support" 2024-09-08 21:31:08 -07:00
QCTECMDR Service
9a7dc3ce79 Merge "ARM: dts: qcom: Add aoss, aop and tme nodes for sdxkova" 2024-09-06 13:40:02 -07:00
Shivangi Kesharwani
73e418e81d ARM: dts: msm: add ice wrapped key support
Add support for ice wrapped keys to the SDHCI DTSI entry
on monaco target.

Signed-off-by: Shivangi Kesharwani <quic_skesharw@quicinc.com>
2024-09-06 06:24:54 -07:00
Vishnu Santhosh
c46bf07941 ARM: dts: qcom: Add aoss, aop and tme nodes for sdxkova
Add devicetree nodes to enable qmp communication with aop and tme.

Change-Id: I62d0020ca600820dd8ce256ee4cbe1ce0dc17b15
Signed-off-by: Vishnu Santhosh <quic_vishsant@quicinc.com>
2024-09-06 00:00:56 -07:00
Vishnu Santhosh
2ceed54f38 ARM: dts: msm: Add smp2p nodes for sdxkova
Add the smp2p device nodes to enable smp2p communication with remote
processors. This adds the configuration for Modem on sdxkova.

Change-Id: Ibd86fcf2a589bfb9f16a645797113f0f0345c81a
Signed-off-by: Vishnu Santhosh <quic_vishsant@quicinc.com>
2024-09-06 00:00:32 -07:00
Vishnu Santhosh
04904d20a8 ARM: dts: msm: Add smem nodes for sdxkova
Add smem nodes for sdxkova SoC.

Change-Id: I489aa0d9341cc48350a37c244135909d1686b0b5
Signed-off-by: Vishnu Santhosh <quic_vishsant@quicinc.com>
2024-09-06 12:10:36 +05:30
QCTECMDR Service
381e26daee Merge "ARM: dts: msm: Add smp2p for kera" 2024-09-05 23:28:40 -07:00
QCTECMDR Service
6b4807711d Merge "ARM: dts: qcom: Add cpe-wkk related devicetree file" 2024-09-05 19:12:40 -07:00
QCTECMDR Service
7f0219bb0f Merge "ARM: dts: msm: Remove console configuration in monaco dt" 2024-09-05 19:12:40 -07:00
QCTECMDR Service
7f53201cab Merge "ARM: dts: msm: Add LLCC node for sdxkova SoC" 2024-09-05 15:30:53 -07:00
QCTECMDR Service
205feb7cc8 Merge "ARM: dts: msm: Enable securemsm related nodes for tuna" 2024-09-05 15:30:53 -07:00
QCTECMDR Service
2d84786d74 Merge "ARM: dts: msm: Correct iova-width values for sun" 2024-09-05 03:56:26 -07:00
Pranav Mahesh Phansalkar
672d7646a1 ARM: dts: msm: Add smp2p for kera
Add the smp2p nodes for lpaidsp, modem, cdsp and soccp for kera.

Change-Id: If037dbee45de527f6eef54776f2f5b6f1b4e108e
Signed-off-by: Pranav Mahesh Phansalkar <quic_pphansal@quicinc.com>
2024-09-05 12:19:19 +05:30
kundan kumar
0edda568b1 ARM: dts: msm: Enable securemsm related nodes for tuna
Added qseecom, tz-log, qrng, qcedev,qtee_shmbridge,qcom_smcinvoke
securemsm nodes for tuna.

Change-Id: I7600c98cf2301b2e83d327017761e0362439f8e0
Signed-off-by: kundan kumar <quic_kunkum@quicinc.com>
2024-09-05 12:12:39 +05:30
Prakash Yadachi
6b30cd02c5 ARM: dts: msm: Add interconnect changes
Add gem_noc and config_noc interconnect
changes for Parrot and ravelin target.

Change-Id: Ia94f8503d7a580fefb3a68efac1a24d525083294
Signed-off-by: Prakash Yadachi <quic_pyadachi@quicinc.com>
2024-09-04 23:18:21 -07:00
Sayan Dey
160a80d44a ARM: dts: msm: Add LLCC node for sdxkova SoC
Add LLCC node for sdxkova to enable last level cache controller.

Change-Id: Ief1651c1bb72a4c8f170b2fc40e9879ab4781b3d
Signed-off-by: Sayan Dey <quic_sayand@quicinc.com>
2024-09-05 11:28:18 +05:30
Ramireddy KrishnaKanth Reddy
c1c4d9629c ARM: dts: msm: Enable fsa4480 in ravelin dtsi
Add compatible string for fsa4480 ravelin.

Change-Id: I01a3e454f3a506b5b86b8e980936810b195b2a0a
Signed-off-by: Ramireddy KrishnaKanth Reddy <quic_ramikris@quicinc.com>
2024-09-04 17:25:45 +05:30
QCTECMDR Service
cc13f7536b Merge "ARM: dts: msm: Add CPUSYS_VM support for Tuna" 2024-09-04 04:13:41 -07:00
QCTECMDR Service
c03efb9a8d Merge "ARM: dts: qcom: Include IPCC test node for sdxkova" 2024-09-04 00:28:10 -07:00
QCTECMDR Service
9eec6eeeea Merge "ARM: dts: msm: add mmc wrapped key support to ravelin" 2024-09-03 19:13:27 -07:00
Krishna Chaithanya Reddy G
f5fe3ae960 ARM: dts: msm: Update interconnect params for QUP and UART dt node
Currently the interconnect provider framework is expecting
the tag QCOM_ICC_TAG_ALWAYS as part of dtsi node of QUP.

In commit 481c435dd1 ("ARM: dts: qcom: sdxkova: update
interconnect providers with bcm-voter-names") interconnect
framework is not expecting the tag QCOM_ICC_TAG_ALWAYS, and
instead it is enabled by default or expects clients to override.

So, updated the QUPv3 and UART interconnects to remove the
additional interconnect tag.

Change-Id: If3780ec7156487f07cc8892a43341d1d9cb88b96
Signed-off-by: Krishna Chaithanya Reddy G <quic_kgangapu@quicinc.com>
2024-09-03 07:00:15 -07:00
Pradnya Dahiwale
1ad1abda94 ARM: dts: msm: Remove console configuration in monaco dt
Based on build version console configuration is made in monaco.bzl.
Hence remove console configuration from monaco dt.

Change-Id: Ie6c6c60fab4ecd729bc47b5bb87c8ea639f8f775
Signed-off-by: Pradnya Dahiwale <quic_pdahiwal@quicinc.com>
2024-09-03 04:58:57 -07:00
Pranav Mahesh Phansalkar
f039ef763f ARM: dts: msm: Add smp2p node for tuna
Add the smp2p device node to enable smp2p communication with WPSS.

Change-Id: I5ecfd5962c9136970e19ea646c2433f03e104ef8
Signed-off-by: Pranav Mahesh Phansalkar <quic_pphansal@quicinc.com>
2024-09-03 15:58:59 +05:30
QCTECMDR Service
03e09aa933 Merge "ARM: dts: qcom: sdxkova: update interconnect providers with bcm-voter-names" 2024-09-02 11:04:36 -07:00
QCTECMDR Service
e640fe35c1 Merge "ARM: dts: msm: Spilt memdump entries to static and dynamic" 2024-09-02 11:04:36 -07:00
Keval Kulkarni
c26f69e0e0 ARM: dts: qcom: Include IPCC test node for sdxkova
Include IPCC test node for sdxkova, so IPCC kernel-tests can
run on sdxkova.

Change-Id: I96e4f925d62eec54455b8f03f46217fc402e43a5
Signed-off-by: Keval Kulkarni <quic_kevalbha@quicinc.com>
Signed-off-by: Khaja Hussain Shaik Khaji <quic_kshaikkh@quicinc.com>
2024-09-02 15:20:15 +05:30
Keval Kulkarni
2e93118b13 ARM: dts: msm: Add ipcc node for sdxkova
Add ipcc node for sdxkova to enable inter processor
communication controller.

Adjust reg format for tz-log node.

Change-Id: I5519f5b8bfc02b2c85c1654a2f39c4ec61fdee9f
Signed-off-by: Keval Kulkarni <quic_kevalbha@quicinc.com>
Signed-off-by: Khaja Hussain Shaik Khaji <quic_kshaikkh@quicinc.com>
2024-09-02 15:18:12 +05:30
Shivendra Pratap
b7a42a08f0 ARM: dts: qcom: Add support for cache-controller for Tuna
Add support for LLCC for Tuna SoC in devicetree. Also, add
corresponding DT compatible string in bindings.

Change-Id: I16978c988bf691cf350a21edffc28084fa01c6e9
Signed-off-by: Shivendra Pratap <quic_spratap@quicinc.com>
2024-09-02 15:07:41 +05:30
QCTECMDR Service
821bb54eb2 Merge "ARM: dts: msm: Enable SMMU in kera" 2024-09-02 02:27:37 -07:00
Hrishabh Rajput
262363b430 ARM: dts: msm: Add CPUSYS_VM support for Tuna
Add reserved memory node for CPUSYS_VM and add support for CPUSYS_VM
loading for Tuna target.

Change-Id: If797d5038601ce17208e4da511edbe77c1ad2c9a
Signed-off-by: Hrishabh Rajput <quic_hrishabh@quicinc.com>
2024-09-02 12:27:19 +05:30