ARM: dts: qcom: Add support for cache-controller for Tuna

Add support for LLCC for Tuna SoC in devicetree. Also, add
corresponding DT compatible string in bindings.

Change-Id: I16978c988bf691cf350a21edffc28084fa01c6e9
Signed-off-by: Shivendra Pratap <quic_spratap@quicinc.com>

bindings/arm/msm/qcom,llcc.yaml

@@ -36,6 +36,7 @@ properties:
       - qcom,pineapple-llcc
       - qcom,sun-llcc
       - qcom,sdxpinn-llcc
+      - qcom,tuna-llcc
       - qcom,kera-llcc
       - qcom,x1e80100-llcc
 

qcom/tuna.dtsi

@@ -510,6 +510,20 @@
 		};
 	};
 
+	cache-controller@24800000 {
+		compatible = "qcom,tuna-llcc";
+		reg = <0x24800000 0x200000>, <0x25800000 0x200000>,
+			<0x24C00000 0x200000>, <0x25C00000 0x200000>,
+			<0x26800000 0x200000>, <0x26C00000 0x200000>;
+
+		reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
+				"llcc3_base", "llcc_broadcast_or_base",
+				"llcc_broadcast_and_base";
+
+		interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+		cap-based-alloc-and-pwr-collapse;
+	};
+
 	apps_rsc: rsc@17a00000 {
 		label = "apps_rsc";
 		compatible = "qcom,rpmh-rsc";