Add support for 1150MHz frequency (Turbo L2) in Kera GPU.
Change-Id: Ibe95ea6dbfaae4090879d59e45d746ce94eff096
Signed-off-by: Kaushal Sanadhya <quic_ksanadhy@quicinc.com>
Add MHI device related DT bindings on sdxkova.
Change-Id: I4bbdfc6e29555d6011cd474f5d0e54d9cd6517d7
Signed-off-by: Anvita T <quic_atadepal@quicinc.com>
Add PCIE endpoint related DT bindings on sdxkova.
Change-Id: Ied1e29b5f272cd10b18334e710c611c407422c43
Signed-off-by: Anvita T <quic_atadepal@quicinc.com>
Change VREG mapping string names to be in line with the
string names sent from FW.
Change-Id: Iea6e1e60295d212f367a686244e51f45f850cdf0
CRs-Fixed: 4074221
Increase the number of pipe clock toggles that will occur after
phystatus goes high at the output of the PHY during L1SS/P2 entry
in PCS_PCIE_POWER_STATE_CONFIG6 register, so that if the phy and
controller goes out of sync this may help us. The number of pipe
clock toggles is equal to (4*value)+1.
Change-Id: I7a31882f18879ef990825aa2d978fc7f39233472
Signed-off-by: Vivek Pernamitta <quic_vpernami@quicinc.com>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Add the soc-specific compatible string as it is
required to apply appropriate keepout regions.
Change-Id: I59fe0c9dffdf182bfb52468ef5a0d564ad7a8b38
Signed-off-by: Saranya R <quic_sarar@quicinc.com>
Update frequency plan as per the latest recommendation.
Change-Id: Ibdd4774022e90ebc0c670ce2cadc071b988698d4
Signed-off-by: Gayathri Veeragandam <quic_gveeraga@quicinc.com>
Add dtsi node to enable Hardware key manager for monaco target.
And add the device tree bindings for the Hardware key manager driver.
Change-Id: If1e38c3c71148fd85058eb31d4eee5f806e47fef
Signed-off-by: Shivangi Kesharwani <quic_skesharw@quicinc.com>
Add ulps and roi support for 120hz, 90hz & 60hz
VTDR6130 panel on Kera target.
Change-Id: I21bf599aadc6d4f10d25c3f1d232c1ba37a0d8b1
Signed-off-by: Abhinav Saurabh <quic_abhisaur@quicinc.com>
Add record in audio-routes for tuna7
where it is missing for record over AATC.
With this can record using AATC.
Change-Id: I9a76e16d5dc8168a11411ce715559350e6cc0c1f
Signed-off-by: Ravulapati Vishnu Vardhan Rao <quic_visr@quicinc.com>
(cherry picked from commit d2fe78d4a6)
Add parrot qfprom compatible string so that data can be
attached to it in the driver.
Change-Id: Ib69c0438446f6493d4a66c3453f1a878ccc0b10a
Signed-off-by: Saranya R <quic_sarar@quicinc.com>
GLINK changed their default handling of channel callbacks from the irq
context to a callback thread. This change impacted FastRPC performance.
Configure FastRPC to use irq context to handle channel callbacks to fix
the performance regression.
Change-Id: I59b2611e2ebe3f5d33650666a8ad7912d79cc1d1
Signed-off-by: Om Deore <quic_odeore@quicinc.com>
GLINK changed to using a non-RT priority when handling channel
callbacks.
For FastRPC configure GLINK to use RT priority when handling
channel callbacks to avoid any performance regression.
Change-Id: Ia1b0a105b79fb450d1fe3437ad88b3ce5d9fd943
Signed-off-by: Om Deore <quic_odeore@quicinc.com>
There is currently a potential for a deadlock in the DSP when it
wants to send a GLINK message but is waiting for an intent.
Increase the number of intents to 1 more than the number of DSP
supported threads so that the DSP won't have to wait for intents.
Change-Id: I31edbebe06738bb56a8305957fde74388c4a5154
Signed-off-by: Om Deore <quic_odeore@quicinc.com>
Reserve 16kb to dcc on TZ while HLOS have 16 KB.
Change-Id: I2063be0924b5719bd2c3abfffc84c0044d74ae37
Signed-off-by: Yingchao Deng <quic_yingdeng@quicinc.com>
Add bindings documentation for qcom,pmic-ecid. PMIC ECID provides the
PMIC specific information for identification.
Change-Id: I012670359ad1b1c4aea92f59b9430efc6e446f5f
Signed-off-by: Brindha T<quic_brint@quicinc.com>
Add devices to track CPU LPMs, SoC level LPMs, and system pm
violators.
Change-Id: I65a0dfeb814b47bdfcc4468ec8f1e7f63338581c
Signed-off-by: Sneh Mankad <quic_smankad@quicinc.com>
Update clk div factor entries for TX and VA macros to reflect
proper HW configuration.
Change-Id: Ic5456d7e30245a484b6a4888835c7e6f838eb92b
Signed-off-by: Ravulapati Vishnu Vardhan Rao <quic_visr@quicinc.com>
