Add 'qcom/audio/' from AUDIO_HANDSET.LA.10.0.r1-06600-pakala.0 of https://git.codelinaro.org/clo/la/platform/vendor/qcom/opensource/audio-devicetree
git-subtree-dir: qcom/audio git-subtree-mainline:573108dc30git-subtree-split:6c0f9e7566
This commit is contained in:
kmiit
63
qcom/audio/Kbuild
Normal file
63
qcom/audio/Kbuild
Normal file
@@ -0,0 +1,63 @@
|
||||
ifeq ($(CONFIG_ARCH_PINEAPPLE), y)
|
||||
dtbo-y += pineapple-audio.dtbo \
|
||||
pineapple-audio-cdp.dtbo \
|
||||
pineapple-audio-wsa883x-cdp.dtbo \
|
||||
pineapple-audio-cdp-nfc.dtbo \
|
||||
pineapple-audio-mtp.dtbo \
|
||||
pineapple-audio-mtp-nfc.dtbo \
|
||||
pineapple-audio-qrd.dtbo \
|
||||
pineapple-audio-atp.dtbo \
|
||||
pineapple-audio-rumi.dtbo \
|
||||
pineapple-audio-rcm.dtbo \
|
||||
pineapple-audio-qrd-sku2.dtbo \
|
||||
pineapplep-audio-hdk.dtbo
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_SUN), y)
|
||||
dtbo-y += sun-audio.dtbo \
|
||||
sun-audio-cdp.dtbo \
|
||||
sun-audio-cdp-nfc.dtbo \
|
||||
sun-audio-rumi.dtbo \
|
||||
sun-audio-mtp.dtbo \
|
||||
sun-audio-mtp-3.5mm.dtbo \
|
||||
sun-audio-mtp-nfc.dtbo \
|
||||
sun-audio-mtp-qmp.dtbo \
|
||||
sun-audio-qrd.dtbo \
|
||||
sun-audio-hdk.dtbo \
|
||||
sun-audio-qrd-sku2.dtbo \
|
||||
sun-audio-atp.dtbo \
|
||||
sun-audio-rcm.dtbo \
|
||||
sun-audio-hamilton-rcm.dtbo \
|
||||
sun-audio-hamilton-cdp.dtbo \
|
||||
sun-audio-hamilton-mtp-v2.dtbo \
|
||||
sun-audio-hamilton-mtp.dtbo \
|
||||
sun-audio-hamilton-mtp-3.5mm.dtbo \
|
||||
tuna-audio-atp.dtbo \
|
||||
tuna-audio.dtbo \
|
||||
tuna-audio-cdp.dtbo \
|
||||
tuna-audio-hamilton-mtp.dtbo \
|
||||
tuna-audio-hamilton-rcm.dtbo \
|
||||
tuna-audio-mtp.dtbo \
|
||||
tuna7-audio-mtp.dtbo \
|
||||
tuna-audio-mtp-qmp1000.dtbo \
|
||||
tuna-audio-qrd.dtbo \
|
||||
tuna-audio-rcm.dtbo
|
||||
endif
|
||||
|
||||
|
||||
ifeq ($(CONFIG_ARCH_KERA), y)
|
||||
dtbo-y += kera-audio.dtbo \
|
||||
kera-audio-atp.dtbo \
|
||||
kera-audio-cdp.dtbo \
|
||||
kera-iot-audio-cdp.dtbo \
|
||||
kera-audio-mtp.dtbo \
|
||||
kera-audio-mtp-qmp1000.dtbo \
|
||||
kera-audio-qrd.dtbo \
|
||||
kera-audio-rcm.dtbo \
|
||||
kera-audio-rcm-orne.dtbo
|
||||
|
||||
endif
|
||||
|
||||
always-y := $(dtb-y) $(dtbo-y)
|
||||
subdir-y := $(dts-dirs)
|
||||
clean-files := *.dtb *.dtbo
|
||||
19
qcom/audio/Makefile
Normal file
19
qcom/audio/Makefile
Normal file
@@ -0,0 +1,19 @@
|
||||
AUDIO_DEVICETREE_ROOT=$(KERNEL_SRC)/$(M)
|
||||
AUDIO_KERNEL_ROOT=$(AUDIO_DEVICETREE_ROOT)/../../opensource/audio-kernel/include
|
||||
|
||||
KBUILD_OPTIONS += KBUILD_DTC_INCLUDE=$(AUDIO_KERNEL_ROOT)
|
||||
KBUILD_OPTIONS += KBUILD_EXTMOD_DTS=.
|
||||
KBUILD_OPTIONS += KERNEL_ROOT=$(ROOT_DIR)/$(KERNEL_DIR)
|
||||
KBUILD_OPTIONS += MODNAME=audio-devicetree
|
||||
|
||||
|
||||
all: dtbs
|
||||
|
||||
dtbs:
|
||||
$(MAKE) -C $(KERNEL_SRC) M=$(M) dtbs $(KBUILD_OPTIONS)
|
||||
|
||||
modules_install:
|
||||
$(MAKE) M=$(M) -C $(KERNEL_SRC) modules_install
|
||||
|
||||
clean:
|
||||
$(MAKE) -C $(KERNEL_SRC) M=$(M) clean
|
||||
17
qcom/audio/kera-audio-atp.dts
Normal file
17
qcom/audio/kera-audio-atp.dts
Normal file
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "kera-audio-atp.dtsi"
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kera ATP";
|
||||
compatible = "qcom,kera-atp", "qcom,kera", "qcom,kerap-atp", "qcom,kerap",
|
||||
"qcom,atp";
|
||||
|
||||
qcom,msm-id = <686 0x10000>, <659 0x10000>;
|
||||
qcom,board-id = <33 0>;
|
||||
};
|
||||
63
qcom/audio/kera-audio-atp.dtsi
Normal file
63
qcom/audio/kera-audio-atp.dtsi
Normal file
@@ -0,0 +1,63 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "kera-audio-mtp.dtsi"
|
||||
|
||||
&lpass_bt_swr {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&kera_snd {
|
||||
qcom,wcn-btfm = <0>;
|
||||
qcom,ext-disp-audio-rx = <0>;
|
||||
qcom,wcd-disabled =<1>;
|
||||
qcom,audio-routing =
|
||||
"TX DMIC0", "Digital Mic0",
|
||||
"TX DMIC1", "Digital Mic1",
|
||||
"TX DMIC2", "Digital Mic2",
|
||||
"TX DMIC3", "Digital Mic3";
|
||||
qcom,wsa-max-devs = <0>;
|
||||
};
|
||||
|
||||
&swr0 {
|
||||
qcom,swr-num-dev = <0>;
|
||||
};
|
||||
|
||||
&wsa884x_0220 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wsa884x_0221 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wcd939x_codec {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wcd939x_rx_slave {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wcd939x_tx_slave {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wcd9378_codec {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wcd9378_rx_slave {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wcd9378_tx_slave {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wsa_macro {
|
||||
qcom,wsa-bat-cfgs= <4>, <4>;
|
||||
};
|
||||
|
||||
19
qcom/audio/kera-audio-cdp.dts
Normal file
19
qcom/audio/kera-audio-cdp.dts
Normal file
@@ -0,0 +1,19 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "kera-audio-cdp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kera CDP";
|
||||
compatible = "qcom,kera-cdp", "qcom,kera", "qcom,kerap-cdp", "qcom,kerap",
|
||||
"qcom,cdp";
|
||||
qcom,msm-id = <686 0x10000>, <659 0x10000>;
|
||||
qcom,board-id = <0x10001 0>, <0x20001 0>,
|
||||
<0x30001 0>, <0x40001 0>;
|
||||
};
|
||||
|
||||
144
qcom/audio/kera-audio-cdp.dtsi
Normal file
144
qcom/audio/kera-audio-cdp.dtsi
Normal file
@@ -0,0 +1,144 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "kera-audio-overlay.dtsi"
|
||||
#include "kera-audio-lpass-reg.dtsi"
|
||||
|
||||
&cdc_pri_mi2s_gpios {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&cdc_quat_mi2s_gpios {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cdc_quin_mi2s_gpios {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cdc_sen_mi2s_gpios {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cdc_sep_mi2s_gpios {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&lpass_bt_swr {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wcd9378_codec {
|
||||
status = "okay";
|
||||
cdc-vdd-io-supply = <&L7B>;
|
||||
qcom,cdc-vdd-io-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-io-current = <20000>;
|
||||
qcom,cdc-vdd-io-lpm-supported = <1>;
|
||||
|
||||
cdc-vdd-mic-bias-supply = <&BOB>;
|
||||
qcom,cdc-vdd-mic-bias-voltage = <3300000 3300000>;
|
||||
qcom,cdc-vdd-mic-bias-current = <40550>;
|
||||
};
|
||||
|
||||
&wcd939x_rx_slave {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wcd939x_tx_slave {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wcd9378_rx_slave {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wcd9378_tx_slave {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&swr0 {
|
||||
qcom,swr-num-dev = <2>;
|
||||
wsa884x_0220: wsa884x@02170220 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
wsa884x_0221: wsa884x@02170221 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&swr1 {
|
||||
qcom,swr-num-dev = <2>;
|
||||
};
|
||||
|
||||
&kera_snd {
|
||||
qcom,model = "kera-cdp-snd-card";
|
||||
swr-haptics-unsupported;
|
||||
qcom,audio-routing =
|
||||
"AMIC1", "Analog Mic1",
|
||||
"AMIC1", "MIC BIAS1",
|
||||
"AMIC2", "Analog Mic2",
|
||||
"AMIC2", "MIC BIAS2",
|
||||
"AMIC3", "Analog Mic3",
|
||||
"AMIC3", "MIC BIAS3",
|
||||
"AMIC4", "Analog Mic4",
|
||||
"VA AMIC1", "Analog Mic1",
|
||||
"VA AMIC1", "VA MIC BIAS1",
|
||||
"VA AMIC2", "Analog Mic2",
|
||||
"VA AMIC2", "VA MIC BIAS2",
|
||||
"VA AMIC3", "Analog Mic3",
|
||||
"VA AMIC3", "VA MIC BIAS3",
|
||||
"VA AMIC4", "Analog Mic4",
|
||||
"TX DMIC0", "Digital Mic0",
|
||||
"TX DMIC0", "MIC BIAS3",
|
||||
"TX DMIC1", "Digital Mic1",
|
||||
"TX DMIC1", "MIC BIAS3",
|
||||
"TX DMIC2", "Digital Mic2",
|
||||
"TX DMIC2", "MIC BIAS1",
|
||||
"TX DMIC3", "Digital Mic3",
|
||||
"TX DMIC3", "MIC BIAS1",
|
||||
"IN1_HPHL", "HPHL_OUT",
|
||||
"IN2_HPHR", "HPHR_OUT",
|
||||
"IN3_AUX", "AUX_OUT",
|
||||
"WSA SRC0_INP", "SRC0",
|
||||
"WSA_TX DEC0_INP", "TX DEC0 MUX",
|
||||
"WSA_TX DEC1_INP", "TX DEC1 MUX",
|
||||
"RX_TX DEC0_INP", "TX DEC0 MUX",
|
||||
"RX_TX DEC1_INP", "TX DEC1 MUX",
|
||||
"RX_TX DEC2_INP", "TX DEC2 MUX",
|
||||
"RX_TX DEC3_INP", "TX DEC3 MUX",
|
||||
"SpkrLeft IN", "WSA_SPK1 OUT",
|
||||
"SpkrRight IN", "WSA_SPK2 OUT",
|
||||
"VA SWR_INPUT", "VA_SWR_CLK",
|
||||
"VA_AIF1 CAP", "VA_SWR_CLK",
|
||||
"VA_AIF2 CAP", "VA_SWR_CLK",
|
||||
"VA_AIF3 CAP", "VA_SWR_CLK",
|
||||
"VA DMIC0", "Digital Mic0",
|
||||
"VA DMIC1", "Digital Mic1",
|
||||
"VA DMIC2", "Digital Mic2",
|
||||
"VA DMIC3", "Digital Mic3",
|
||||
"VA DMIC0", "VA MIC BIAS3",
|
||||
"VA DMIC1", "VA MIC BIAS3",
|
||||
"VA DMIC2", "VA MIC BIAS1",
|
||||
"VA DMIC3", "VA MIC BIAS1";
|
||||
asoc-codec = <&stub_codec>, <&lpass_cdc>,
|
||||
<&wcd9378_codec>,
|
||||
<&wsa884x_0220>, <&wsa884x_0221>;
|
||||
asoc-codec-names = "msm-stub-codec.1", "lpass-cdc",
|
||||
"wcd9378_codec",
|
||||
"wsa-codec1", "wsa-codec2";
|
||||
qcom,msm_audio_ssr_devs = <&audio_gpr>, <&lpi_tlmm>,
|
||||
<&lpass_cdc>;
|
||||
qcom,wsa-max-devs = <2>;
|
||||
qcom,pri-mi2s-gpios = <&cdc_pri_mi2s_gpios>;
|
||||
qcom,quat-mi2s-gpios = <&cdc_quat_mi2s_gpios>;
|
||||
qcom,quin-mi2s-gpios = <&cdc_quin_mi2s_gpios>;
|
||||
qcom,sen-mi2s-gpios = <&cdc_sen_mi2s_gpios>;
|
||||
qcom,sep-mi2s-gpios = <&cdc_sep_mi2s_gpios>;
|
||||
qcom,msm-mbhc-usbc-audio-supported = <0>;
|
||||
qcom,msm-mbhc-hphl-swh = <1>;
|
||||
qcom,msm-mbhc-gnd-swh = <1>;
|
||||
qcom,msm-mbhc-hs-mic-max-threshold-mv = <1680>;
|
||||
};
|
||||
33
qcom/audio/kera-audio-lpass-reg.dtsi
Normal file
33
qcom/audio/kera-audio-lpass-reg.dtsi
Normal file
@@ -0,0 +1,33 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
&rx_macro {
|
||||
reg = <0x6AC0000 0x0>;
|
||||
};
|
||||
|
||||
&swr1 {
|
||||
swrm-io-base = <0x6AD0000 0x0>;
|
||||
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&tx_macro {
|
||||
reg = <0x6AE0000 0x0>;
|
||||
};
|
||||
|
||||
&wsa_macro {
|
||||
reg = <0x6B00000 0x0>;
|
||||
};
|
||||
|
||||
&swr0 {
|
||||
swrm-io-base = <0x6B10000 0x0>;
|
||||
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&swr2 {
|
||||
swrm-io-base = <0x7630000 0x0>;
|
||||
};
|
||||
|
||||
&va_macro {
|
||||
reg = <0x7660000 0x0>;
|
||||
};
|
||||
18
qcom/audio/kera-audio-mtp-qmp1000.dts
Normal file
18
qcom/audio/kera-audio-mtp-qmp1000.dts
Normal file
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "kera-audio-mtp-qmp1000.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kera MTP QMP1000";
|
||||
compatible = "qcom,kera-mtp", "qcom,kera", "qcom,kerap-mtp", "qcom,kerap",
|
||||
"qcom,mtp";
|
||||
qcom,msm-id = <686 0x10000>, <659 0x10000>;
|
||||
qcom,board-id = <0x30008 0>, <0x30008 1>;
|
||||
};
|
||||
|
||||
163
qcom/audio/kera-audio-mtp-qmp1000.dtsi
Normal file
163
qcom/audio/kera-audio-mtp-qmp1000.dtsi
Normal file
@@ -0,0 +1,163 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "kera-audio-mtp.dtsi"
|
||||
|
||||
|
||||
&swr2 {
|
||||
qmp01: qmp@04170232 {
|
||||
/*
|
||||
* reg = <Class_partID[7:0]
|
||||
* partID[15:8] manuID[7:0] manuID[15:8](version4bits_UniqueID4bits)
|
||||
*/
|
||||
reg = <0x0100 0x04170232>;
|
||||
compatible = "qcom,qmp-sdca-dmic";
|
||||
sound-name-prefix = "QMP_MIC01";
|
||||
qcom,codec-name = "qmp-dmic.01";
|
||||
qmp-vdd-supply = <&wcd_mb3_reg>;
|
||||
qcom,swr-tx-port-params =
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL2 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL2 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL2 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL2 LANE0>;
|
||||
reg-values = <0x401805B0 0x5
|
||||
0x401805B1 0x5
|
||||
0x401805B2 0x5
|
||||
0x401805B3 0x5
|
||||
0x401805B8 0x5>;
|
||||
};
|
||||
|
||||
qmp02: qmp@04170236 {
|
||||
reg = <0x0100 0x04170236>;
|
||||
compatible = "qcom,qmp-sdca-dmic";
|
||||
sound-name-prefix = "QMP_MIC02";
|
||||
qcom,codec-name = "qmp-dmic.02";
|
||||
qmp-vdd-supply = <&wcd_mb3_reg>;
|
||||
qcom,swr-tx-port-params =
|
||||
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>,
|
||||
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>,
|
||||
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>,
|
||||
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>;
|
||||
reg-values = <0x401805B0 0x5
|
||||
0x401805B1 0x5
|
||||
0x401805B2 0x5
|
||||
0x401805B3 0x5
|
||||
0x401805B8 0x5>;
|
||||
};
|
||||
|
||||
qmp03: qmp@04170230 {
|
||||
reg = <0x0100 0x04170230>;
|
||||
compatible = "qcom,qmp-sdca-dmic";
|
||||
sound-name-prefix = "QMP_MIC03";
|
||||
qcom,codec-name = "qmp-dmic.03";
|
||||
qmp-vdd-supply = <&wcd_mb1_reg>;
|
||||
qcom,swr-tx-port-params =
|
||||
<OFFSET1_VAL3 LANE0>, <OFFSET1_VAL2 LANE0>,
|
||||
<OFFSET1_VAL3 LANE0>, <OFFSET1_VAL2 LANE0>,
|
||||
<OFFSET1_VAL3 LANE0>, <OFFSET1_VAL2 LANE0>,
|
||||
<OFFSET1_VAL3 LANE0>, <OFFSET1_VAL2 LANE0>;
|
||||
reg-values = <0x401805B0 0x5
|
||||
0x401805B1 0x5
|
||||
0x401805B2 0x5
|
||||
0x401805B3 0x5
|
||||
0x401805B8 0x5>;
|
||||
};
|
||||
|
||||
qmp04: qmp@04170239 {
|
||||
reg = <0x0100 0x04170239>;
|
||||
compatible = "qcom,qmp-sdca-dmic";
|
||||
sound-name-prefix = "QMP_MIC04";
|
||||
qcom,codec-name = "qmp-dmic.04";
|
||||
qmp-vdd-supply = <&wcd_mb1_reg>;
|
||||
qcom,swr-tx-port-params =
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL2 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL2 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL2 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL2 LANE0>;
|
||||
reg-values = <0x401805B0 0x5
|
||||
0x401805B1 0x5
|
||||
0x401805B2 0x5
|
||||
0x401805B3 0x5
|
||||
0x401805B8 0x5>;
|
||||
};
|
||||
};
|
||||
|
||||
&kera_snd {
|
||||
qcom,model = "kera-mtp-qmp-snd-card";
|
||||
asoc-codec = <&stub_codec>, <&lpass_cdc>,
|
||||
<&wcd939x_codec>,
|
||||
<&wsa884x_0220>, <&wsa884x_0221>,
|
||||
<&qmp01>, <&qmp02>,
|
||||
<&qmp03>, <&qmp04>;
|
||||
asoc-codec-names = "msm-stub-codec.1", "lpass-cdc",
|
||||
"wcd939x_codec",
|
||||
"wsa-codec1", "wsa-codec2",
|
||||
"qmp-dmic.01", "qmp-dmic.02",
|
||||
"qmp-dmic.03", "qmp-dmic.04";
|
||||
qcom,qmp-mic = <1>;
|
||||
qcom,audio-routing =
|
||||
"AMIC1", "Analog Mic1",
|
||||
"AMIC1", "MIC BIAS1",
|
||||
"AMIC2", "Analog Mic2",
|
||||
"AMIC2", "MIC BIAS2",
|
||||
"AMIC3", "Analog Mic3",
|
||||
"AMIC3", "MIC BIAS3",
|
||||
"AMIC4", "Analog Mic4",
|
||||
"AMIC4", "MIC BIAS1",
|
||||
"VA AMIC1", "Analog Mic1",
|
||||
"VA AMIC1", "VA MIC BIAS1",
|
||||
"VA AMIC2", "Analog Mic2",
|
||||
"VA AMIC2", "VA MIC BIAS2",
|
||||
"VA AMIC3", "Analog Mic3",
|
||||
"VA AMIC3", "VA MIC BIAS3",
|
||||
"VA AMIC4", "Analog Mic4",
|
||||
"VA AMIC4", "VA MIC BIAS1",
|
||||
"TX DMIC0", "Digital Mic0",
|
||||
"TX DMIC0", "MIC BIAS3",
|
||||
"TX DMIC1", "Digital Mic1",
|
||||
"TX DMIC1", "MIC BIAS3",
|
||||
"TX DMIC2", "Digital Mic2",
|
||||
"TX DMIC2", "MIC BIAS1",
|
||||
"TX DMIC3", "Digital Mic3",
|
||||
"TX DMIC3", "MIC BIAS1",
|
||||
"IN1_HPHL", "HPHL_OUT",
|
||||
"IN2_HPHR", "HPHR_OUT",
|
||||
"IN3_AUX", "AUX_OUT",
|
||||
"WSA SRC0_INP", "SRC0",
|
||||
"WSA_TX DEC0_INP", "TX DEC0 MUX",
|
||||
"WSA_TX DEC1_INP", "TX DEC1 MUX",
|
||||
"RX_TX DEC0_INP", "TX DEC0 MUX",
|
||||
"RX_TX DEC1_INP", "TX DEC1 MUX",
|
||||
"RX_TX DEC2_INP", "TX DEC2 MUX",
|
||||
"RX_TX DEC3_INP", "TX DEC3 MUX",
|
||||
"SpkrLeft IN", "WSA_SPK1 OUT",
|
||||
"SpkrRight IN", "WSA_SPK2 OUT",
|
||||
"TX SWR_INPUT", "WCD_TX_OUTPUT",
|
||||
"TX SWR_INPUT", "QMP_MIC01 NORMAL_OUTPUT",
|
||||
"TX SWR_INPUT", "QMP_MIC02 NORMAL_OUTPUT",
|
||||
"TX SWR_INPUT", "QMP_MIC03 NORMAL_OUTPUT",
|
||||
"TX SWR_INPUT", "QMP_MIC04 NORMAL_OUTPUT",
|
||||
"VA SWR_INPUT", "VA_SWR_CLK",
|
||||
"VA SWR_INPUT", "WCD_TX_OUTPUT",
|
||||
"VA SWR_INPUT", "QMP_MIC01 LP_OUTPUT",
|
||||
"VA SWR_INPUT", "QMP_MIC02 LP_OUTPUT",
|
||||
"VA SWR_INPUT", "QMP_MIC03 LP_OUTPUT",
|
||||
"VA SWR_INPUT", "QMP_MIC04 LP_OUTPUT",
|
||||
"VA SWR_INPUT", "QMP_MIC01 VA_NORMAL_OUTPUT",
|
||||
"VA SWR_INPUT", "QMP_MIC02 VA_NORMAL_OUTPUT",
|
||||
"VA SWR_INPUT", "QMP_MIC03 VA_NORMAL_OUTPUT",
|
||||
"VA SWR_INPUT", "QMP_MIC04 VA_NORMAL_OUTPUT",
|
||||
"VA_AIF1 CAP", "VA_SWR_CLK",
|
||||
"VA_AIF2 CAP", "VA_SWR_CLK",
|
||||
"VA_AIF3 CAP", "VA_SWR_CLK",
|
||||
"VA DMIC0", "Digital Mic0",
|
||||
"VA DMIC1", "Digital Mic1",
|
||||
"VA DMIC2", "Digital Mic2",
|
||||
"VA DMIC3", "Digital Mic3",
|
||||
"VA DMIC0", "VA MIC BIAS3",
|
||||
"VA DMIC1", "VA MIC BIAS3",
|
||||
"VA DMIC2", "VA MIC BIAS1",
|
||||
"VA DMIC3", "VA MIC BIAS1";
|
||||
};
|
||||
18
qcom/audio/kera-audio-mtp.dts
Normal file
18
qcom/audio/kera-audio-mtp.dts
Normal file
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "kera-audio-mtp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kera MTP";
|
||||
compatible = "qcom,kera-mtp", "qcom,kera", "qcom,kerap-mtp", "qcom,kerap",
|
||||
"qcom,mtp";
|
||||
qcom,msm-id = <686 0x10000>, <659 0x10000>;
|
||||
qcom,board-id = <0x10008 0>, <0x20008 0>, <0x10008 1>, <0x20008 1>;
|
||||
};
|
||||
|
||||
167
qcom/audio/kera-audio-mtp.dtsi
Normal file
167
qcom/audio/kera-audio-mtp.dtsi
Normal file
@@ -0,0 +1,167 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "kera-audio-overlay.dtsi"
|
||||
#include "kera-audio-lpass-reg.dtsi"
|
||||
|
||||
&tx_swr_clk_active {
|
||||
config {
|
||||
drive-strength = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&tx_swr_data0_active {
|
||||
config {
|
||||
drive-strength = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&tx_swr_data1_active {
|
||||
config {
|
||||
drive-strength = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&tx_swr_data2_active {
|
||||
config {
|
||||
drive-strength = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&cdc_pri_mi2s_gpios {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&swr1 {
|
||||
qcom,swr-num-dev = <2>;
|
||||
};
|
||||
|
||||
&swr0 {
|
||||
qcom,swr-num-dev = <2>;
|
||||
};
|
||||
|
||||
&wsa884x_0220 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wsa884x_0221 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wcd9378_rx_slave {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wcd9378_tx_slave {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wcd9378_codec {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&lpass_bt_swr {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wcd939x_rx_slave {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wcd939x_tx_slave {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wcd939x_codec {
|
||||
status = "okay";
|
||||
/* 0 for digital crosstalk disabled,
|
||||
* 1 for digital crosstalk with local sensed a-xtalk enabled, and
|
||||
* 2 for digital crosstalk with remote sensed a-xtalk enabled.
|
||||
*/
|
||||
qcom,usbcss-hs-xtalk-config = <0>;
|
||||
qcom,usbcss-hs-rdson = <600>;
|
||||
qcom,usbcss-hs-r2 = <7550>;
|
||||
qcom,usbcss-hs-r3 = <1>;
|
||||
qcom,usbcss-hs-r4 = <330>;
|
||||
qcom,usbcss-hs-r5 = <5>;
|
||||
qcom,usbcss-hs-r6 = <1>;
|
||||
qcom,usbcss-hs-r7 = <5>;
|
||||
qcom,usbcss-hs-lin-k-aud = <13>;
|
||||
qcom,usbcss-hs-lin-k-gnd = <13>;
|
||||
};
|
||||
|
||||
|
||||
&kera_snd {
|
||||
qcom,model = "kera-mtp-snd-card";
|
||||
qcom,audio-routing =
|
||||
"AMIC1", "Analog Mic1",
|
||||
"AMIC1", "MIC BIAS1",
|
||||
"AMIC2", "Analog Mic2",
|
||||
"AMIC2", "MIC BIAS2",
|
||||
"AMIC3", "Analog Mic3",
|
||||
"AMIC3", "MIC BIAS3",
|
||||
"AMIC4", "Analog Mic4",
|
||||
"AMIC4", "MIC BIAS1",
|
||||
"VA AMIC1", "Analog Mic1",
|
||||
"VA AMIC1", "VA MIC BIAS1",
|
||||
"VA AMIC2", "Analog Mic2",
|
||||
"VA AMIC2", "VA MIC BIAS2",
|
||||
"VA AMIC3", "Analog Mic3",
|
||||
"VA AMIC3", "VA MIC BIAS3",
|
||||
"VA AMIC4", "Analog Mic4",
|
||||
"VA AMIC4", "VA MIC BIAS1",
|
||||
"TX DMIC0", "Digital Mic0",
|
||||
"TX DMIC0", "MIC BIAS3",
|
||||
"TX DMIC1", "Digital Mic1",
|
||||
"TX DMIC1", "MIC BIAS3",
|
||||
"TX DMIC2", "Digital Mic2",
|
||||
"TX DMIC2", "MIC BIAS1",
|
||||
"TX DMIC3", "Digital Mic3",
|
||||
"TX DMIC3", "MIC BIAS1",
|
||||
"IN1_HPHL", "HPHL_OUT",
|
||||
"IN2_HPHR", "HPHR_OUT",
|
||||
"IN3_EAR", "AUX_OUT",
|
||||
"WSA SRC0_INP", "SRC0",
|
||||
"WSA_TX DEC0_INP", "TX DEC0 MUX",
|
||||
"WSA_TX DEC1_INP", "TX DEC1 MUX",
|
||||
"RX_TX DEC0_INP", "TX DEC0 MUX",
|
||||
"RX_TX DEC1_INP", "TX DEC1 MUX",
|
||||
"RX_TX DEC2_INP", "TX DEC2 MUX",
|
||||
"RX_TX DEC3_INP", "TX DEC3 MUX",
|
||||
"SpkrLeft IN", "WSA_SPK1 OUT",
|
||||
"SpkrRight IN", "WSA_SPK2 OUT",
|
||||
"TX SWR_INPUT", "WCD_TX_OUTPUT",
|
||||
"VA SWR_INPUT", "WCD_TX_OUTPUT",
|
||||
"VA SWR_INPUT", "VA_SWR_CLK",
|
||||
"VA_AIF1 CAP", "VA_SWR_CLK",
|
||||
"VA_AIF2 CAP", "VA_SWR_CLK",
|
||||
"VA_AIF3 CAP", "VA_SWR_CLK",
|
||||
"VA DMIC0", "Digital Mic0",
|
||||
"VA DMIC1", "Digital Mic1",
|
||||
"VA DMIC2", "Digital Mic2",
|
||||
"VA DMIC3", "Digital Mic3",
|
||||
"VA DMIC0", "VA MIC BIAS3",
|
||||
"VA DMIC1", "VA MIC BIAS3",
|
||||
"VA DMIC2", "VA MIC BIAS1",
|
||||
"VA DMIC3", "VA MIC BIAS1";
|
||||
qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>;
|
||||
qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>;
|
||||
qcom,msm_audio_ssr_devs = <&audio_gpr>, <&lpi_tlmm>,
|
||||
<&lpass_cdc>;
|
||||
asoc-codec = <&stub_codec>, <&lpass_cdc>,
|
||||
<&wcd939x_codec>, <&wsa884x_0220>,
|
||||
<&wsa884x_0221>;
|
||||
asoc-codec-names = "msm-stub-codec.1", "lpass-cdc",
|
||||
"wcd939x_codec", "wsa-codec1",
|
||||
"wsa-codec2";
|
||||
qcom,wsa-max-devs = <2>;
|
||||
qcom,pri-mi2s-gpios = <&cdc_pri_mi2s_gpios>;
|
||||
qcom,wcd-disable-legacy-surge;
|
||||
wcd939x-i2c-handle = <&wcd_usbss>;
|
||||
qcom,msm-mbhc-usbc-audio-supported = <0>;
|
||||
qcom,msm-mbhc-hphl-swh = <1>;
|
||||
qcom,msm-mbhc-gnd-swh = <1>;
|
||||
qcom,msm-mbhc-hs-mic-max-threshold-mv = <1670>;
|
||||
};
|
||||
763
qcom/audio/kera-audio-overlay.dtsi
Normal file
763
qcom/audio/kera-audio-overlay.dtsi
Normal file
@@ -0,0 +1,763 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <bindings/qcom,audio-ext-clk.h>
|
||||
#include <bindings/qcom,lpass-cdc-clk-rsc.h>
|
||||
#include <bindings/audio-codec-port-types.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include "kera-lpi.dtsi"
|
||||
|
||||
&lpass_cdc {
|
||||
qcom,num-macros = <4>;
|
||||
qcom,lpass-cdc-version = <7>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
lpass-cdc-clk-rsc-mngr {
|
||||
compatible = "qcom,lpass-cdc-clk-rsc-mngr";
|
||||
qcom,fs-gen-sequence = <0x3000 0x1 0x1>, <0x3004 0x3 0x3>,
|
||||
<0x3004 0x3 0x1>, <0x3080 0x2 0x2>;
|
||||
qcom,rx_mclk_mode_muxsel = <0x06BEC0D8>;
|
||||
qcom,wsa_mclk_mode_muxsel = <0x06BEA110>;
|
||||
clock-names = "tx_core_clk", "rx_core_clk", "wsa_core_clk",
|
||||
"rx_tx_core_clk", "wsa_tx_core_clk", "va_core_clk";
|
||||
clocks = <&clock_audio_tx_1 0>, <&clock_audio_rx_1 0>,
|
||||
<&clock_audio_wsa_1 0>, <&clock_audio_rx_tx 0>,
|
||||
<&clock_audio_wsa_tx 0>, <&clock_audio_va_1 0>;
|
||||
};
|
||||
|
||||
va_macro: va-macro@7660000 {
|
||||
compatible = "qcom,lpass-cdc-va-macro";
|
||||
clock-names = "lpass_audio_hw_vote";
|
||||
clocks = <&lpass_audio_hw_vote 0>;
|
||||
qcom,va-clk-mux-select = <1>;
|
||||
/*
|
||||
* Clk divding factors for each DMIC pair.
|
||||
* Valid entries for each DMIC pair:
|
||||
* 2, 3, 4, 6, 8, 16
|
||||
*
|
||||
* These factors are translated to corresponding config values
|
||||
* for the following registers,
|
||||
* -- LPASS_VA_TOP_CSR_DMIC0_CTL,
|
||||
* -- LPASS_VA_TOP_CSR_DMIC1_CTL,
|
||||
* -- LPASS_VA_TOP_CSR_DMIC2_CTL,
|
||||
* -- LPASS_VA_TOP_CSR_DMIC3_CTL,
|
||||
*/
|
||||
qcom,va-dmic-clk-div-factor = <16 16 16 16>;
|
||||
qcom,default-clk-id = <TX_CORE_CLK>;
|
||||
qcom,use-clk-id = <VA_CORE_CLK>;
|
||||
qcom,is-used-swr-gpio = <1>;
|
||||
qcom,va-swr-gpios = <&va_swr_gpios>;
|
||||
swr2: va_swr_master {
|
||||
compatible = "qcom,swr-mstr";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "lpass_core_hw_vote",
|
||||
"lpass_audio_hw_vote";
|
||||
clocks = <&lpass_core_hw_vote 0>,
|
||||
<&lpass_audio_hw_vote 0>;
|
||||
qcom,swr_master_id = <3>;
|
||||
qcom,mipi-sdw-block-packing-mode = <1>;
|
||||
interrupts =
|
||||
<GIC_SPI 721 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "swr_master_irq", "swr_wake_irq";
|
||||
qcom,swr-wakeup-required = <1>;
|
||||
qcom,swr-num-ports = <5>;
|
||||
qcom,swr-port-mapping = <1 SWRM_TX_PCM_OUT 0x3>,
|
||||
<2 SWRM_TX1_CH1 0x1>, <2 SWRM_TX1_CH2 0x2>,
|
||||
<2 SWRM_TX1_CH3 0x4>, <2 SWRM_TX1_CH4 0x8>,
|
||||
<3 SWRM_TX2_CH1 0x1>, <3 SWRM_TX2_CH2 0x2>,
|
||||
<3 SWRM_TX2_CH3 0x4>, <3 SWRM_TX2_CH4 0x8>,
|
||||
<4 SWRM_TX3_CH1 0x1>, <4 SWRM_TX3_CH2 0x2>,
|
||||
<4 SWRM_TX3_CH3 0x4>, <4 SWRM_TX3_CH4 0x8>,
|
||||
<5 SWRM_TX_PCM_IN 0x3>;
|
||||
qcom,swr-num-dev = <5>;
|
||||
qcom,swr-clock-stop-mode0 = <1>;
|
||||
qcom,swr-mstr-irq-wakeup-capable = <1>;
|
||||
qcom,is-always-on = <1>;
|
||||
wcd9378_tx_slave: wcd9378-tx-slave {
|
||||
compatible = "qcom,wcd9378-slave";
|
||||
reg = <0x10 0x01170223>;
|
||||
};
|
||||
|
||||
wcd939x_tx_slave: wcd939x-tx-slave {
|
||||
status = "disabled";
|
||||
compatible = "qcom,wcd939x-slave";
|
||||
reg = <0x0E 0x01170223>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tx_macro: tx-macro@6AE0000 {
|
||||
compatible = "qcom,lpass-cdc-tx-macro";
|
||||
qcom,default-clk-id = <TX_CORE_CLK>;
|
||||
/*
|
||||
* Clk divding factors for each DMIC pair.
|
||||
* Valid entries for each DMIC pair:
|
||||
* 2, 3, 4, 6, 8, 16
|
||||
*
|
||||
* These factors are translated to corresponding config values
|
||||
* for the following registers,
|
||||
* -- LPASS_VA_TOP_CSR_DMIC0_CTL,
|
||||
* -- LPASS_VA_TOP_CSR_DMIC1_CTL,
|
||||
* -- LPASS_VA_TOP_CSR_DMIC2_CTL,
|
||||
* -- LPASS_VA_TOP_CSR_DMIC3_CTL,
|
||||
*/
|
||||
qcom,tx-dmic-clk-div-factor = <4 4 4 4>;
|
||||
qcom,is-used-swr-gpio = <0>;
|
||||
};
|
||||
|
||||
rx_macro: rx-macro@6AC0000 {
|
||||
compatible = "qcom,lpass-cdc-rx-macro";
|
||||
qcom,rx-swr-gpios = <&rx_swr_gpios>;
|
||||
qcom,rx_mclk_mode_muxsel = <0x06BEC0D8>;
|
||||
qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x03 0x48>;
|
||||
qcom,default-clk-id = <RX_TX_CORE_CLK>;
|
||||
clock-names = "rx_mclk2_2x_clk";
|
||||
clocks = <&clock_audio_rx_mclk2_2x_clk 0>;
|
||||
swr1: rx_swr_master {
|
||||
compatible = "qcom,swr-mstr";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "lpass_core_hw_vote",
|
||||
"lpass_audio_hw_vote";
|
||||
clocks = <&lpass_core_hw_vote 0>,
|
||||
<&lpass_audio_hw_vote 0>;
|
||||
qcom,swr_master_id = <2>;
|
||||
qcom,mipi-sdw-block-packing-mode = <1>;
|
||||
interrupt-names = "swr_master_irq";
|
||||
qcom,swr-num-ports = <12>;
|
||||
qcom,swr-port-mapping = <1 HPH_L 0x1>,
|
||||
<1 HPH_R 0x2>, <2 CLSH 0x3>,
|
||||
<3 COMP_L 0x1>, <3 COMP_R 0x2>,
|
||||
<4 LO 0x1>, <5 DSD_L 0x1>,
|
||||
<5 DSD_R 0x2>, <6 PCM_OUT1 0x01>,
|
||||
<7 GPPO 0x03>, <8 HAPT 0x03>,
|
||||
<9 HIFI_PCM_L 0x01>, <9 HIFI_PCM_R 0x2>,
|
||||
<10 HPTH 0x03>, <11 CMPT 0x03>, <12 IPCM 0x03>;
|
||||
|
||||
/* num-dev is 2 if WCD RX and PMIC SWR Slaves are connected */
|
||||
/* num-dev is 1 if only WCD RX slave is connected */
|
||||
qcom,swr-num-dev = <1>;
|
||||
qcom,swr-clock-stop-mode0 = <1>;
|
||||
swr_haptics: swr_haptics@f0170220 {
|
||||
compatible = "qcom,pmih010x-swr-haptics";
|
||||
reg = <0x03 0xf0170220>;
|
||||
//swr-slave-supply = <&hap_swr_slave_reg>;
|
||||
qcom,rx_swr_ch_map = <0 0x01 0x01 0 PCM_OUT1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wcd9378_rx_slave: wcd9378-rx-slave {
|
||||
compatible = "qcom,wcd9378-slave";
|
||||
reg = <0x10 0x01170224>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
wcd939x_rx_slave: wcd939x-rx-slave {
|
||||
compatible = "qcom,wcd939x-slave";
|
||||
reg = <0x0E 0x01170224>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
wsa_macro: wsa-macro@6B00000 {
|
||||
compatible = "qcom,lpass-cdc-wsa-macro";
|
||||
wsa_data_fs_ctl_reg = <0x6B6F000>;
|
||||
qcom,wsa-swr-gpios = <&wsa_swr_gpios>;
|
||||
qcom,wsa-bat-cfgs= <1>, <1>;
|
||||
qcom,wsa-rloads= <2>, <2>;
|
||||
qcom,wsa-system-gains= <0 9>, <0 9>;
|
||||
qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x03 0x48>;
|
||||
qcom,default-clk-id = <WSA_TX_CORE_CLK>;
|
||||
qcom,thermal-max-state = <11>;
|
||||
qcom,noise-gate-mode = <2>;
|
||||
#cooling-cells = <2>;
|
||||
swr0: wsa_swr_master {
|
||||
compatible = "qcom,swr-mstr";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "lpass_core_hw_vote",
|
||||
"lpass_audio_hw_vote";
|
||||
clocks = <&lpass_core_hw_vote 0>,
|
||||
<&lpass_audio_hw_vote 0>;
|
||||
qcom,swr_master_id = <1>;
|
||||
qcom,mipi-sdw-block-packing-mode = <0>;
|
||||
interrupt-names = "swr_master_irq";
|
||||
qcom,swr-num-ports = <13>;
|
||||
qcom,swr-clock-stop-mode0 = <1>;
|
||||
qcom,swr-port-mapping = <1 SPKR_L 0x1>,
|
||||
<2 SPKR_L_COMP 0xF>, <3 SPKR_L_BOOST 0x3>,
|
||||
<4 SPKR_R 0x1>, <5 SPKR_R_COMP 0xF>,
|
||||
<6 SPKR_R_BOOST 0x3>, <7 PBR 0x3>,
|
||||
<8 SPKR_HAPT 0x3>, <9 OCPM 0x3>,
|
||||
<10 SPKR_L_VI 0x3>, <11 SPKR_R_VI 0x3>,
|
||||
<12 SPKR_IPCM 0x3>, <13 CPS 0x3>;
|
||||
qcom,swr-num-dev = <1>;
|
||||
qcom,dynamic-port-map-supported = <0>;
|
||||
wsa884x_0220: wsa884x@02170220 {
|
||||
compatible = "qcom,wsa884x";
|
||||
status = "disabled";
|
||||
reg = <0x4 0x2170220>;
|
||||
qcom,spkr-sd-n-node = <&wsa_spkr_en02>;
|
||||
qcom,lpass-cdc-handle = <&lpass_cdc>;
|
||||
qcom,wsa-macro-handle = <&wsa_macro>;
|
||||
qcom,swr-wsa-port-params =
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>,
|
||||
<OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>,
|
||||
<OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>,
|
||||
<OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>,
|
||||
<OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>,
|
||||
<OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>,
|
||||
<OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>,
|
||||
<OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>,
|
||||
<OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>;
|
||||
cdc-vdd-1p8-supply = <&L7B>;
|
||||
qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-1p8-current = <20000>;
|
||||
qcom,cdc-vdd-1p8-lpm-supported = <1>;
|
||||
qcom,cdc-static-supplies = "cdc-vdd-1p8";
|
||||
sound-name-prefix = "SpkrLeft";
|
||||
};
|
||||
|
||||
wsa884x_0221: wsa884x@02170221 {
|
||||
compatible = "qcom,wsa884x";
|
||||
reg = <0x4 0x2170221>;
|
||||
qcom,spkr-sd-n-node = <&wsa_spkr_en13>;
|
||||
qcom,lpass-cdc-handle = <&lpass_cdc>;
|
||||
qcom,wsa-macro-handle = <&wsa_macro>;
|
||||
qcom,swr-wsa-port-params =
|
||||
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>,
|
||||
<OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>,
|
||||
<OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>,
|
||||
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>,
|
||||
<OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>,
|
||||
<OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>,
|
||||
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>,
|
||||
<OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>,
|
||||
<OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>,
|
||||
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>,
|
||||
<OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>,
|
||||
<OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>;
|
||||
cdc-vdd-1p8-supply = <&L7B>;
|
||||
qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-1p8-current = <20000>;
|
||||
qcom,cdc-vdd-1p8-lpm-supported = <1>;
|
||||
qcom,cdc-static-supplies = "cdc-vdd-1p8";
|
||||
sound-name-prefix = "SpkrRight";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
wcd939x_codec: wcd939x-codec {
|
||||
compatible = "qcom,wcd939x-codec";
|
||||
status = "disabled";
|
||||
qcom,split-codec = <1>;
|
||||
qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
|
||||
<0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>,
|
||||
<2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
|
||||
<3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
|
||||
<4 DSD_R 0x2 0 DSD_R>, <5 HIFI_PCM_L 0x1 0 HIFI_PCM_L>,
|
||||
<5 HIFI_PCM_R 0x2 0 HIFI_PCM_R>;
|
||||
|
||||
qcom,tx_swr_ch_map = <0 ADC1 0x1 0 SWRM_TX1_CH1>,
|
||||
<0 ADC2 0x2 0 SWRM_TX1_CH2>,
|
||||
<1 ADC3 0x1 0 SWRM_TX1_CH3>,
|
||||
<1 ADC4 0x2 0 SWRM_TX1_CH4>,
|
||||
<2 DMIC0 0x1 0 SWRM_TX2_CH1>,
|
||||
<2 DMIC1 0x2 0 SWRM_TX2_CH2>,
|
||||
<2 MBHC 0x4 0 SWRM_TX2_CH3>,
|
||||
<2 DMIC2 0x4 0 SWRM_TX2_CH3>,
|
||||
<2 DMIC3 0x8 0 SWRM_TX2_CH4>,
|
||||
<3 DMIC4 0x1 0 SWRM_TX3_CH1>,
|
||||
<3 DMIC5 0x2 0 SWRM_TX3_CH2>,
|
||||
<3 DMIC6 0x4 0 SWRM_TX3_CH3>,
|
||||
<3 DMIC7 0x8 0 SWRM_TX3_CH4>;
|
||||
|
||||
qcom,swr-tx-port-params =
|
||||
<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL0 LANE2>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,
|
||||
<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL1 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,
|
||||
<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL2 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL2 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>;
|
||||
qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>;
|
||||
qcom,rx-slave = <&wcd939x_rx_slave>;
|
||||
qcom,tx-slave = <&wcd939x_tx_slave>;
|
||||
|
||||
cdc-vdd-rx-supply = <&L7B>;
|
||||
qcom,cdc-vdd-rx-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-rx-current = <45000>;
|
||||
qcom,cdc-vdd-rx-lpm-supported = <1>;
|
||||
|
||||
cdc-vdd-tx-supply = <&L7B>;
|
||||
qcom,cdc-vdd-tx-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-tx-current = <45000>;
|
||||
qcom,cdc-vdd-tx-lpm-supported = <1>;
|
||||
|
||||
cdc-vdd-buck-supply = <&L7B>;
|
||||
qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-buck-current = <650000>;
|
||||
qcom,cdc-vdd-buck-lpm-supported = <1>;
|
||||
|
||||
cdc-vdd-mic-bias-supply = <&BOB>;
|
||||
qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>;
|
||||
qcom,cdc-vdd-mic-bias-current = <30000>;
|
||||
|
||||
cdc-vdd-px-supply = <&L3G>;
|
||||
qcom,cdc-vdd-px-voltage = <1200000 1200000>;
|
||||
qcom,cdc-vdd-px-current = <15000>;
|
||||
qcom,cdc-vdd-px-lpm-supported = <1>;
|
||||
|
||||
qcom,cdc-vdd-px-rem-supported = <1>;
|
||||
|
||||
qcom,cdc-micbias1-mv = <1800>;
|
||||
qcom,cdc-micbias2-mv = <1800>;
|
||||
qcom,cdc-micbias3-mv = <1800>;
|
||||
qcom,cdc-micbias4-mv = <1800>;
|
||||
|
||||
qcom,cdc-static-supplies = "cdc-vdd-rx",
|
||||
"cdc-vdd-tx",
|
||||
"cdc-vdd-mic-bias";
|
||||
qcom,cdc-on-demand-supplies = "cdc-vdd-buck",
|
||||
"cdc-vdd-px";
|
||||
|
||||
wcd_mb1_reg: qcom,wcd-mb1-reg {
|
||||
regulator-name = "wcd-mb1-reg";
|
||||
};
|
||||
|
||||
wcd_mb2_reg: qcom,wcd-mb2-reg {
|
||||
regulator-name = "wcd-mb2-reg";
|
||||
};
|
||||
|
||||
wcd_mb3_reg: qcom,wcd-mb3-reg {
|
||||
regulator-name = "wcd-mb3-reg";
|
||||
};
|
||||
|
||||
wcd_mb4_reg: qcom,wcd-mb4-reg {
|
||||
regulator-name = "wcd-mb4-reg";
|
||||
};
|
||||
};
|
||||
|
||||
wcd9378_codec: wcd9378-codec {
|
||||
compatible = "qcom,wcd9378-codec";
|
||||
qcom,split-codec = <1>;
|
||||
qcom,wcd-mode = <1>;
|
||||
qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
|
||||
<0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>,
|
||||
<2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
|
||||
<3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
|
||||
<4 DSD_R 0x2 0 DSD_R>;
|
||||
qcom,tx_swr_ch_map = <0 ADC1 0x1 0 SWRM_TX1_CH1>,
|
||||
<1 ADC2 0x1 0 SWRM_TX1_CH2>,
|
||||
<2 ADC3 0x1 0 SWRM_TX1_CH3>,
|
||||
<3 DMIC0 0x4 0 SWRM_TX2_CH1>,
|
||||
<3 DMIC1 0x8 0 SWRM_TX2_CH2>,
|
||||
<3 MBHC 0x4 0 SWRM_TX2_CH3>,
|
||||
<4 DMIC2 0x1 0 SWRM_TX2_CH3>,
|
||||
<4 DMIC3 0x2 0 SWRM_TX2_CH4>,
|
||||
<4 DMIC4 0x3 0 SWRM_TX3_CH1>,
|
||||
<4 DMIC5 0x4 0 SWRM_TX3_CH2>;
|
||||
qcom,swr-tx-port-params =
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE1>, <OFFSET1_VAL0 LANE1>, <OFFSET1_VAL1 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE1>, <OFFSET1_VAL0 LANE1>, <OFFSET1_VAL1 LANE0>,
|
||||
<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL2 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>;
|
||||
qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>;
|
||||
qcom,rx-slave = <&wcd9378_rx_slave>;
|
||||
qcom,tx-slave = <&wcd9378_tx_slave>;
|
||||
|
||||
cdc-vdd-rxtx-supply = <&L7B>;
|
||||
qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-rxtx-current = <30000>;
|
||||
qcom,cdc-vdd-rxtx-lpm-supported = <1>;
|
||||
|
||||
cdc-vdd-io-supply = <&L3G>;
|
||||
qcom,cdc-vdd-io-voltage = <1200000 1200000>;
|
||||
qcom,cdc-vdd-io-current = <20000>;
|
||||
qcom,cdc-vdd-io-lpm-supported = <1>;
|
||||
|
||||
cdc-vdd-buck-supply = <&L7B>;
|
||||
qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-buck-current = <30070>;
|
||||
qcom,cdc-vdd-buck-lpm-supported = <1>;
|
||||
|
||||
cdc-vdd-mic-bias-supply = <&BOB>;
|
||||
qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>;
|
||||
qcom,cdc-vdd-mic-bias-current = <40550>;
|
||||
|
||||
qcom,cdc-micbias1-mv = <1800>;
|
||||
qcom,cdc-micbias2-mv = <1800>;
|
||||
qcom,cdc-micbias3-mv = <1800>;
|
||||
|
||||
qcom,cdc-static-supplies = "cdc-vdd-rxtx",
|
||||
"cdc-vdd-io";
|
||||
qcom,cdc-on-demand-supplies = "cdc-vdd-buck";
|
||||
};
|
||||
};
|
||||
|
||||
&lpass_bt_swr {
|
||||
clock-names = "bt_swr_mclk_clk", "bt_swr_mclk_clk_2x",
|
||||
"lpass_core_hw_vote", "lpass_audio_hw_vote";
|
||||
clocks = <&clock_audio_bt_swr_mclk_clk 0>,
|
||||
<&clock_audio_bt_swr_mclk_clk_2x 0>,
|
||||
<&lpass_core_hw_vote 0>,
|
||||
<&lpass_audio_hw_vote 0>;
|
||||
qcom,bt-swr-gpios = <&bt_swr_gpios>;
|
||||
};
|
||||
|
||||
&swr4 {
|
||||
compatible = "qcom,swr-mstr";
|
||||
qcom,swr_master_id = <5>;
|
||||
clock-names = "lpass_core_hw_vote",
|
||||
"lpass_audio_hw_vote";
|
||||
clocks = <&lpass_core_hw_vote 0>,
|
||||
<&lpass_audio_hw_vote 0>;
|
||||
swrm-io-base = <0x06CA0000 0x0>;
|
||||
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "swr_master_irq";
|
||||
qcom,swr-num-ports = <7>;
|
||||
qcom,swr-port-mapping = <1 BT_AUDIO_RX1 0x3>,
|
||||
<2 BT_AUDIO_RX2 0x3>, <3 BT_AUDIO_RX3 0x3>,
|
||||
<5 BT_AUDIO_TX1 0x3>, <6 BT_AUDIO_TX2 0x3>,
|
||||
<7 BT_AUDIO_TX3 0x3>, <8 FM_AUDIO_TX1 0x3>;
|
||||
qcom,swr-num-dev = <1>;
|
||||
};
|
||||
|
||||
&spf_core_platform {
|
||||
kera_snd: sound {
|
||||
qcom,model = "kera-qrd-snd-card";
|
||||
qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>, <1>, <1>;
|
||||
qcom,mi2s-tdm-is-hw-vote-needed = <1>, <1>, <1>, <1>, <1>, <1>, <1>;
|
||||
qcom,wcn-bt = <1>;
|
||||
qcom,ext-disp-audio-rx = <1>;
|
||||
qcom,tdm-max-slots = <8>;
|
||||
qcom,tdm-clk-attribute = <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>;
|
||||
qcom,mi2s-clk-attribute = <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>;
|
||||
qcom,audio-core-list = <0>, <1>;
|
||||
qcom,audio-routing =
|
||||
"AMIC1", "Analog Mic1",
|
||||
"AMIC1", "MIC BIAS1",
|
||||
"AMIC2", "Analog Mic2",
|
||||
"AMIC2", "MIC BIAS2",
|
||||
"AMIC3", "Analog Mic3",
|
||||
"AMIC3", "MIC BIAS3",
|
||||
"AMIC4", "Analog Mic4",
|
||||
"AMIC4", "MIC BIAS1",
|
||||
"VA AMIC1", "Analog Mic1",
|
||||
"VA AMIC1", "VA MIC BIAS1",
|
||||
"VA AMIC2", "Analog Mic2",
|
||||
"VA AMIC2", "VA MIC BIAS2",
|
||||
"VA AMIC3", "Analog Mic3",
|
||||
"VA AMIC3", "VA MIC BIAS3",
|
||||
"VA AMIC4", "Analog Mic4",
|
||||
"VA AMIC4", "VA MIC BIAS1",
|
||||
"TX DMIC0", "Digital Mic0",
|
||||
"TX DMIC0", "MIC BIAS3",
|
||||
"TX DMIC1", "Digital Mic1",
|
||||
"TX DMIC1", "MIC BIAS3",
|
||||
"TX DMIC2", "Digital Mic2",
|
||||
"TX DMIC2", "MIC BIAS1",
|
||||
"TX DMIC3", "Digital Mic3",
|
||||
"TX DMIC3", "MIC BIAS1",
|
||||
"IN1_HPHL", "HPHL_OUT",
|
||||
"IN2_HPHR", "HPHR_OUT",
|
||||
"IN3_AUX", "AUX_OUT",
|
||||
"WSA SRC0_INP", "SRC0",
|
||||
"WSA_TX DEC0_INP", "TX DEC0 MUX",
|
||||
"WSA_TX DEC1_INP", "TX DEC1 MUX",
|
||||
"RX_TX DEC0_INP", "TX DEC0 MUX",
|
||||
"RX_TX DEC1_INP", "TX DEC1 MUX",
|
||||
"RX_TX DEC2_INP", "TX DEC2 MUX",
|
||||
"RX_TX DEC3_INP", "TX DEC3 MUX",
|
||||
"SpkrLeft IN", "WSA_SPK1 OUT",
|
||||
"VA SWR_INPUT", "VA_SWR_CLK",
|
||||
"VA_AIF1 CAP", "VA_SWR_CLK",
|
||||
"VA_AIF2 CAP", "VA_SWR_CLK",
|
||||
"VA_AIF3 CAP", "VA_SWR_CLK",
|
||||
"VA DMIC0", "Digital Mic0",
|
||||
"VA DMIC1", "Digital Mic1",
|
||||
"VA DMIC2", "Digital Mic2",
|
||||
"VA DMIC3", "Digital Mic3",
|
||||
"VA DMIC0", "VA MIC BIAS3",
|
||||
"VA DMIC1", "VA MIC BIAS3",
|
||||
"VA DMIC2", "VA MIC BIAS1",
|
||||
"VA DMIC3", "VA MIC BIAS1";
|
||||
asoc-codec = <&stub_codec>, <&lpass_cdc>,
|
||||
<&wcd9378_codec>, <&wsa884x_0221>;
|
||||
asoc-codec-names = "msm-stub-codec.1", "lpass-cdc",
|
||||
"wcd9378_codec", "wsa-codec2";
|
||||
qcom,msm-mbhc-usbc-audio-supported = <1>;
|
||||
qcom,msm-mbhc-hphl-swh = <0>;
|
||||
qcom,msm-mbhc-gnd-swh = <0>;
|
||||
qcom,wsa-max-devs = <1>;
|
||||
qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>;
|
||||
qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>;
|
||||
qcom,msm_audio_ssr_devs = <&audio_gpr>, <&lpi_tlmm>,
|
||||
<&lpass_cdc>, <&lpass_bt_swr>;
|
||||
|
||||
};
|
||||
|
||||
cdc_pri_mi2s_gpios: pri_mi2s_pinctrl {
|
||||
status = "disabled";
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&i2s0_sck_active &i2s0_ws_active
|
||||
&i2s0_sd0_active>;
|
||||
pinctrl-1 = <&i2s0_sck_sleep &i2s0_ws_sleep
|
||||
&i2s0_sd0_sleep>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
cdc_quat_mi2s_gpios: quat_mi2s_pinctrl {
|
||||
status = "disabled";
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&quat_mi2s_sck_active &quat_mi2s_ws_active
|
||||
&quat_mi2s_sd0_active &quat_mi2s_sd1_active
|
||||
&quat_mi2s_sd2_active &quat_mi2s_sd3_active>;
|
||||
pinctrl-1 = <&quat_mi2s_sck_sleep &quat_mi2s_ws_sleep
|
||||
&quat_mi2s_sd0_sleep &quat_mi2s_sd1_sleep
|
||||
&quat_mi2s_sd2_sleep &quat_mi2s_sd3_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <138 143>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
cdc_quin_mi2s_gpios: quin_mi2s_pinctrl {
|
||||
status = "disabled";
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&lpi_i2s1_sck_active &lpi_i2s1_ws_active
|
||||
&lpi_i2s1_data0_active &lpi_i2s1_data1_active>;
|
||||
pinctrl-1 = <&lpi_i2s1_sck_sleep &lpi_i2s1_ws_sleep
|
||||
&lpi_i2s1_data0_sleep &lpi_i2s1_data1_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <144 147>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
cdc_sen_mi2s_gpios: sen_mi2s_pinctrl {
|
||||
status = "disabled";
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&lpi_i2s2_sck_active &lpi_i2s2_ws_active
|
||||
&lpi_i2s2_data0_active &lpi_i2s2_data1_active>;
|
||||
pinctrl-1 = <&lpi_i2s2_sck_sleep &lpi_i2s2_ws_sleep
|
||||
&lpi_i2s2_data0_sleep &lpi_i2s2_data1_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <148 151>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
cdc_sep_mi2s_gpios: sep_mi2s_pinctrl {
|
||||
status = "disabled";
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&lpi_i2s3_sck_active &lpi_i2s3_ws_active
|
||||
&lpi_i2s3_data0_active &lpi_i2s3_data1_active>;
|
||||
pinctrl-1 = <&lpi_i2s3_sck_sleep &lpi_i2s3_ws_sleep
|
||||
&lpi_i2s3_data0_sleep &lpi_i2s3_data1_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <153 156>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
wsa_swr_gpios: wsa_swr_clk_data_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&wsa_swr_clk_active &wsa_swr_data_active>;
|
||||
pinctrl-1 = <&wsa_swr_clk_sleep &wsa_swr_data_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <149>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
rx_swr_gpios: rx_swr_clk_data_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&rx_swr_clk_active &rx_swr_data_active
|
||||
&rx_swr_data1_active>;
|
||||
pinctrl-1 = <&rx_swr_clk_sleep &rx_swr_data_sleep
|
||||
&rx_swr_data1_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <142>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
va_swr_gpios: tx_swr_clk_data_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&tx_swr_clk_active &tx_swr_data0_active
|
||||
&tx_swr_data1_active &tx_swr_data2_active>;
|
||||
pinctrl-1 = <&tx_swr_clk_sleep &tx_swr_data0_sleep
|
||||
&tx_swr_data1_sleep &tx_swr_data2_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,chip-wakeup-reg = <0xf18b008>;
|
||||
qcom,chip-wakeup-maskbit = <7>;
|
||||
qcom,chip-wakeup-default-val = <0x1>;
|
||||
qcom,tlmm-pins = <139>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
cdc_dmic01_gpios: cdc_dmic01_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&cdc_dmic01_clk_active &cdc_dmic01_data_active>;
|
||||
pinctrl-1 = <&cdc_dmic01_clk_sleep &cdc_dmic01_data_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <144 145>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
cdc_dmic23_gpios: cdc_dmic23_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&cdc_dmic23_clk_active &cdc_dmic23_data_active>;
|
||||
pinctrl-1 = <&cdc_dmic23_clk_sleep &cdc_dmic23_data_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <146 147>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
cdc_dmic45_gpios: cdc_dmic45_pinctrl {
|
||||
status = "disabled";
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&cdc_dmic45_clk_active &cdc_dmic45_data_active>;
|
||||
pinctrl-1 = <&cdc_dmic45_clk_sleep &cdc_dmic45_data_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <150 151>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
cdc_dmic67_gpios: cdc_dmic67_pinctrl {
|
||||
status = "disabled";
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&cdc_dmic67_clk_active &cdc_dmic67_data_active>;
|
||||
pinctrl-1 = <&cdc_dmic67_clk_sleep &cdc_dmic67_data_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <155 156>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
bt_swr_gpios: bt_swr_clk_data_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&bt_swr_clk_active &bt_swr_data_active>;
|
||||
pinctrl-1 = <&bt_swr_clk_sleep &bt_swr_data_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
wsa_spkr_en02: wsa_spkr_en1_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&spkr_1_sd_n_active>;
|
||||
pinctrl-1 = <&spkr_1_sd_n_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
};
|
||||
|
||||
wsa_spkr_en13: wsa_spkr_en2_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&spkr_2_sd_n_active>;
|
||||
pinctrl-1 = <&spkr_2_sd_n_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
};
|
||||
|
||||
wcd_rst_gpio: msm_cdc_pinctrl@32 {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&wcd_reset_active>;
|
||||
pinctrl-1 = <&wcd_reset_sleep>;
|
||||
};
|
||||
|
||||
clock_audio_va_1: va_core_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK>;
|
||||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||||
qcom,codec-lpass-clk-id = <0x307>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_wsa_1: wsa_core_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_2>;
|
||||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||||
qcom,codec-lpass-clk-id = <0x309>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_rx_1: rx_core_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_4>;
|
||||
qcom,codec-lpass-ext-clk-freq = <22579200>;
|
||||
qcom,codec-lpass-clk-id = <0x30E>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_rx_tx: rx_core_tx_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_10>;
|
||||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||||
qcom,codec-lpass-clk-id = <0x312>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_tx_1: tx_core_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_6>;
|
||||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||||
qcom,codec-lpass-clk-id = <0x30C>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_wsa_tx: wsa_core_tx_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_11>;
|
||||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||||
qcom,codec-lpass-clk-id = <0x314>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_rx_mclk2_2x_clk: rx_mclk2_2x_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_13>;
|
||||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||||
qcom,codec-lpass-clk-id = <0x318>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_bt_swr_mclk_clk: bt_swr_mclk_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_15>;
|
||||
qcom,codec-lpass-ext-clk-freq = <24576000>;
|
||||
qcom,codec-lpass-clk-id = <0x31A>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_bt_swr_mclk_clk_2x: bt_swr_mclk_clk_2x {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_16>;
|
||||
qcom,codec-lpass-ext-clk-freq = <24576000>;
|
||||
qcom,codec-lpass-clk-id = <0x31B>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&adsp_loader {
|
||||
status = "ok";
|
||||
};
|
||||
17
qcom/audio/kera-audio-qrd.dts
Normal file
17
qcom/audio/kera-audio-qrd.dts
Normal file
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "kera-audio-qrd.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kera QRD";
|
||||
compatible = "qcom,kera-qrd", "qcom,kera", "qcom,kerap-qrd", "qcom,kerap",
|
||||
"qcom,qrd";
|
||||
qcom,msm-id = <686 0x10000>, <659 0x10000>;
|
||||
qcom,board-id = <0x1000B 0>, <0x2000B 0>, <0x3000B 0>;
|
||||
};
|
||||
86
qcom/audio/kera-audio-qrd.dtsi
Normal file
86
qcom/audio/kera-audio-qrd.dtsi
Normal file
@@ -0,0 +1,86 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
#include "kera-audio-overlay.dtsi"
|
||||
#include "kera-audio-lpass-reg.dtsi"
|
||||
|
||||
&tx_swr_clk_active {
|
||||
config {
|
||||
drive-strength = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&tx_swr_data0_active {
|
||||
config {
|
||||
drive-strength = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&tx_swr_data1_active {
|
||||
config {
|
||||
drive-strength = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&tx_swr_data2_active {
|
||||
config {
|
||||
drive-strength = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&swr0 {
|
||||
wsa884x_0220: wsa884x@02170220 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
wsa884x_0221: wsa884x@02170221 {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
&wsa_macro {
|
||||
qcom,wsa-bat-cfgs = <1>, <1>;
|
||||
};
|
||||
|
||||
&wcd939x_rx_slave {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wcd939x_tx_slave {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wcd939x_codec {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cdc_dmic01_gpios {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cdc_dmic23_gpios {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wcd9378_codec {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wcd9378_rx_slave {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wcd9378_tx_slave {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&kera_snd {
|
||||
qcom,model = "kera-qrd-snd-card";
|
||||
asoc-codec = <&stub_codec>, <&lpass_cdc>,
|
||||
<&wcd9378_codec>, <&wsa884x_0220>;
|
||||
asoc-codec-names = "msm-stub-codec.1", "lpass-cdc",
|
||||
"wcd9378_codec", "wsa-codec1";
|
||||
qcom,wsa-max-devs = <1>;
|
||||
fsa4480-i2c-handle = <&fsa4480>;
|
||||
};
|
||||
17
qcom/audio/kera-audio-rcm-orne.dts
Normal file
17
qcom/audio/kera-audio-rcm-orne.dts
Normal file
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "kera-audio-rcm-orne.dtsi"
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kuna RCM+ORNE";
|
||||
compatible = "qcom,kera-rcm", "qcom,kera", "qcom,kerap-rcm", "qcom,kerap",
|
||||
"qcom,rcm";
|
||||
qcom,msm-id = <686 0x10000>, <659 0x10000>;
|
||||
qcom,board-id = <0x10015 0>, <0x20015 0>, <0x30015 0>, <0x30015 1>,
|
||||
<0x10015 1>, <0x20015 1>;
|
||||
};
|
||||
13
qcom/audio/kera-audio-rcm-orne.dtsi
Normal file
13
qcom/audio/kera-audio-rcm-orne.dtsi
Normal file
@@ -0,0 +1,13 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "kera-audio-cdp.dtsi"
|
||||
|
||||
&lpass_bt_swr {
|
||||
status = "okay";
|
||||
};
|
||||
17
qcom/audio/kera-audio-rcm.dts
Normal file
17
qcom/audio/kera-audio-rcm.dts
Normal file
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "kera-audio-cdp.dtsi"
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kuna RCM";
|
||||
compatible = "qcom,kera-rcm", "qcom,kera", "qcom,kerap-rcm", "qcom,kerap",
|
||||
"qcom,rcm";
|
||||
qcom,msm-id = <686 0x10000>, <659 0x10000>;
|
||||
qcom,board-id = <0x10015 0>, <0x20015 0>, <0x30015 0>, <0x30015 1>,
|
||||
<0x10015 1>, <0x20015 1>;
|
||||
};
|
||||
21
qcom/audio/kera-audio.dts
Normal file
21
qcom/audio/kera-audio.dts
Normal file
@@ -0,0 +1,21 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/clock/qcom,gcc-kera.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interconnect/qcom,kera.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
|
||||
#include "kera-audio.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. kera";
|
||||
compatible = "qcom,kera";
|
||||
qcom,msm-id = <686 0x10000>, <659 0x10000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
186
qcom/audio/kera-audio.dtsi
Normal file
186
qcom/audio/kera-audio.dtsi
Normal file
@@ -0,0 +1,186 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <bindings/qcom,audio-ext-clk.h>
|
||||
#include <bindings/qcom,gpr.h>
|
||||
#include "msm-audio-lpass.dtsi"
|
||||
|
||||
&soc {
|
||||
spf_core_platform: spf_core_platform {
|
||||
compatible = "qcom,spf-core-platform";
|
||||
};
|
||||
|
||||
lpass_core_hw_vote: vote_lpass_core_hw {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_CORE_HW_VOTE>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
lpass_audio_hw_vote: vote_lpass_audio_hw {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_AUDIO_HW_VOTE>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&remoteproc_adsp_glink {
|
||||
audio_gpr: qcom,gpr {
|
||||
compatible = "qcom,gpr";
|
||||
qcom,glink-channels = "adsp_apps";
|
||||
qcom,intents = <0x200 20>;
|
||||
qcom,ch-sched-rt;
|
||||
reg = <GPR_DOMAIN_ADSP>;
|
||||
|
||||
spf_core {
|
||||
compatible = "qcom,spf_core";
|
||||
reg = <GPR_SVC_ADSP_CORE>;
|
||||
};
|
||||
|
||||
audio-pkt {
|
||||
compatible = "qcom,audio-pkt";
|
||||
qcom,audiopkt-ch-name = "apr_audio_svc";
|
||||
reg = <GPR_SVC_MAX>;
|
||||
};
|
||||
|
||||
audio_prm: q6prm {
|
||||
compatible = "qcom,audio_prm";
|
||||
qcom,sleep-api-supported = <1>;
|
||||
reg = <GPR_SVC_ASM>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spf_core_platform {
|
||||
|
||||
msm_audio_ion: qcom,msm-audio-ion {
|
||||
compatible = "qcom,msm-audio-ion";
|
||||
qcom,smmu-version = <2>;
|
||||
qcom,smmu-enabled;
|
||||
iommus = <&apps_smmu 0x1001 0x0080>, <&apps_smmu 0x1041 0x20>;
|
||||
memory-region = <&audio_cnss_resv_region>;
|
||||
qcom,smmu-sid-mask = /bits/ 64 <0xf>;
|
||||
dma-coherent;
|
||||
|
||||
audio_cnss_resv_region: audio_cnss_resv_region {
|
||||
iommu-addresses = <&msm_audio_ion 0x00000000 0x18000000>,
|
||||
<&msm_audio_ion 0xb0000000 0x50000000>;
|
||||
};
|
||||
};
|
||||
|
||||
msm_audio_ion_cma: qcom,msm-audio-ion-cma {
|
||||
compatible = "qcom,msm-audio-ion-cma";
|
||||
};
|
||||
|
||||
lpi_tlmm: lpi_pinctrl@07760000 {
|
||||
compatible = "qcom,lpi-pinctrl";
|
||||
reg = <0x07760000 0x0>;
|
||||
qcom,gpios-count = <23>;
|
||||
qcom,slew-reg = <0x07760000 0x0>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
qcom,lpi-offset-tbl = <0x00000000>, <0x00001000>,
|
||||
<0x00002000>, <0x00003000>,
|
||||
<0x00004000>, <0x00005000>,
|
||||
<0x00006000>, <0x00007000>,
|
||||
<0x00008000>, <0x00009000>,
|
||||
<0x0000A000>, <0x0000B000>,
|
||||
<0x0000C000>, <0x0000D000>,
|
||||
<0x0000E000>, <0x0000F000>,
|
||||
<0x00010000>, <0x00011000>,
|
||||
<0x00012000>, <0x00013000>,
|
||||
<0x00014000>, <0x00015000>,
|
||||
<0x00016000>;
|
||||
qcom,lpi-slew-offset-tbl = <0x0000000B>, <0x0000000B>,
|
||||
<0x0000000B>, <0x0000000B>,
|
||||
<0x0000000B>, <0x0000000B>,
|
||||
<0x0000000B>, <0x0000000B>,
|
||||
<0x0000000B>, <0x0000000B>,
|
||||
<0x0000000B>, <0x0000000B>,
|
||||
<0x0000000B>, <0x0000000B>,
|
||||
<0x0000000B>, <0x0000000B>,
|
||||
<0x0000000B>, <0x0000000B>,
|
||||
<0x0000000B>, <0x0000000B>,
|
||||
<0x0000000B>, <0x0000000B>,
|
||||
<0x0000000B>;
|
||||
|
||||
qcom,lpi-slew-base-tbl = <0x7760000>, <0x7761000>,
|
||||
<0x7762000>, <0x7763000>,
|
||||
<0x7764000>, <0x7765000>,
|
||||
<0x7766000>, <0x7767000>,
|
||||
<0x7768000>, <0x7769000>,
|
||||
<0x776A000>, <0x776B000>,
|
||||
<0x776C000>, <0x776D000>,
|
||||
<0x776E000>, <0x776F000>,
|
||||
<0x7770000>, <0x7771000>,
|
||||
<0x7772000>, <0x7773000>,
|
||||
<0x7774000>, <0x7775000>,
|
||||
<0x7776000>;
|
||||
|
||||
clock-names = "lpass_core_hw_vote",
|
||||
"lpass_audio_hw_vote";
|
||||
clocks = <&lpass_core_hw_vote 0>,
|
||||
<&lpass_audio_hw_vote 0>;
|
||||
};
|
||||
|
||||
lpass_cdc: lpass-cdc {
|
||||
compatible = "qcom,lpass-cdc";
|
||||
clock-names = "lpass_core_hw_vote",
|
||||
"lpass_audio_hw_vote";
|
||||
clocks = <&lpass_core_hw_vote 0>,
|
||||
<&lpass_audio_hw_vote 0>;
|
||||
lpass-cdc-clk-rsc-mngr {
|
||||
compatible = "qcom,lpass-cdc-clk-rsc-mngr";
|
||||
};
|
||||
|
||||
va_macro: va-macro@7660000 {
|
||||
swr2: va_swr_master {
|
||||
};
|
||||
};
|
||||
|
||||
tx_macro: tx-macro@6AE0000 {
|
||||
};
|
||||
|
||||
rx_macro: rx-macro@6AC0000 {
|
||||
swr1: rx_swr_master {
|
||||
};
|
||||
};
|
||||
|
||||
wsa_macro: wsa-macro@6B00000 {
|
||||
swr0: wsa_swr_master {
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
lpass_bt_swr: lpass_bt_swr@6CA0000 {
|
||||
compatible = "qcom,lpass-bt-swr";
|
||||
swr4: bt_swr_mstr {
|
||||
};
|
||||
};
|
||||
|
||||
kera_snd: sound {
|
||||
compatible = "qcom,sun-asoc-snd";
|
||||
qcom,mi2s-audio-intf = <1>;
|
||||
qcom,tdm-audio-intf = <0>;
|
||||
qcom,auxpcm-audio-intf = <1>;
|
||||
qcom,wcn-bt = <0>;
|
||||
qcom,ext-disp-audio-rx = <0>;
|
||||
qcom,afe-rxtx-lb = <0>;
|
||||
|
||||
clock-names = "lpass_audio_hw_vote";
|
||||
clocks = <&lpass_audio_hw_vote 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&aliases {
|
||||
swr0 = "/soc/spf_core_platform/lpass-cdc/wsa-macro@6B00000/wsa_swr_master";
|
||||
swr1 = "/soc/spf_core_platform/lpass-cdc/rx-macro@6AC0000/rx_swr_master";
|
||||
swr2 = "/soc/spf_core_platform/lpass-cdc/va-macro@7660000/va_swr_master";
|
||||
swr4 = "/soc/spf_core_platform/lpass_bt_swr@6CA0000/bt_swr_mstr";
|
||||
};
|
||||
|
||||
&adsp_loader {
|
||||
/delete-property/ qcom,adsp-state;
|
||||
};
|
||||
18
qcom/audio/kera-iot-audio-cdp.dts
Normal file
18
qcom/audio/kera-iot-audio-cdp.dts
Normal file
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "kera-iot-audio-cdp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kera CDP for IoT";
|
||||
compatible = "qcom,kera-cdp", "qcom,kera", "qcom,kerap-cdp", "qcom,kerap",
|
||||
"qcom,cdp";
|
||||
qcom,msm-id = <686 0x10000>, <659 0x10000>;
|
||||
qcom,board-id = <0x50001 0>;
|
||||
};
|
||||
|
||||
155
qcom/audio/kera-iot-audio-cdp.dtsi
Normal file
155
qcom/audio/kera-iot-audio-cdp.dtsi
Normal file
@@ -0,0 +1,155 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "kera-audio-overlay.dtsi"
|
||||
#include "kera-audio-lpass-reg.dtsi"
|
||||
|
||||
&cdc_pri_mi2s_gpios {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&cdc_quat_mi2s_gpios {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cdc_quin_mi2s_gpios {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cdc_sen_mi2s_gpios {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cdc_sep_mi2s_gpios {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&lpass_bt_swr {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cdc_dmic67_gpios {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wcd9378_codec {
|
||||
status = "okay";
|
||||
cdc-vdd-io-supply = <&L7B>;
|
||||
qcom,cdc-vdd-io-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-io-current = <20000>;
|
||||
qcom,cdc-vdd-io-lpm-supported = <1>;
|
||||
|
||||
cdc-vdd-mic-bias-supply = <&BOB>;
|
||||
qcom,cdc-vdd-mic-bias-voltage = <3300000 3300000>;
|
||||
qcom,cdc-vdd-mic-bias-current = <40550>;
|
||||
};
|
||||
|
||||
&wcd939x_rx_slave {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wcd939x_tx_slave {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wcd9378_rx_slave {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wcd9378_tx_slave {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&swr0 {
|
||||
qcom,swr-num-dev = <2>;
|
||||
wsa884x_0220: wsa884x@02170220 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
wsa884x_0221: wsa884x@02170221 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&swr1 {
|
||||
qcom,swr-num-dev = <2>;
|
||||
};
|
||||
|
||||
&kera_snd {
|
||||
qcom,model = "kera-cdp-snd-card";
|
||||
swr-haptics-unsupported;
|
||||
qcom,audio-routing =
|
||||
"AMIC1", "Analog Mic1",
|
||||
"AMIC1", "MIC BIAS1",
|
||||
"AMIC2", "Analog Mic2",
|
||||
"AMIC2", "MIC BIAS2",
|
||||
"AMIC3", "Analog Mic3",
|
||||
"AMIC3", "MIC BIAS3",
|
||||
"AMIC4", "Analog Mic4",
|
||||
"VA AMIC1", "Analog Mic1",
|
||||
"VA AMIC1", "VA MIC BIAS1",
|
||||
"VA AMIC2", "Analog Mic2",
|
||||
"VA AMIC2", "VA MIC BIAS2",
|
||||
"VA AMIC3", "Analog Mic3",
|
||||
"VA AMIC3", "VA MIC BIAS3",
|
||||
"VA AMIC4", "Analog Mic4",
|
||||
"TX DMIC0", "Digital Mic0",
|
||||
"TX DMIC0", "MIC BIAS3",
|
||||
"TX DMIC1", "Digital Mic1",
|
||||
"TX DMIC1", "MIC BIAS3",
|
||||
"TX DMIC2", "Digital Mic2",
|
||||
"TX DMIC2", "MIC BIAS1",
|
||||
"TX DMIC3", "Digital Mic3",
|
||||
"TX DMIC3", "MIC BIAS1",
|
||||
"TX DMIC6", "Digital Mic6",
|
||||
"TX DMIC6", "MIC BIAS1",
|
||||
"TX DMIC7", "Digital Mic7",
|
||||
"TX DMIC7", "MIC BIAS1",
|
||||
"IN1_HPHL", "HPHL_OUT",
|
||||
"IN2_HPHR", "HPHR_OUT",
|
||||
"IN3_AUX", "AUX_OUT",
|
||||
"WSA SRC0_INP", "SRC0",
|
||||
"WSA_TX DEC0_INP", "TX DEC0 MUX",
|
||||
"WSA_TX DEC1_INP", "TX DEC1 MUX",
|
||||
"RX_TX DEC0_INP", "TX DEC0 MUX",
|
||||
"RX_TX DEC1_INP", "TX DEC1 MUX",
|
||||
"RX_TX DEC2_INP", "TX DEC2 MUX",
|
||||
"RX_TX DEC3_INP", "TX DEC3 MUX",
|
||||
"SpkrLeft IN", "WSA_SPK1 OUT",
|
||||
"SpkrRight IN", "WSA_SPK2 OUT",
|
||||
"VA SWR_INPUT", "VA_SWR_CLK",
|
||||
"VA_AIF1 CAP", "VA_SWR_CLK",
|
||||
"VA_AIF2 CAP", "VA_SWR_CLK",
|
||||
"VA_AIF3 CAP", "VA_SWR_CLK",
|
||||
"VA DMIC0", "Digital Mic0",
|
||||
"VA DMIC1", "Digital Mic1",
|
||||
"VA DMIC2", "Digital Mic2",
|
||||
"VA DMIC3", "Digital Mic3",
|
||||
"VA DMIC6", "Digital Mic6",
|
||||
"VA DMIC7", "Digital Mic7",
|
||||
"VA DMIC0", "VA MIC BIAS3",
|
||||
"VA DMIC1", "VA MIC BIAS3",
|
||||
"VA DMIC2", "VA MIC BIAS1",
|
||||
"VA DMIC3", "VA MIC BIAS1",
|
||||
"VA DMIC6", "VA MIC BIAS1",
|
||||
"VA DMIC7", "VA MIC BIAS1";
|
||||
asoc-codec = <&stub_codec>, <&lpass_cdc>,
|
||||
<&wcd9378_codec>,
|
||||
<&wsa884x_0220>, <&wsa884x_0221>;
|
||||
asoc-codec-names = "msm-stub-codec.1", "lpass-cdc",
|
||||
"wcd9378_codec",
|
||||
"wsa-codec1", "wsa-codec2";
|
||||
qcom,wsa-max-devs = <2>;
|
||||
qcom,pri-mi2s-gpios = <&cdc_pri_mi2s_gpios>;
|
||||
qcom,quat-mi2s-gpios = <&cdc_quat_mi2s_gpios>;
|
||||
qcom,quin-mi2s-gpios = <&cdc_quin_mi2s_gpios>;
|
||||
qcom,sen-mi2s-gpios = <&cdc_sen_mi2s_gpios>;
|
||||
qcom,sep-mi2s-gpios = <&cdc_sep_mi2s_gpios>;
|
||||
qcom,cdc-dmic67-gpios = <&cdc_dmic67_gpios>;
|
||||
qcom,msm-mbhc-usbc-audio-supported = <0>;
|
||||
qcom,msm-mbhc-hphl-swh = <1>;
|
||||
qcom,msm-mbhc-gnd-swh = <1>;
|
||||
qcom,msm-mbhc-hs-mic-max-threshold-mv = <1680>;
|
||||
};
|
||||
2188
qcom/audio/kera-lpi.dtsi
Normal file
2188
qcom/audio/kera-lpi.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
27
qcom/audio/msm-audio-lpass.dtsi
Normal file
27
qcom/audio/msm-audio-lpass.dtsi
Normal file
@@ -0,0 +1,27 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&soc {
|
||||
stub_codec: qcom,msm-stub-codec {
|
||||
compatible = "qcom,msm-stub-codec";
|
||||
};
|
||||
|
||||
audio_pkt_core_platform: qcom,audio-pkt-core-platform {
|
||||
compatible = "qcom,audio-pkt-core-platform";
|
||||
};
|
||||
|
||||
adsp_loader: qcom,msm-adsp-loader {
|
||||
status = "disabled";
|
||||
compatible = "qcom,adsp-loader";
|
||||
qcom,rproc-handle = <&adsp_pas>;
|
||||
qcom,adsp-state = <0>;
|
||||
};
|
||||
|
||||
adsp_notify: qcom,msm-adsp-notify {
|
||||
status = "ok";
|
||||
compatible = "qcom,adsp-notify";
|
||||
qcom,rproc-handle = <&adsp_pas>;
|
||||
};
|
||||
};
|
||||
1004
qcom/audio/msm-auto-audio-lpass.dtsi
Normal file
1004
qcom/audio/msm-auto-audio-lpass.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
973
qcom/audio/msm-auto-vm-audio-lpass.dtsi
Normal file
973
qcom/audio/msm-auto-vm-audio-lpass.dtsi
Normal file
@@ -0,0 +1,973 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&soc {
|
||||
pcm0: qcom,msm-pcm {
|
||||
compatible = "qcom,msm-pcm-dsp";
|
||||
qcom,msm-pcm-dsp-id = <0>;
|
||||
};
|
||||
|
||||
routing: qcom,msm-pcm-routing {
|
||||
compatible = "qcom,msm-pcm-routing";
|
||||
};
|
||||
|
||||
compr: qcom,msm-compr-dsp {
|
||||
compatible = "qcom,msm-compr-dsp";
|
||||
};
|
||||
|
||||
pcm1: qcom,msm-pcm-low-latency {
|
||||
compatible = "qcom,msm-pcm-dsp";
|
||||
qcom,msm-pcm-dsp-id = <1>;
|
||||
qcom,msm-pcm-low-latency;
|
||||
qcom,latency-level = "regular";
|
||||
};
|
||||
|
||||
pcm2: qcom,msm-ultra-low-latency {
|
||||
compatible = "qcom,msm-pcm-dsp";
|
||||
qcom,msm-pcm-dsp-id = <2>;
|
||||
qcom,msm-pcm-low-latency;
|
||||
qcom,latency-level = "ultra";
|
||||
};
|
||||
|
||||
pcm_noirq: qcom,msm-pcm-dsp-noirq {
|
||||
compatible = "qcom,msm-pcm-dsp-noirq";
|
||||
qcom,msm-pcm-low-latency;
|
||||
qcom,latency-level = "ultra";
|
||||
};
|
||||
|
||||
trans_loopback: qcom,msm-transcode-loopback {
|
||||
compatible = "qcom,msm-transcode-loopback";
|
||||
};
|
||||
|
||||
compress: qcom,msm-compress-dsp {
|
||||
compatible = "qcom,msm-compress-dsp";
|
||||
};
|
||||
|
||||
voip: qcom,msm-voip-dsp {
|
||||
compatible = "qcom,msm-voip-dsp";
|
||||
};
|
||||
|
||||
voice: qcom,msm-pcm-voice {
|
||||
compatible = "qcom,msm-pcm-voice";
|
||||
qcom,destroy-cvd;
|
||||
};
|
||||
|
||||
stub_codec: qcom,msm-stub-codec {
|
||||
compatible = "qcom,msm-stub-codec";
|
||||
};
|
||||
|
||||
qcom,msm-dai-fe {
|
||||
compatible = "qcom,msm-dai-fe";
|
||||
};
|
||||
|
||||
afe: qcom,msm-pcm-afe {
|
||||
compatible = "qcom,msm-pcm-afe";
|
||||
};
|
||||
|
||||
dai_hdmi: qcom,msm-dai-q6-hdmi {
|
||||
compatible = "qcom,msm-dai-q6-hdmi";
|
||||
qcom,msm-dai-q6-dev-id = <8>;
|
||||
};
|
||||
|
||||
dai_dp: qcom,msm-dai-q6-dp {
|
||||
compatible = "qcom,msm-dai-q6-hdmi";
|
||||
qcom,msm-dai-q6-dev-id = <0>;
|
||||
};
|
||||
|
||||
dai_dp1: qcom,msm-dai-q6-dp1 {
|
||||
compatible = "qcom,msm-dai-q6-hdmi";
|
||||
qcom,msm-dai-q6-dev-id = <1>;
|
||||
};
|
||||
|
||||
loopback: qcom,msm-pcm-loopback {
|
||||
compatible = "qcom,msm-pcm-loopback";
|
||||
};
|
||||
|
||||
loopback1: qcom,msm-pcm-loopback-low-latency {
|
||||
compatible = "qcom,msm-pcm-loopback";
|
||||
qcom,msm-pcm-loopback-low-latency;
|
||||
};
|
||||
|
||||
pcm_dtmf: qcom,msm-pcm-dtmf {
|
||||
compatible = "qcom,msm-pcm-dtmf";
|
||||
};
|
||||
|
||||
msm_dai_mi2s: qcom,msm-dai-mi2s {
|
||||
compatible = "qcom,msm-dai-mi2s";
|
||||
dai_mi2s0_rx: qcom,msm-dai-q6-mi2s-prim-rx {
|
||||
compatible = "qcom,msm-dai-q6-mi2s";
|
||||
qcom,msm-dai-q6-mi2s-dev-id = <0>;
|
||||
qcom,msm-mi2s-lines = <3>;
|
||||
};
|
||||
|
||||
dai_mi2s0_tx: qcom,msm-dai-q6-mi2s-prim-tx {
|
||||
compatible = "qcom,msm-dai-q6-mi2s";
|
||||
qcom,msm-dai-q6-mi2s-dev-id = <1>;
|
||||
qcom,msm-mi2s-lines = <1>;
|
||||
};
|
||||
|
||||
dai_mi2s1_rx: qcom,msm-dai-q6-mi2s-sec-rx {
|
||||
compatible = "qcom,msm-dai-q6-mi2s";
|
||||
qcom,msm-dai-q6-mi2s-dev-id = <2>;
|
||||
qcom,msm-mi2s-lines = <1>;
|
||||
};
|
||||
|
||||
dai_mi2s1_tx: qcom,msm-dai-q6-mi2s-sec-tx {
|
||||
compatible = "qcom,msm-dai-q6-mi2s";
|
||||
qcom,msm-dai-q6-mi2s-dev-id = <3>;
|
||||
qcom,msm-mi2s-lines = <1>;
|
||||
};
|
||||
|
||||
dai_mi2s2_rx: qcom,msm-dai-q6-mi2s-tert-rx {
|
||||
compatible = "qcom,msm-dai-q6-mi2s";
|
||||
qcom,msm-dai-q6-mi2s-dev-id = <4>;
|
||||
qcom,msm-mi2s-lines = <1>;
|
||||
};
|
||||
|
||||
dai_mi2s2_tx: qcom,msm-dai-q6-mi2s-tert-tx {
|
||||
compatible = "qcom,msm-dai-q6-mi2s";
|
||||
qcom,msm-dai-q6-mi2s-dev-id = <5>;
|
||||
qcom,msm-mi2s-lines = <3>;
|
||||
};
|
||||
|
||||
dai_mi2s3_rx: qcom,msm-dai-q6-mi2s-quat-rx {
|
||||
compatible = "qcom,msm-dai-q6-mi2s";
|
||||
qcom,msm-dai-q6-mi2s-dev-id = <6>;
|
||||
qcom,msm-mi2s-lines = <1>;
|
||||
};
|
||||
|
||||
dai_mi2s3_tx: qcom,msm-dai-q6-mi2s-quat-tx {
|
||||
compatible = "qcom,msm-dai-q6-mi2s";
|
||||
qcom,msm-dai-q6-mi2s-dev-id = <7>;
|
||||
qcom,msm-mi2s-lines = <2>;
|
||||
};
|
||||
|
||||
dai_mi2s4_rx: qcom,msm-dai-q6-mi2s-quin-rx {
|
||||
compatible = "qcom,msm-dai-q6-mi2s";
|
||||
qcom,msm-dai-q6-mi2s-dev-id = <8>;
|
||||
qcom,msm-mi2s-lines = <1>;
|
||||
};
|
||||
|
||||
dai_mi2s4_tx: qcom,msm-dai-q6-mi2s-quin-tx {
|
||||
compatible = "qcom,msm-dai-q6-mi2s";
|
||||
qcom,msm-dai-q6-mi2s-dev-id = <9>;
|
||||
qcom,msm-mi2s-lines = <2>;
|
||||
};
|
||||
|
||||
dai_mi2s5_rx: qcom,msm-dai-q6-mi2s-senary-rx {
|
||||
compatible = "qcom,msm-dai-q6-mi2s";
|
||||
qcom,msm-dai-q6-mi2s-dev-id = <10>;
|
||||
qcom,msm-mi2s-lines = <1>;
|
||||
};
|
||||
|
||||
dai_mi2s5_tx: qcom,msm-dai-q6-mi2s-senary-tx {
|
||||
compatible = "qcom,msm-dai-q6-mi2s";
|
||||
qcom,msm-dai-q6-mi2s-dev-id = <11>;
|
||||
qcom,msm-mi2s-lines = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
msm_dai_cdc_dma: qcom,msm-dai-cdc-dma {
|
||||
compatible = "qcom,msm-dai-cdc-dma";
|
||||
wsa_cdc_dma_0_rx: qcom,msm-dai-wsa-cdc-dma-0-rx {
|
||||
compatible = "qcom,msm-dai-cdc-dma-dev";
|
||||
qcom,msm-dai-cdc-dma-dev-id = <45056>;
|
||||
};
|
||||
|
||||
wsa_cdc_dma_0_tx: qcom,msm-dai-wsa-cdc-dma-0-tx {
|
||||
compatible = "qcom,msm-dai-cdc-dma-dev";
|
||||
qcom,msm-dai-cdc-dma-dev-id = <45057>;
|
||||
};
|
||||
|
||||
wsa_cdc_dma_1_rx: qcom,msm-dai-wsa-cdc-dma-1-rx {
|
||||
compatible = "qcom,msm-dai-cdc-dma-dev";
|
||||
qcom,msm-dai-cdc-dma-dev-id = <45058>;
|
||||
};
|
||||
|
||||
wsa_cdc_dma_1_tx: qcom,msm-dai-wsa-cdc-dma-1-tx {
|
||||
compatible = "qcom,msm-dai-cdc-dma-dev";
|
||||
qcom,msm-dai-cdc-dma-dev-id = <45059>;
|
||||
};
|
||||
|
||||
wsa_cdc_dma_2_tx: qcom,msm-dai-wsa-cdc-dma-2-tx {
|
||||
compatible = "qcom,msm-dai-cdc-dma-dev";
|
||||
qcom,msm-dai-cdc-dma-dev-id = <45061>;
|
||||
};
|
||||
|
||||
va_cdc_dma_0_tx: qcom,msm-dai-va-cdc-dma-0-tx {
|
||||
compatible = "qcom,msm-dai-cdc-dma-dev";
|
||||
qcom,msm-dai-cdc-dma-dev-id = <45089>;
|
||||
};
|
||||
|
||||
va_cdc_dma_1_tx: qcom,msm-dai-va-cdc-dma-1-tx {
|
||||
compatible = "qcom,msm-dai-cdc-dma-dev";
|
||||
qcom,msm-dai-cdc-dma-dev-id = <45091>;
|
||||
};
|
||||
|
||||
va_cdc_dma_2_tx: qcom,msm-dai-va-cdc-dma-2-tx {
|
||||
compatible = "qcom,msm-dai-cdc-dma-dev";
|
||||
qcom,msm-dai-cdc-dma-dev-id = <45093>;
|
||||
};
|
||||
|
||||
rx_cdc_dma_0_rx: qcom,msm-dai-rx-cdc-dma-0-rx {
|
||||
compatible = "qcom,msm-dai-cdc-dma-dev";
|
||||
qcom,msm-dai-cdc-dma-dev-id = <45104>;
|
||||
};
|
||||
|
||||
rx_cdc_dma_1_rx: qcom,msm-dai-rx-cdc-dma-1-rx {
|
||||
compatible = "qcom,msm-dai-cdc-dma-dev";
|
||||
qcom,msm-dai-cdc-dma-dev-id = <45106>;
|
||||
};
|
||||
|
||||
rx_cdc_dma_2_rx: qcom,msm-dai-rx-cdc-dma-2-rx {
|
||||
compatible = "qcom,msm-dai-cdc-dma-dev";
|
||||
qcom,msm-dai-cdc-dma-dev-id = <45108>;
|
||||
};
|
||||
|
||||
rx_cdc_dma_3_rx: qcom,msm-dai-rx-cdc-dma-3-rx {
|
||||
compatible = "qcom,msm-dai-cdc-dma-dev";
|
||||
qcom,msm-dai-cdc-dma-dev-id = <45110>;
|
||||
};
|
||||
|
||||
rx_cdc_dma_4_rx: qcom,msm-dai-rx-cdc-dma-4-rx {
|
||||
compatible = "qcom,msm-dai-cdc-dma-dev";
|
||||
qcom,msm-dai-cdc-dma-dev-id = <45112>;
|
||||
};
|
||||
|
||||
rx_cdc_dma_5_rx: qcom,msm-dai-rx-cdc-dma-5-rx {
|
||||
compatible = "qcom,msm-dai-cdc-dma-dev";
|
||||
qcom,msm-dai-cdc-dma-dev-id = <45114>;
|
||||
};
|
||||
|
||||
rx_cdc_dma_6_rx: qcom,msm-dai-rx-cdc-dma-6-rx {
|
||||
compatible = "qcom,msm-dai-cdc-dma-dev";
|
||||
qcom,msm-dai-cdc-dma-dev-id = <45116>;
|
||||
qcom,msm-cdc-dma-data-align = <1>;
|
||||
};
|
||||
|
||||
rx_cdc_dma_7_rx: qcom,msm-dai-rx-cdc-dma-7-rx {
|
||||
compatible = "qcom,msm-dai-cdc-dma-dev";
|
||||
qcom,msm-dai-cdc-dma-dev-id = <45118>;
|
||||
};
|
||||
|
||||
tx_cdc_dma_0_tx: qcom,msm-dai-tx-cdc-dma-0-tx {
|
||||
compatible = "qcom,msm-dai-cdc-dma-dev";
|
||||
qcom,msm-dai-cdc-dma-dev-id = <45105>;
|
||||
};
|
||||
|
||||
tx_cdc_dma_1_tx: qcom,msm-dai-tx-cdc-dma-1-tx {
|
||||
compatible = "qcom,msm-dai-cdc-dma-dev";
|
||||
qcom,msm-dai-cdc-dma-dev-id = <45107>;
|
||||
};
|
||||
|
||||
tx_cdc_dma_2_tx: qcom,msm-dai-tx-cdc-dma-2-tx {
|
||||
compatible = "qcom,msm-dai-cdc-dma-dev";
|
||||
qcom,msm-dai-cdc-dma-dev-id = <45109>;
|
||||
};
|
||||
|
||||
tx_cdc_dma_3_tx: qcom,msm-dai-tx-cdc-dma-3-tx {
|
||||
compatible = "qcom,msm-dai-cdc-dma-dev";
|
||||
qcom,msm-dai-cdc-dma-dev-id = <45111>;
|
||||
};
|
||||
|
||||
tx_cdc_dma_4_tx: qcom,msm-dai-tx-cdc-dma-4-tx {
|
||||
compatible = "qcom,msm-dai-cdc-dma-dev";
|
||||
qcom,msm-dai-cdc-dma-dev-id = <45113>;
|
||||
};
|
||||
|
||||
tx_cdc_dma_5_tx: qcom,msm-dai-tx-cdc-dma-5-tx {
|
||||
compatible = "qcom,msm-dai-cdc-dma-dev";
|
||||
qcom,msm-dai-cdc-dma-dev-id = <45115>;
|
||||
};
|
||||
};
|
||||
|
||||
lsm: qcom,msm-lsm-client {
|
||||
compatible = "qcom,msm-lsm-client";
|
||||
};
|
||||
|
||||
dai_msm_q6:qcom,msm-dai-q6 {
|
||||
compatible = "qcom,msm-dai-q6";
|
||||
sb_7_rx: qcom,msm-dai-q6-sb-7-rx {
|
||||
compatible = "qcom,msm-dai-q6-dev";
|
||||
qcom,msm-dai-q6-dev-id = <16398>;
|
||||
qcom,msm-dai-q6-slim-dev-id = <0>;
|
||||
};
|
||||
|
||||
sb_7_tx: qcom,msm-dai-q6-sb-7-tx {
|
||||
compatible = "qcom,msm-dai-q6-dev";
|
||||
qcom,msm-dai-q6-dev-id = <16399>;
|
||||
qcom,msm-dai-q6-slim-dev-id = <0>;
|
||||
};
|
||||
|
||||
sb_8_tx: qcom,msm-dai-q6-sb-8-tx {
|
||||
compatible = "qcom,msm-dai-q6-dev";
|
||||
qcom,msm-dai-q6-dev-id = <16401>;
|
||||
qcom,msm-dai-q6-slim-dev-id = <0>;
|
||||
};
|
||||
|
||||
bt_sco_rx: qcom,msm-dai-q6-bt-sco-rx {
|
||||
compatible = "qcom,msm-dai-q6-dev";
|
||||
qcom,msm-dai-q6-dev-id = <12288>;
|
||||
};
|
||||
|
||||
bt_sco_tx: qcom,msm-dai-q6-bt-sco-tx {
|
||||
compatible = "qcom,msm-dai-q6-dev";
|
||||
qcom,msm-dai-q6-dev-id = <12289>;
|
||||
};
|
||||
|
||||
int_fm_rx: qcom,msm-dai-q6-int-fm-rx {
|
||||
compatible = "qcom,msm-dai-q6-dev";
|
||||
qcom,msm-dai-q6-dev-id = <12292>;
|
||||
};
|
||||
|
||||
int_fm_tx: qcom,msm-dai-q6-int-fm-tx {
|
||||
compatible = "qcom,msm-dai-q6-dev";
|
||||
qcom,msm-dai-q6-dev-id = <12293>;
|
||||
};
|
||||
|
||||
afe_pcm_rx: qcom,msm-dai-q6-be-afe-pcm-rx {
|
||||
compatible = "qcom,msm-dai-q6-dev";
|
||||
qcom,msm-dai-q6-dev-id = <224>;
|
||||
};
|
||||
|
||||
afe_pcm_tx: qcom,msm-dai-q6-be-afe-pcm-tx {
|
||||
compatible = "qcom,msm-dai-q6-dev";
|
||||
qcom,msm-dai-q6-dev-id = <225>;
|
||||
};
|
||||
|
||||
afe_proxy_rx: qcom,msm-dai-q6-afe-proxy-rx {
|
||||
compatible = "qcom,msm-dai-q6-dev";
|
||||
qcom,msm-dai-q6-dev-id = <241>;
|
||||
};
|
||||
|
||||
afe_proxy_tx: qcom,msm-dai-q6-afe-proxy-tx {
|
||||
compatible = "qcom,msm-dai-q6-dev";
|
||||
qcom,msm-dai-q6-dev-id = <240>;
|
||||
};
|
||||
|
||||
incall_record_rx: qcom,msm-dai-q6-incall-record-rx {
|
||||
compatible = "qcom,msm-dai-q6-dev";
|
||||
qcom,msm-dai-q6-dev-id = <32771>;
|
||||
};
|
||||
|
||||
incall_record_tx: qcom,msm-dai-q6-incall-record-tx {
|
||||
compatible = "qcom,msm-dai-q6-dev";
|
||||
qcom,msm-dai-q6-dev-id = <32772>;
|
||||
};
|
||||
|
||||
incall_music_rx: qcom,msm-dai-q6-incall-music-rx {
|
||||
compatible = "qcom,msm-dai-q6-dev";
|
||||
qcom,msm-dai-q6-dev-id = <32773>;
|
||||
};
|
||||
|
||||
incall_music_2_rx: qcom,msm-dai-q6-incall-music-2-rx {
|
||||
compatible = "qcom,msm-dai-q6-dev";
|
||||
qcom,msm-dai-q6-dev-id = <32770>;
|
||||
};
|
||||
|
||||
qcom,msm-dai-q6-afe-proxy-tx-1 {
|
||||
compatible = "qcom,msm-dai-q6-dev";
|
||||
qcom,msm-dai-q6-dev-id = <242>;
|
||||
};
|
||||
|
||||
proxy_rx: qcom,msm-dai-q6-proxy-rx {
|
||||
compatible = "qcom,msm-dai-q6-dev";
|
||||
qcom,msm-dai-q6-dev-id = <8194>;
|
||||
};
|
||||
|
||||
proxy_tx: qcom,msm-dai-q6-proxy-tx {
|
||||
compatible = "qcom,msm-dai-q6-dev";
|
||||
qcom,msm-dai-q6-dev-id = <8195>;
|
||||
};
|
||||
|
||||
usb_audio_rx: qcom,msm-dai-q6-usb-audio-rx {
|
||||
compatible = "qcom,msm-dai-q6-dev";
|
||||
qcom,msm-dai-q6-dev-id = <28672>;
|
||||
};
|
||||
|
||||
usb_audio_tx: qcom,msm-dai-q6-usb-audio-tx {
|
||||
compatible = "qcom,msm-dai-q6-dev";
|
||||
qcom,msm-dai-q6-dev-id = <28673>;
|
||||
};
|
||||
};
|
||||
|
||||
hostless: qcom,msm-pcm-hostless {
|
||||
compatible = "qcom,msm-pcm-hostless";
|
||||
};
|
||||
|
||||
audio_apr: qcom,msm-audio-apr {
|
||||
compatible = "qcom,msm-audio-apr";
|
||||
qcom,subsys-name = "apr_adsp";
|
||||
|
||||
msm_audio_ion: qcom,msm-audio-ion {
|
||||
compatible = "qcom,msm-audio-ion";
|
||||
qcom,smmu-version = <2>;
|
||||
qcom,smmu-enabled;
|
||||
qcom,iommu-dma-addr-pool = <0x10000000 0x10000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dai_pri_auxpcm_rx: qcom,msm-pri-auxpcm_rx {
|
||||
compatible = "qcom,msm-auxpcm-dev";
|
||||
qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
|
||||
qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
|
||||
qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
|
||||
qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
|
||||
qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>;
|
||||
qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>;
|
||||
qcom,msm-cpudai-auxpcm-data = <0>, <0>;
|
||||
qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
|
||||
qcom,msm-auxpcm-interface = "primaryRx";
|
||||
qcom,msm-cpudai-afe-clk-ver = <2>;
|
||||
};
|
||||
|
||||
dai_pri_auxpcm_tx: qcom,msm-pri-auxpcm_tx {
|
||||
compatible = "qcom,msm-auxpcm-dev";
|
||||
qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
|
||||
qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
|
||||
qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
|
||||
qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
|
||||
qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>;
|
||||
qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>;
|
||||
qcom,msm-cpudai-auxpcm-data = <0>, <0>;
|
||||
qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
|
||||
qcom,msm-auxpcm-interface = "primaryTx";
|
||||
qcom,msm-cpudai-afe-clk-ver = <2>;
|
||||
};
|
||||
|
||||
dai_sec_auxpcm_rx: qcom,msm-sec-auxpcm_rx {
|
||||
compatible = "qcom,msm-auxpcm-dev";
|
||||
qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
|
||||
qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
|
||||
qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
|
||||
qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
|
||||
qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>;
|
||||
qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>;
|
||||
qcom,msm-cpudai-auxpcm-data = <0>, <0>;
|
||||
qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
|
||||
qcom,msm-auxpcm-interface = "secondaryRx";
|
||||
qcom,msm-cpudai-afe-clk-ver = <2>;
|
||||
};
|
||||
|
||||
dai_sec_auxpcm_tx: qcom,msm-sec-auxpcm_tx {
|
||||
compatible = "qcom,msm-auxpcm-dev";
|
||||
qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
|
||||
qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
|
||||
qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
|
||||
qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
|
||||
qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>;
|
||||
qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>;
|
||||
qcom,msm-cpudai-auxpcm-data = <0>, <0>;
|
||||
qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
|
||||
qcom,msm-auxpcm-interface = "secondaryTx";
|
||||
qcom,msm-cpudai-afe-clk-ver = <2>;
|
||||
};
|
||||
|
||||
dai_tert_auxpcm_rx: qcom,msm-tert-auxpcm_rx {
|
||||
compatible = "qcom,msm-auxpcm-dev";
|
||||
qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
|
||||
qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
|
||||
qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
|
||||
qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
|
||||
qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>;
|
||||
qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>;
|
||||
qcom,msm-cpudai-auxpcm-data = <0>, <0>;
|
||||
qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
|
||||
qcom,msm-auxpcm-interface = "tertiaryRx";
|
||||
qcom,msm-cpudai-afe-clk-ver = <2>;
|
||||
};
|
||||
|
||||
dai_tert_auxpcm_tx: qcom,msm-tert-auxpcm_tx {
|
||||
compatible = "qcom,msm-auxpcm-dev";
|
||||
qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
|
||||
qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
|
||||
qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
|
||||
qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
|
||||
qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>;
|
||||
qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>;
|
||||
qcom,msm-cpudai-auxpcm-data = <0>, <0>;
|
||||
qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
|
||||
qcom,msm-auxpcm-interface = "tertiaryTx";
|
||||
qcom,msm-cpudai-afe-clk-ver = <2>;
|
||||
};
|
||||
|
||||
dai_quat_auxpcm_rx: qcom,msm-quat-auxpcm_rx {
|
||||
compatible = "qcom,msm-auxpcm-dev";
|
||||
qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
|
||||
qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
|
||||
qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
|
||||
qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
|
||||
qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>;
|
||||
qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>;
|
||||
qcom,msm-cpudai-auxpcm-data = <0>, <0>;
|
||||
qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
|
||||
qcom,msm-auxpcm-interface = "quaternaryRx";
|
||||
qcom,msm-cpudai-afe-clk-ver = <2>;
|
||||
};
|
||||
|
||||
dai_quat_auxpcm_tx: qcom,msm-quat-auxpcm_tx {
|
||||
compatible = "qcom,msm-auxpcm-dev";
|
||||
qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
|
||||
qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
|
||||
qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
|
||||
qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
|
||||
qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>;
|
||||
qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>;
|
||||
qcom,msm-cpudai-auxpcm-data = <0>, <0>;
|
||||
qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
|
||||
qcom,msm-auxpcm-interface = "quaternaryTx";
|
||||
qcom,msm-cpudai-afe-clk-ver = <2>;
|
||||
};
|
||||
|
||||
dai_quin_auxpcm_rx: qcom,msm-quin-auxpcm_rx {
|
||||
compatible = "qcom,msm-auxpcm-dev";
|
||||
qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
|
||||
qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
|
||||
qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
|
||||
qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
|
||||
qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>;
|
||||
qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>;
|
||||
qcom,msm-cpudai-auxpcm-data = <0>, <0>;
|
||||
qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
|
||||
qcom,msm-auxpcm-interface = "quinaryRx";
|
||||
qcom,msm-cpudai-afe-clk-ver = <2>;
|
||||
};
|
||||
|
||||
dai_quin_auxpcm_tx: qcom,msm-quin-auxpcm_tx {
|
||||
compatible = "qcom,msm-auxpcm-dev";
|
||||
qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
|
||||
qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
|
||||
qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
|
||||
qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
|
||||
qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>;
|
||||
qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>;
|
||||
qcom,msm-cpudai-auxpcm-data = <0>, <0>;
|
||||
qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
|
||||
qcom,msm-auxpcm-interface = "quinaryTx";
|
||||
qcom,msm-cpudai-afe-clk-ver = <2>;
|
||||
};
|
||||
|
||||
|
||||
hdmi_dba: qcom,msm-hdmi-dba-codec-rx {
|
||||
compatible = "qcom,msm-hdmi-dba-codec-rx";
|
||||
qcom,dba-bridge-chip = "adv7533";
|
||||
};
|
||||
|
||||
adsp_loader: qcom,msm-adsp-loader {
|
||||
status = "ok";
|
||||
compatible = "qcom,adsp-loader";
|
||||
qcom,adsp-state = <0>;
|
||||
};
|
||||
|
||||
adsp_notify: qcom,msm-adsp-notify {
|
||||
status = "ok";
|
||||
compatible = "qcom,adsp-notify";
|
||||
};
|
||||
|
||||
qcom,msm-dai-tdm-pri-rx {
|
||||
compatible = "qcom,msm-dai-tdm";
|
||||
qcom,msm-cpudai-tdm-group-id = <37120>;
|
||||
qcom,msm-cpudai-tdm-group-num-ports = <1>;
|
||||
qcom,msm-cpudai-tdm-group-port-id = <36864>;
|
||||
qcom,msm-cpudai-tdm-clk-rate = <1536000>;
|
||||
qcom,msm-cpudai-tdm-clk-internal = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-mode = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-src = <1>;
|
||||
qcom,msm-cpudai-tdm-data-out = <0>;
|
||||
qcom,msm-cpudai-tdm-invert-sync = <1>;
|
||||
qcom,msm-cpudai-tdm-data-delay = <1>;
|
||||
qcom,msm-dai-q6-tdm-pri-rx-0 {
|
||||
compatible = "qcom,msm-dai-q6-tdm";
|
||||
qcom,msm-cpudai-tdm-dev-id = <36864>;
|
||||
qcom,msm-cpudai-tdm-data-align = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,msm-dai-tdm-pri-tx {
|
||||
compatible = "qcom,msm-dai-tdm";
|
||||
qcom,msm-cpudai-tdm-group-id = <37121>;
|
||||
qcom,msm-cpudai-tdm-group-num-ports = <1>;
|
||||
qcom,msm-cpudai-tdm-group-port-id = <36865>;
|
||||
qcom,msm-cpudai-tdm-clk-rate = <1536000>;
|
||||
qcom,msm-cpudai-tdm-clk-internal = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-mode = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-src = <1>;
|
||||
qcom,msm-cpudai-tdm-data-out = <0>;
|
||||
qcom,msm-cpudai-tdm-invert-sync = <1>;
|
||||
qcom,msm-cpudai-tdm-data-delay = <1>;
|
||||
qcom,msm-dai-q6-tdm-pri-tx-0 {
|
||||
compatible = "qcom,msm-dai-q6-tdm";
|
||||
qcom,msm-cpudai-tdm-dev-id = <36865>;
|
||||
qcom,msm-cpudai-tdm-data-align = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,msm-dai-tdm-sec-rx {
|
||||
compatible = "qcom,msm-dai-tdm";
|
||||
qcom,msm-cpudai-tdm-group-id = <37136>;
|
||||
qcom,msm-cpudai-tdm-group-num-ports = <1>;
|
||||
qcom,msm-cpudai-tdm-group-port-id = <36880>;
|
||||
qcom,msm-cpudai-tdm-clk-rate = <1536000>;
|
||||
qcom,msm-cpudai-tdm-clk-internal = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-mode = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-src = <1>;
|
||||
qcom,msm-cpudai-tdm-data-out = <0>;
|
||||
qcom,msm-cpudai-tdm-invert-sync = <1>;
|
||||
qcom,msm-cpudai-tdm-data-delay = <1>;
|
||||
qcom,msm-dai-q6-tdm-sec-rx-0 {
|
||||
compatible = "qcom,msm-dai-q6-tdm";
|
||||
qcom,msm-cpudai-tdm-dev-id = <36880>;
|
||||
qcom,msm-cpudai-tdm-data-align = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,msm-dai-tdm-sec-tx {
|
||||
compatible = "qcom,msm-dai-tdm";
|
||||
qcom,msm-cpudai-tdm-group-id = <37137>;
|
||||
qcom,msm-cpudai-tdm-group-num-ports = <1>;
|
||||
qcom,msm-cpudai-tdm-group-port-id = <36881>;
|
||||
qcom,msm-cpudai-tdm-clk-rate = <1536000>;
|
||||
qcom,msm-cpudai-tdm-clk-internal = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-mode = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-src = <1>;
|
||||
qcom,msm-cpudai-tdm-data-out = <0>;
|
||||
qcom,msm-cpudai-tdm-invert-sync = <1>;
|
||||
qcom,msm-cpudai-tdm-data-delay = <1>;
|
||||
qcom,msm-dai-q6-tdm-sec-tx-0 {
|
||||
compatible = "qcom,msm-dai-q6-tdm";
|
||||
qcom,msm-cpudai-tdm-dev-id = <36881>;
|
||||
qcom,msm-cpudai-tdm-data-align = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,msm-dai-tdm-tert-rx {
|
||||
compatible = "qcom,msm-dai-tdm";
|
||||
qcom,msm-cpudai-tdm-group-id = <37152>;
|
||||
qcom,msm-cpudai-tdm-group-num-ports = <1>;
|
||||
qcom,msm-cpudai-tdm-group-port-id = <36896>;
|
||||
qcom,msm-cpudai-tdm-clk-rate = <1536000>;
|
||||
qcom,msm-cpudai-tdm-clk-internal = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-mode = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-src = <1>;
|
||||
qcom,msm-cpudai-tdm-data-out = <0>;
|
||||
qcom,msm-cpudai-tdm-invert-sync = <1>;
|
||||
qcom,msm-cpudai-tdm-data-delay = <1>;
|
||||
qcom,msm-dai-q6-tdm-tert-rx-0 {
|
||||
compatible = "qcom,msm-dai-q6-tdm";
|
||||
qcom,msm-cpudai-tdm-dev-id = <36896>;
|
||||
qcom,msm-cpudai-tdm-data-align = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,msm-dai-tdm-tert-tx {
|
||||
compatible = "qcom,msm-dai-tdm";
|
||||
qcom,msm-cpudai-tdm-group-id = <37153>;
|
||||
qcom,msm-cpudai-tdm-group-num-ports = <1>;
|
||||
qcom,msm-cpudai-tdm-group-port-id = <36897 >;
|
||||
qcom,msm-cpudai-tdm-clk-rate = <1536000>;
|
||||
qcom,msm-cpudai-tdm-clk-internal = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-mode = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-src = <1>;
|
||||
qcom,msm-cpudai-tdm-data-out = <0>;
|
||||
qcom,msm-cpudai-tdm-invert-sync = <1>;
|
||||
qcom,msm-cpudai-tdm-data-delay = <1>;
|
||||
qcom,msm-dai-q6-tdm-tert-tx-0 {
|
||||
compatible = "qcom,msm-dai-q6-tdm";
|
||||
qcom,msm-cpudai-tdm-dev-id = <36897 >;
|
||||
qcom,msm-cpudai-tdm-data-align = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,msm-dai-tdm-quat-rx {
|
||||
compatible = "qcom,msm-dai-tdm";
|
||||
qcom,msm-cpudai-tdm-group-id = <37168>;
|
||||
qcom,msm-cpudai-tdm-group-num-ports = <1>;
|
||||
qcom,msm-cpudai-tdm-group-port-id = <36912>;
|
||||
qcom,msm-cpudai-tdm-clk-rate = <1536000>;
|
||||
qcom,msm-cpudai-tdm-clk-internal = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-mode = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-src = <1>;
|
||||
qcom,msm-cpudai-tdm-data-out = <0>;
|
||||
qcom,msm-cpudai-tdm-invert-sync = <1>;
|
||||
qcom,msm-cpudai-tdm-data-delay = <1>;
|
||||
qcom,msm-dai-q6-tdm-quat-rx-0 {
|
||||
compatible = "qcom,msm-dai-q6-tdm";
|
||||
qcom,msm-cpudai-tdm-dev-id = <36912>;
|
||||
qcom,msm-cpudai-tdm-data-align = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,msm-dai-tdm-quat-tx {
|
||||
compatible = "qcom,msm-dai-tdm";
|
||||
qcom,msm-cpudai-tdm-group-id = <37169>;
|
||||
qcom,msm-cpudai-tdm-group-num-ports = <1>;
|
||||
qcom,msm-cpudai-tdm-group-port-id = <36913 >;
|
||||
qcom,msm-cpudai-tdm-clk-rate = <1536000>;
|
||||
qcom,msm-cpudai-tdm-clk-internal = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-mode = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-src = <1>;
|
||||
qcom,msm-cpudai-tdm-data-out = <0>;
|
||||
qcom,msm-cpudai-tdm-invert-sync = <1>;
|
||||
qcom,msm-cpudai-tdm-data-delay = <1>;
|
||||
qcom,msm-dai-q6-tdm-quat-tx-0 {
|
||||
compatible = "qcom,msm-dai-q6-tdm";
|
||||
qcom,msm-cpudai-tdm-dev-id = <36913 >;
|
||||
qcom,msm-cpudai-tdm-data-align = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,msm-dai-tdm-quin-rx {
|
||||
compatible = "qcom,msm-dai-tdm";
|
||||
qcom,msm-cpudai-tdm-group-id = <37184>;
|
||||
qcom,msm-cpudai-tdm-group-num-ports = <1>;
|
||||
qcom,msm-cpudai-tdm-group-port-id = <36928>;
|
||||
qcom,msm-cpudai-tdm-clk-rate = <1536000>;
|
||||
qcom,msm-cpudai-tdm-clk-internal = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-mode = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-src = <1>;
|
||||
qcom,msm-cpudai-tdm-data-out = <0>;
|
||||
qcom,msm-cpudai-tdm-invert-sync = <1>;
|
||||
qcom,msm-cpudai-tdm-data-delay = <1>;
|
||||
qcom,msm-dai-q6-tdm-quin-rx-0 {
|
||||
compatible = "qcom,msm-dai-q6-tdm";
|
||||
qcom,msm-cpudai-tdm-dev-id = <36928>;
|
||||
qcom,msm-cpudai-tdm-data-align = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,msm-dai-tdm-quin-tx {
|
||||
compatible = "qcom,msm-dai-tdm";
|
||||
qcom,msm-cpudai-tdm-group-id = <37185>;
|
||||
qcom,msm-cpudai-tdm-group-num-ports = <1>;
|
||||
qcom,msm-cpudai-tdm-group-port-id = <36929>;
|
||||
qcom,msm-cpudai-tdm-clk-rate = <1536000>;
|
||||
qcom,msm-cpudai-tdm-clk-internal = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-mode = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-src = <1>;
|
||||
qcom,msm-cpudai-tdm-data-out = <0>;
|
||||
qcom,msm-cpudai-tdm-invert-sync = <1>;
|
||||
qcom,msm-cpudai-tdm-data-delay = <1>;
|
||||
qcom,msm-dai-q6-tdm-quin-tx-0 {
|
||||
compatible = "qcom,msm-dai-q6-tdm";
|
||||
qcom,msm-cpudai-tdm-dev-id = <36929>;
|
||||
qcom,msm-cpudai-tdm-data-align = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
tdm_sen_rx: qcom,msm-dai-tdm-sen-rx {
|
||||
compatible = "qcom,msm-dai-tdm";
|
||||
qcom,msm-cpudai-tdm-group-id = <37200>;
|
||||
qcom,msm-cpudai-tdm-group-num-ports = <1>;
|
||||
qcom,msm-cpudai-tdm-group-port-id = <36944>;
|
||||
qcom,msm-cpudai-tdm-clk-rate = <1536000>;
|
||||
qcom,msm-cpudai-tdm-clk-internal = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-mode = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-src = <1>;
|
||||
qcom,msm-cpudai-tdm-data-out = <0>;
|
||||
qcom,msm-cpudai-tdm-invert-sync = <1>;
|
||||
qcom,msm-cpudai-tdm-data-delay = <1>;
|
||||
dai_sen_tdm_rx_0: qcom,msm-dai-q6-tdm-sen-rx-0 {
|
||||
compatible = "qcom,msm-dai-q6-tdm";
|
||||
qcom,msm-cpudai-tdm-dev-id = <36944>;
|
||||
qcom,msm-cpudai-tdm-data-align = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
tdm_sen_tx: qcom,msm-dai-tdm-sen-tx {
|
||||
compatible = "qcom,msm-dai-tdm";
|
||||
qcom,msm-cpudai-tdm-group-id = <37201>;
|
||||
qcom,msm-cpudai-tdm-group-num-ports = <1>;
|
||||
qcom,msm-cpudai-tdm-group-port-id = <36945>;
|
||||
qcom,msm-cpudai-tdm-clk-rate = <1536000>;
|
||||
qcom,msm-cpudai-tdm-clk-internal = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-mode = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-src = <1>;
|
||||
qcom,msm-cpudai-tdm-data-out = <0>;
|
||||
qcom,msm-cpudai-tdm-invert-sync = <1>;
|
||||
qcom,msm-cpudai-tdm-data-delay = <1>;
|
||||
dai_sen_tdm_tx_0: qcom,msm-dai-q6-tdm-sen-tx-0 {
|
||||
compatible = "qcom,msm-dai-q6-tdm";
|
||||
qcom,msm-cpudai-tdm-dev-id = <36945>;
|
||||
qcom,msm-cpudai-tdm-data-align = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
tdm_sep_rx: qcom,msm-dai-tdm-sep-rx {
|
||||
compatible = "qcom,msm-dai-tdm";
|
||||
qcom,msm-cpudai-tdm-group-id = <37216>;
|
||||
qcom,msm-cpudai-tdm-group-num-ports = <1>;
|
||||
qcom,msm-cpudai-tdm-group-port-id = <36960>;
|
||||
qcom,msm-cpudai-tdm-clk-rate = <1536000>;
|
||||
qcom,msm-cpudai-tdm-clk-internal = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-mode = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-src = <1>;
|
||||
qcom,msm-cpudai-tdm-data-out = <0>;
|
||||
qcom,msm-cpudai-tdm-invert-sync = <1>;
|
||||
qcom,msm-cpudai-tdm-data-delay = <1>;
|
||||
dai_sep_tdm_rx_0: qcom,msm-dai-q6-tdm-sep-rx-0 {
|
||||
compatible = "qcom,msm-dai-q6-tdm";
|
||||
qcom,msm-cpudai-tdm-dev-id = <36960>;
|
||||
qcom,msm-cpudai-tdm-data-align = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
tdm_sep_tx: qcom,msm-dai-tdm-sep-tx {
|
||||
compatible = "qcom,msm-dai-tdm";
|
||||
qcom,msm-cpudai-tdm-group-id = <37217>;
|
||||
qcom,msm-cpudai-tdm-group-num-ports = <1>;
|
||||
qcom,msm-cpudai-tdm-group-port-id = <36961>;
|
||||
qcom,msm-cpudai-tdm-clk-rate = <1536000>;
|
||||
qcom,msm-cpudai-tdm-clk-internal = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-mode = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-src = <1>;
|
||||
qcom,msm-cpudai-tdm-data-out = <0>;
|
||||
qcom,msm-cpudai-tdm-invert-sync = <1>;
|
||||
qcom,msm-cpudai-tdm-data-delay = <1>;
|
||||
dai_sep_tdm_tx_0: qcom,msm-dai-q6-tdm-sep-tx-0 {
|
||||
compatible = "qcom,msm-dai-q6-tdm";
|
||||
qcom,msm-cpudai-tdm-dev-id = <36961>;
|
||||
qcom,msm-cpudai-tdm-data-align = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
tdm_hsif0_rx: qcom,msm-dai-tdm-hsif0-rx {
|
||||
compatible = "qcom,msm-dai-tdm";
|
||||
qcom,msm-cpudai-tdm-group-id = <37232>;
|
||||
qcom,msm-cpudai-tdm-group-num-ports = <1>;
|
||||
qcom,msm-cpudai-tdm-group-port-id = <36976>;
|
||||
qcom,msm-cpudai-tdm-clk-rate = <1536000>;
|
||||
qcom,msm-cpudai-tdm-clk-internal = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-mode = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-src = <1>;
|
||||
qcom,msm-cpudai-tdm-data-out = <0>;
|
||||
qcom,msm-cpudai-tdm-invert-sync = <1>;
|
||||
qcom,msm-cpudai-tdm-data-delay = <1>;
|
||||
dai_hsif0_tdm_rx_0: qcom,msm-dai-q6-tdm-hsif0-rx-0 {
|
||||
compatible = "qcom,msm-dai-q6-tdm";
|
||||
qcom,msm-cpudai-tdm-dev-id = <36976>;
|
||||
qcom,msm-cpudai-tdm-data-align = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
tdm_hsif0_tx: qcom,msm-dai-tdm-hsif0-tx {
|
||||
compatible = "qcom,msm-dai-tdm";
|
||||
qcom,msm-cpudai-tdm-group-id = <37231>;
|
||||
qcom,msm-cpudai-tdm-group-num-ports = <1>;
|
||||
qcom,msm-cpudai-tdm-group-port-id = <36977>;
|
||||
qcom,msm-cpudai-tdm-clk-rate = <1536000>;
|
||||
qcom,msm-cpudai-tdm-clk-internal = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-mode = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-src = <1>;
|
||||
qcom,msm-cpudai-tdm-data-out = <0>;
|
||||
qcom,msm-cpudai-tdm-invert-sync = <1>;
|
||||
qcom,msm-cpudai-tdm-data-delay = <1>;
|
||||
dai_hsif0_tdm_tx_0: qcom,msm-dai-q6-tdm-hsif0-tx-0 {
|
||||
compatible = "qcom,msm-dai-q6-tdm";
|
||||
qcom,msm-cpudai-tdm-dev-id = <36977>;
|
||||
qcom,msm-cpudai-tdm-data-align = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
tdm_hsif1_rx: qcom,msm-dai-tdm-hsif1-rx {
|
||||
compatible = "qcom,msm-dai-tdm";
|
||||
qcom,msm-cpudai-tdm-group-id = <37248>;
|
||||
qcom,msm-cpudai-tdm-group-num-ports = <1>;
|
||||
qcom,msm-cpudai-tdm-group-port-id = <36992>;
|
||||
qcom,msm-cpudai-tdm-clk-rate = <1536000>;
|
||||
qcom,msm-cpudai-tdm-clk-internal = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-mode = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-src = <1>;
|
||||
qcom,msm-cpudai-tdm-data-out = <0>;
|
||||
qcom,msm-cpudai-tdm-invert-sync = <1>;
|
||||
qcom,msm-cpudai-tdm-data-delay = <1>;
|
||||
dai_hsif1_tdm_rx_0: qcom,msm-dai-q6-tdm-hsif1-rx-0 {
|
||||
compatible = "qcom,msm-dai-q6-tdm";
|
||||
qcom,msm-cpudai-tdm-dev-id = <36992>;
|
||||
qcom,msm-cpudai-tdm-data-align = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
tdm_hsif1_tx: qcom,msm-dai-tdm-hsif1-tx {
|
||||
compatible = "qcom,msm-dai-tdm";
|
||||
qcom,msm-cpudai-tdm-group-id = <37249>;
|
||||
qcom,msm-cpudai-tdm-group-num-ports = <1>;
|
||||
qcom,msm-cpudai-tdm-group-port-id = <36993>;
|
||||
qcom,msm-cpudai-tdm-clk-rate = <1536000>;
|
||||
qcom,msm-cpudai-tdm-clk-internal = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-mode = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-src = <1>;
|
||||
qcom,msm-cpudai-tdm-data-out = <0>;
|
||||
qcom,msm-cpudai-tdm-invert-sync = <1>;
|
||||
qcom,msm-cpudai-tdm-data-delay = <1>;
|
||||
dai_hsif1_tdm_tx_0: qcom,msm-dai-q6-tdm-hsif1-tx-0 {
|
||||
compatible = "qcom,msm-dai-q6-tdm";
|
||||
qcom,msm-cpudai-tdm-dev-id = <36993>;
|
||||
qcom,msm-cpudai-tdm-data-align = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
tdm_hsif2_rx: qcom,msm-dai-tdm-hsif2-rx {
|
||||
compatible = "qcom,msm-dai-tdm";
|
||||
qcom,msm-cpudai-tdm-group-id = <37264>;
|
||||
qcom,msm-cpudai-tdm-group-num-ports = <1>;
|
||||
qcom,msm-cpudai-tdm-group-port-id = <37008>;
|
||||
qcom,msm-cpudai-tdm-clk-rate = <1536000>;
|
||||
qcom,msm-cpudai-tdm-clk-internal = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-mode = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-src = <1>;
|
||||
qcom,msm-cpudai-tdm-data-out = <0>;
|
||||
qcom,msm-cpudai-tdm-invert-sync = <1>;
|
||||
qcom,msm-cpudai-tdm-data-delay = <1>;
|
||||
dai_hsif2_tdm_rx_0: qcom,msm-dai-q6-tdm-hsif2-rx-0 {
|
||||
compatible = "qcom,msm-dai-q6-tdm";
|
||||
qcom,msm-cpudai-tdm-dev-id = <37008>;
|
||||
qcom,msm-cpudai-tdm-data-align = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
tdm_hsif2_tx: qcom,msm-dai-tdm-hsif2-tx {
|
||||
compatible = "qcom,msm-dai-tdm";
|
||||
qcom,msm-cpudai-tdm-group-id = <37265>;
|
||||
qcom,msm-cpudai-tdm-group-num-ports = <1>;
|
||||
qcom,msm-cpudai-tdm-group-port-id = <37009>;
|
||||
qcom,msm-cpudai-tdm-clk-rate = <1536000>;
|
||||
qcom,msm-cpudai-tdm-clk-internal = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-mode = <1>;
|
||||
qcom,msm-cpudai-tdm-sync-src = <1>;
|
||||
qcom,msm-cpudai-tdm-data-out = <0>;
|
||||
qcom,msm-cpudai-tdm-invert-sync = <1>;
|
||||
qcom,msm-cpudai-tdm-data-delay = <1>;
|
||||
dai_hsif2_tdm_tx_0: qcom,msm-dai-q6-tdm-hsif2-tx-0 {
|
||||
compatible = "qcom,msm-dai-q6-tdm";
|
||||
qcom,msm-cpudai-tdm-dev-id = <37009>;
|
||||
qcom,msm-cpudai-tdm-data-align = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
dai_pri_spdif_rx: qcom,msm-dai-q6-spdif-pri-rx {
|
||||
compatible = "qcom,msm-dai-q6-spdif";
|
||||
qcom,msm-dai-q6-dev-id = <20480>;
|
||||
};
|
||||
|
||||
dai_pri_spdif_tx: qcom,msm-dai-q6-spdif-pri-tx {
|
||||
compatible = "qcom,msm-dai-q6-spdif";
|
||||
qcom,msm-dai-q6-dev-id = <20481>;
|
||||
};
|
||||
|
||||
dai_sec_spdif_rx: qcom,msm-dai-q6-spdif-sec-rx {
|
||||
compatible = "qcom,msm-dai-q6-spdif";
|
||||
qcom,msm-dai-q6-dev-id = <20482>;
|
||||
};
|
||||
|
||||
dai_sec_spdif_tx: qcom,msm-dai-q6-spdif-sec-tx {
|
||||
compatible = "qcom,msm-dai-q6-spdif";
|
||||
qcom,msm-dai-q6-dev-id = <20483>;
|
||||
};
|
||||
|
||||
afe_loopback_tx: qcom,msm-dai-q6-afe-loopback-tx {
|
||||
compatible = "qcom,msm-dai-q6-dev";
|
||||
qcom,msm-dai-q6-dev-id = <24577>;
|
||||
};
|
||||
};
|
||||
15
qcom/audio/pineapple-audio-atp.dts
Normal file
15
qcom/audio/pineapple-audio-atp.dts
Normal file
@@ -0,0 +1,15 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "pineapple-audio-atp.dtsi"
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Pineapple ATP";
|
||||
compatible = "qcom,pineapple-atp", "qcom,pineapple", "qcom,atp";
|
||||
qcom,msm-id = <557 0x10000>, <557 0x20000>, <577 0x10000>, <577 0x20000>;
|
||||
qcom,board-id = <0x10021 0>;
|
||||
};
|
||||
82
qcom/audio/pineapple-audio-atp.dtsi
Normal file
82
qcom/audio/pineapple-audio-atp.dtsi
Normal file
@@ -0,0 +1,82 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "pineapple-audio-mtp.dtsi"
|
||||
|
||||
&swr_haptics {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pineapple_snd {
|
||||
asoc-codec = <&stub_codec>, <&lpass_cdc>,
|
||||
<&wcd939x_codec>, <&wsa884x_0220>,
|
||||
<&wsa884x_0221>;
|
||||
asoc-codec-names = "msm-stub-codec.1", "lpass-cdc",
|
||||
"wcd939x_codec", "wsa-codec1", "wsa-codec2";
|
||||
swr-haptics-unsupported;
|
||||
qcom,audio-routing =
|
||||
"AMIC1", "Analog Mic1",
|
||||
"AMIC1", "MIC BIAS1",
|
||||
"AMIC2", "Analog Mic2",
|
||||
"AMIC2", "MIC BIAS2",
|
||||
"AMIC3", "Analog Mic3",
|
||||
"AMIC3", "MIC BIAS3",
|
||||
"AMIC4", "Analog Mic4",
|
||||
"AMIC4", "MIC BIAS3",
|
||||
"AMIC5", "Analog Mic5",
|
||||
"AMIC5", "MIC BIAS4",
|
||||
"VA AMIC1", "Analog Mic1",
|
||||
"VA AMIC1", "VA MIC BIAS1",
|
||||
"VA AMIC2", "Analog Mic2",
|
||||
"VA AMIC2", "VA MIC BIAS2",
|
||||
"VA AMIC3", "Analog Mic3",
|
||||
"VA AMIC3", "VA MIC BIAS3",
|
||||
"VA AMIC4", "Analog Mic4",
|
||||
"VA AMIC4", "VA MIC BIAS3",
|
||||
"VA AMIC5", "Analog Mic5",
|
||||
"VA AMIC5", "VA MIC BIAS4",
|
||||
"TX DMIC0", "Digital Mic0",
|
||||
"TX DMIC0", "MIC BIAS3",
|
||||
"TX DMIC1", "Digital Mic1",
|
||||
"TX DMIC1", "MIC BIAS3",
|
||||
"TX DMIC2", "Digital Mic2",
|
||||
"TX DMIC2", "MIC BIAS1",
|
||||
"TX DMIC3", "Digital Mic3",
|
||||
"TX DMIC3", "MIC BIAS1",
|
||||
"IN1_HPHL", "HPHL_OUT",
|
||||
"IN2_HPHR", "HPHR_OUT",
|
||||
"IN3_EAR", "AUX_OUT",
|
||||
"WSA SRC0_INP", "SRC0",
|
||||
"WSA_TX DEC0_INP", "TX DEC0 MUX",
|
||||
"WSA_TX DEC1_INP", "TX DEC1 MUX",
|
||||
"RX_TX DEC0_INP", "TX DEC0 MUX",
|
||||
"RX_TX DEC1_INP", "TX DEC1 MUX",
|
||||
"RX_TX DEC2_INP", "TX DEC2 MUX",
|
||||
"RX_TX DEC3_INP", "TX DEC3 MUX",
|
||||
"SpkrLeft IN", "WSA_SPK1 OUT",
|
||||
"SpkrRight IN", "WSA_SPK2 OUT",
|
||||
"TX SWR_INPUT", "WCD_TX_OUTPUT",
|
||||
"VA SWR_INPUT", "VA_SWR_CLK",
|
||||
"VA SWR_INPUT", "WCD_TX_OUTPUT",
|
||||
"VA_AIF1 CAP", "VA_SWR_CLK",
|
||||
"VA_AIF2 CAP", "VA_SWR_CLK",
|
||||
"VA_AIF3 CAP", "VA_SWR_CLK",
|
||||
"VA DMIC0", "Digital Mic0",
|
||||
"VA DMIC1", "Digital Mic1",
|
||||
"VA DMIC2", "Digital Mic2",
|
||||
"VA DMIC3", "Digital Mic3",
|
||||
"VA DMIC0", "VA MIC BIAS3",
|
||||
"VA DMIC1", "VA MIC BIAS3",
|
||||
"VA DMIC2", "VA MIC BIAS1",
|
||||
"VA DMIC3", "VA MIC BIAS1";
|
||||
};
|
||||
|
||||
&wsa_macro {
|
||||
qcom,wsa-bat-cfgs= <4>, <4>;
|
||||
};
|
||||
|
||||
&wsa2_macro {
|
||||
qcom,wsa-bat-cfgs= <4>, <4>;
|
||||
};
|
||||
16
qcom/audio/pineapple-audio-cdp-nfc.dts
Normal file
16
qcom/audio/pineapple-audio-cdp-nfc.dts
Normal file
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "pineapple-audio-cdp-nfc.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Pineapple CDP ST54L NFC";
|
||||
compatible = "qcom,pineapple-cdp", "qcom,pineapple", "qcom,pineapplep-cdp", "qcom,pineapplep", "qcom,cdp";
|
||||
qcom,msm-id = <557 0x10000>, <557 0x20000>, <577 0x10000>, <577 0x20000>;
|
||||
qcom,board-id = <0x50001 0>;
|
||||
};
|
||||
6
qcom/audio/pineapple-audio-cdp-nfc.dtsi
Normal file
6
qcom/audio/pineapple-audio-cdp-nfc.dtsi
Normal file
@@ -0,0 +1,6 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "pineapple-audio-cdp.dtsi"
|
||||
15
qcom/audio/pineapple-audio-cdp.dts
Normal file
15
qcom/audio/pineapple-audio-cdp.dts
Normal file
@@ -0,0 +1,15 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "pineapple-audio-cdp.dtsi"
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Pineapple CDP";
|
||||
compatible = "qcom,pineapple-cdp", "qcom,pineapple", "qcom,cdp";
|
||||
qcom,msm-id = <557 0x10000>, <557 0x20000>, <577 0x10000>, <577 0x20000>;
|
||||
qcom,board-id = <1 0>;
|
||||
};
|
||||
149
qcom/audio/pineapple-audio-cdp.dtsi
Normal file
149
qcom/audio/pineapple-audio-cdp.dtsi
Normal file
@@ -0,0 +1,149 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "pineapple-audio-overlay.dtsi"
|
||||
|
||||
&lpass_cdc {
|
||||
qcom,num-macros = <4>;
|
||||
};
|
||||
|
||||
&wsa2_macro {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&swr_dmic_01 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&swr_dmic_02 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&swr_dmic_03 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&swr_dmic_04 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cdc_pri_mi2s_gpios {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&fm_i2s1_gpios {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&cdc_tert_mi2s_gpios {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cdc_quat_mi2s_gpios {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cdc_quin_mi2s_gpios {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cdc_sen_mi2s_gpios {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cdc_sep_mi2s_gpios {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pineapple_snd {
|
||||
qcom,model = "pineapple-cdp-snd-card";
|
||||
qcom,audio-routing =
|
||||
"AMIC1", "Analog Mic1",
|
||||
"AMIC1", "MIC BIAS1",
|
||||
"AMIC2", "Analog Mic2",
|
||||
"AMIC2", "MIC BIAS2",
|
||||
"AMIC3", "Analog Mic3",
|
||||
"AMIC3", "MIC BIAS1",
|
||||
"AMIC4", "Analog Mic4",
|
||||
"AMIC4", "MIC BIAS3",
|
||||
"AMIC5", "Analog Mic5",
|
||||
"AMIC5", "MIC BIAS4",
|
||||
"VA AMIC1", "Analog Mic1",
|
||||
"VA AMIC1", "VA MIC BIAS1",
|
||||
"VA AMIC2", "Analog Mic2",
|
||||
"VA AMIC2", "VA MIC BIAS2",
|
||||
"VA AMIC3", "Analog Mic3",
|
||||
"VA AMIC3", "VA MIC BIAS1",
|
||||
"VA AMIC4", "Analog Mic4",
|
||||
"VA AMIC4", "VA MIC BIAS3",
|
||||
"VA AMIC5", "Analog Mic5",
|
||||
"VA AMIC5", "VA MIC BIAS4",
|
||||
"TX DMIC0", "Digital Mic0",
|
||||
"TX DMIC0", "MIC BIAS1",
|
||||
"TX DMIC1", "Digital Mic1",
|
||||
"TX DMIC1", "MIC BIAS1",
|
||||
"TX DMIC2", "Digital Mic2",
|
||||
"TX DMIC2", "MIC BIAS1",
|
||||
"TX DMIC3", "Digital Mic3",
|
||||
"TX DMIC3", "MIC BIAS1",
|
||||
"TX DMIC4", "Digital Mic4",
|
||||
"TX DMIC4", "MIC BIAS3",
|
||||
"TX DMIC5", "Digital Mic5",
|
||||
"TX DMIC5", "MIC BIAS3",
|
||||
"TX DMIC6", "Digital Mic6",
|
||||
"TX DMIC6", "MIC BIAS4",
|
||||
"TX DMIC7", "Digital Mic7",
|
||||
"TX DMIC7", "MIC BIAS4",
|
||||
"IN1_HPHL", "HPHL_OUT",
|
||||
"IN2_HPHR", "HPHR_OUT",
|
||||
"IN3_EAR", "AUX_OUT",
|
||||
"WSA SRC0_INP", "SRC0",
|
||||
"WSA_TX DEC0_INP", "TX DEC0 MUX",
|
||||
"WSA_TX DEC1_INP", "TX DEC1 MUX",
|
||||
"RX_TX DEC0_INP", "TX DEC0 MUX",
|
||||
"RX_TX DEC1_INP", "TX DEC1 MUX",
|
||||
"RX_TX DEC2_INP", "TX DEC2 MUX",
|
||||
"RX_TX DEC3_INP", "TX DEC3 MUX",
|
||||
"SpkrLeft IN", "WSA_SPK1 OUT",
|
||||
"SpkrRight IN", "WSA_SPK2 OUT",
|
||||
"TX SWR_INPUT", "WCD_TX_OUTPUT",
|
||||
"VA SWR_INPUT", "VA_SWR_CLK",
|
||||
"VA SWR_INPUT", "WCD_TX_OUTPUT",
|
||||
"VA_AIF1 CAP", "VA_SWR_CLK",
|
||||
"VA_AIF2 CAP", "VA_SWR_CLK",
|
||||
"VA_AIF3 CAP", "VA_SWR_CLK",
|
||||
"VA DMIC0", "Digital Mic0",
|
||||
"VA DMIC1", "Digital Mic1",
|
||||
"VA DMIC2", "Digital Mic2",
|
||||
"VA DMIC3", "Digital Mic3",
|
||||
"VA DMIC4", "Digital Mic4",
|
||||
"VA DMIC5", "Digital Mic5",
|
||||
"VA DMIC6", "Digital Mic6",
|
||||
"VA DMIC7", "Digital Mic7",
|
||||
"VA DMIC0", "VA MIC BIAS1",
|
||||
"VA DMIC1", "VA MIC BIAS1",
|
||||
"VA DMIC2", "VA MIC BIAS1",
|
||||
"VA DMIC3", "VA MIC BIAS1",
|
||||
"VA DMIC4", "VA MIC BIAS3",
|
||||
"VA DMIC5", "VA MIC BIAS3",
|
||||
"VA DMIC6", "VA MIC BIAS4",
|
||||
"VA DMIC7", "VA MIC BIAS4";
|
||||
qcom,cdc-dmic67-gpios = <&cdc_dmic67_gpios>;
|
||||
asoc-codec = <&stub_codec>, <&lpass_cdc>,
|
||||
<&wcd939x_codec>, <&swr_haptics>,
|
||||
<&wsa884x_0220>, <&wsa884x_0221>;
|
||||
asoc-codec-names = "msm-stub-codec.1", "lpass-cdc",
|
||||
"wcd939x_codec", "swr-haptics",
|
||||
"wsa-codec1", "wsa-codec2";
|
||||
qcom,wsa-max-devs = <2>;
|
||||
qcom,pri-mi2s-gpios = <&cdc_pri_mi2s_gpios>;
|
||||
qcom,sec-mi2s-gpios = <&fm_i2s1_gpios>;
|
||||
qcom,tert-mi2s-gpios = <&cdc_tert_mi2s_gpios>;
|
||||
qcom,quat-mi2s-gpios = <&cdc_quat_mi2s_gpios>;
|
||||
qcom,quin-mi2s-gpios = <&cdc_quin_mi2s_gpios>;
|
||||
qcom,sen-mi2s-gpios = <&cdc_sen_mi2s_gpios>;
|
||||
qcom,sep-mi2s-gpios = <&cdc_sep_mi2s_gpios>;
|
||||
qcom,usbss-hsj-connect-enabled;
|
||||
};
|
||||
16
qcom/audio/pineapple-audio-mtp-nfc.dts
Normal file
16
qcom/audio/pineapple-audio-mtp-nfc.dts
Normal file
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "pineapple-audio-mtp-nfc.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Pineapple MTP ST54L NFC";
|
||||
compatible = "qcom,pineapple-mtp", "qcom,pineapple", "qcom,pineapplep-mtp", "qcom,pineapplep", "qcom,mtp";
|
||||
qcom,msm-id = <557 0x10000>, <557 0x20000>, <577 0x10000>, <577 0x20000>;
|
||||
qcom,board-id = <0x50008 0>;
|
||||
};
|
||||
6
qcom/audio/pineapple-audio-mtp-nfc.dtsi
Normal file
6
qcom/audio/pineapple-audio-mtp-nfc.dtsi
Normal file
@@ -0,0 +1,6 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "pineapple-audio-overlay.dtsi"
|
||||
15
qcom/audio/pineapple-audio-mtp.dts
Normal file
15
qcom/audio/pineapple-audio-mtp.dts
Normal file
@@ -0,0 +1,15 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "pineapple-audio-mtp.dtsi"
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Pineapple MTP";
|
||||
compatible = "qcom,pineapple-mtp", "qcom,pineapple", "qcom,mtp";
|
||||
qcom,msm-id = <557 0x10000>, <557 0x20000>, <577 0x10000>, <577 0x20000>;
|
||||
qcom,board-id = <8 0>;
|
||||
};
|
||||
14
qcom/audio/pineapple-audio-mtp.dtsi
Normal file
14
qcom/audio/pineapple-audio-mtp.dtsi
Normal file
@@ -0,0 +1,14 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "pineapple-audio-overlay.dtsi"
|
||||
|
||||
&fm_i2s1_gpios {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&pineapple_snd {
|
||||
qcom,sec-mi2s-gpios = <&fm_i2s1_gpios>;
|
||||
};
|
||||
812
qcom/audio/pineapple-audio-overlay.dtsi
Normal file
812
qcom/audio/pineapple-audio-overlay.dtsi
Normal file
@@ -0,0 +1,812 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <bindings/qcom,audio-ext-clk.h>
|
||||
#include <bindings/qcom,lpass-cdc-clk-rsc.h>
|
||||
#include <bindings/audio-codec-port-types.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include "pineapple-lpi.dtsi"
|
||||
|
||||
&lpass_cdc {
|
||||
qcom,num-macros = <4>;
|
||||
qcom,lpass-cdc-version = <7>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
lpass-cdc-clk-rsc-mngr {
|
||||
compatible = "qcom,lpass-cdc-clk-rsc-mngr";
|
||||
qcom,fs-gen-sequence = <0x3000 0x1 0x1>, <0x3004 0x3 0x3>,
|
||||
<0x3004 0x3 0x1>, <0x3080 0x2 0x2>;
|
||||
qcom,rx_mclk_mode_muxsel = <0x06BEC0D8>;
|
||||
qcom,wsa_mclk_mode_muxsel = <0x06BEA100>;
|
||||
qcom,va_mclk_mode_muxsel = <0x06E28000>;
|
||||
clock-names = "tx_core_clk", "rx_core_clk", "wsa_core_clk",
|
||||
"wsa2_core_clk", "rx_tx_core_clk",
|
||||
"wsa_tx_core_clk", "wsa2_tx_core_clk", "va_core_clk";
|
||||
clocks = <&clock_audio_tx_1 0>, <&clock_audio_rx_1 0>,
|
||||
<&clock_audio_wsa_1 0>,
|
||||
<&clock_audio_wsa_2 0>, <&clock_audio_rx_tx 0>,
|
||||
<&clock_audio_wsa_tx 0>, <&clock_audio_wsa2_tx 0>,
|
||||
<&clock_audio_va_1 0>;
|
||||
};
|
||||
|
||||
va_macro: va-macro@6D44000 {
|
||||
compatible = "qcom,lpass-cdc-va-macro";
|
||||
reg = <0x6D44000 0x0>;
|
||||
clock-names = "lpass_audio_hw_vote";
|
||||
clocks = <&lpass_audio_hw_vote 0>;
|
||||
qcom,va-dmic-sample-rate = <600000>;
|
||||
qcom,va-clk-mux-select = <1>;
|
||||
qcom,va-island-mode-muxsel = <0x06E28000>;
|
||||
qcom,default-clk-id = <TX_CORE_CLK>;
|
||||
qcom,use-clk-id = <VA_CORE_CLK>;
|
||||
qcom,is-used-swr-gpio = <1>;
|
||||
qcom,va-swr-gpios = <&va_swr_gpios>;
|
||||
swr2: va_swr_master {
|
||||
compatible = "qcom,swr-mstr";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "lpass_core_hw_vote",
|
||||
"lpass_audio_hw_vote";
|
||||
clocks = <&lpass_core_hw_vote 0>,
|
||||
<&lpass_audio_hw_vote 0>;
|
||||
qcom,swr_master_id = <3>;
|
||||
qcom,mipi-sdw-block-packing-mode = <1>;
|
||||
swrm-io-base = <0x6d30000 0x0>;
|
||||
interrupts =
|
||||
<GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "swr_master_irq", "swr_wake_irq";
|
||||
qcom,swr-wakeup-required = <1>;
|
||||
qcom,swr-num-ports = <5>;
|
||||
qcom,swr-port-mapping = <1 SWRM_TX_PCM_OUT 0x3>,
|
||||
<2 SWRM_TX1_CH1 0x1>, <2 SWRM_TX1_CH2 0x2>,
|
||||
<2 SWRM_TX1_CH3 0x4>, <2 SWRM_TX1_CH4 0x8>,
|
||||
<3 SWRM_TX2_CH1 0x1>, <3 SWRM_TX2_CH2 0x2>,
|
||||
<3 SWRM_TX2_CH3 0x4>, <3 SWRM_TX2_CH4 0x8>,
|
||||
<4 SWRM_TX3_CH1 0x1>, <4 SWRM_TX3_CH2 0x2>,
|
||||
<4 SWRM_TX3_CH3 0x4>, <4 SWRM_TX3_CH4 0x8>,
|
||||
<5 SWRM_TX_PCM_IN 0x3>;
|
||||
qcom,swr-num-dev = <5>;
|
||||
qcom,swr-clock-stop-mode0 = <1>;
|
||||
qcom,swr-mstr-irq-wakeup-capable = <1>;
|
||||
qcom,is-always-on = <1>;
|
||||
wcd939x_tx_slave: wcd939x-tx-slave {
|
||||
compatible = "qcom,wcd939x-slave";
|
||||
reg = <0x0E 0x01170223>;
|
||||
};
|
||||
|
||||
swr_dmic_04: dmic_swr@58350223 {
|
||||
compatible = "qcom,swr-dmic";
|
||||
reg = <0x08 0x58350223>;
|
||||
sound-name-prefix = "SWR_MIC3";
|
||||
qcom,codec-name = "swr-dmic.04";
|
||||
qcom,swr-dmic-supply = <3>;
|
||||
qcom,wcd-handle = <&wcd939x_codec>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
swr_dmic_03: dmic_swr@58350222 {
|
||||
compatible = "qcom,swr-dmic";
|
||||
reg = <0x08 0x58350222>;
|
||||
sound-name-prefix = "SWR_MIC2";
|
||||
qcom,codec-name = "swr-dmic.03";
|
||||
qcom,swr-dmic-supply = <1>;
|
||||
qcom,wcd-handle = <&wcd939x_codec>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
swr_dmic_02: dmic_swr@58350221 {
|
||||
compatible = "qcom,swr-dmic";
|
||||
reg = <0x08 0x58350221>;
|
||||
sound-name-prefix = "SWR_MIC1";
|
||||
qcom,codec-name = "swr-dmic.02";
|
||||
qcom,swr-dmic-supply = <1>;
|
||||
qcom,wcd-handle = <&wcd939x_codec>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
swr_dmic_01: dmic_swr@58350220 {
|
||||
compatible = "qcom,swr-dmic";
|
||||
reg = <0x08 0x58350220>;
|
||||
sound-name-prefix = "SWR_MIC0";
|
||||
qcom,codec-name = "swr-dmic.01";
|
||||
qcom,swr-dmic-supply = <3>;
|
||||
qcom,wcd-handle = <&wcd939x_codec>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tx_macro: tx-macro@6AE0000 {
|
||||
compatible = "qcom,lpass-cdc-tx-macro";
|
||||
reg = <0x6AE0000 0x0>;
|
||||
qcom,default-clk-id = <TX_CORE_CLK>;
|
||||
qcom,tx-dmic-sample-rate = <2400000>;
|
||||
qcom,is-used-swr-gpio = <0>;
|
||||
};
|
||||
|
||||
rx_macro: rx-macro@6AC0000 {
|
||||
compatible = "qcom,lpass-cdc-rx-macro";
|
||||
reg = <0x6AC0000 0x0>;
|
||||
qcom,rx-swr-gpios = <&rx_swr_gpios>;
|
||||
qcom,rx_mclk_mode_muxsel = <0x06BEC0D8>;
|
||||
qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x03 0x48>;
|
||||
qcom,default-clk-id = <RX_TX_CORE_CLK>;
|
||||
clock-names = "rx_mclk2_2x_clk";
|
||||
clocks = <&clock_audio_rx_mclk2_2x_clk 0>;
|
||||
swr1: rx_swr_master {
|
||||
compatible = "qcom,swr-mstr";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "lpass_core_hw_vote",
|
||||
"lpass_audio_hw_vote";
|
||||
clocks = <&lpass_core_hw_vote 0>,
|
||||
<&lpass_audio_hw_vote 0>;
|
||||
qcom,swr_master_id = <2>;
|
||||
qcom,mipi-sdw-block-packing-mode = <1>;
|
||||
swrm-io-base = <0x6ad0000 0x0>;
|
||||
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "swr_master_irq";
|
||||
qcom,swr-num-ports = <12>;
|
||||
qcom,swr-port-mapping = <1 HPH_L 0x1>,
|
||||
<1 HPH_R 0x2>, <2 CLSH 0x3>,
|
||||
<3 COMP_L 0x1>, <3 COMP_R 0x2>,
|
||||
<4 LO 0x1>, <5 DSD_L 0x1>,
|
||||
<5 DSD_R 0x2>, <6 PCM_OUT1 0x01>,
|
||||
<7 GPPO 0x03>, <8 HAPT 0x03>,
|
||||
<9 HIFI_PCM_L 0x01>, <9 HIFI_PCM_R 0x2>,
|
||||
<10 HPTH 0x03>, <11 CMPT 0x03>, <12 IPCM 0x03>;
|
||||
qcom,swr-num-dev = <2>;
|
||||
qcom,swr-clock-stop-mode0 = <1>;
|
||||
swr_haptics: swr_haptics@f0170220 {
|
||||
compatible = "qcom,pm8550b-swr-haptics";
|
||||
reg = <0x02 0xf0170220>;
|
||||
swr-slave-supply = <&hap_swr_slave_reg>;
|
||||
qcom,rx_swr_ch_map = <0 0x01 0x01 0 PCM_OUT1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wcd939x_rx_slave: wcd939x-rx-slave {
|
||||
compatible = "qcom,wcd939x-slave";
|
||||
reg = <0x0E 0x01170224>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
wsa_macro: wsa-macro@6B00000 {
|
||||
compatible = "qcom,lpass-cdc-wsa-macro";
|
||||
reg = <0x6B00000 0x0>;
|
||||
wsa_data_fs_ctl_reg = <0x6B6F000>;
|
||||
qcom,wsa-swr-gpios = <&wsa_swr_gpios>;
|
||||
qcom,wsa-bat-cfgs= <1>, <1>;
|
||||
qcom,wsa-rloads= <2>, <2>;
|
||||
qcom,wsa-system-gains= <0 9>, <0 9>;
|
||||
qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x03 0x48>;
|
||||
qcom,default-clk-id = <WSA_TX_CORE_CLK>;
|
||||
qcom,thermal-max-state = <11>;
|
||||
qcom,noise-gate-mode = <2>;
|
||||
#cooling-cells = <2>;
|
||||
swr0: wsa_swr_master {
|
||||
compatible = "qcom,swr-mstr";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "lpass_core_hw_vote",
|
||||
"lpass_audio_hw_vote";
|
||||
clocks = <&lpass_core_hw_vote 0>,
|
||||
<&lpass_audio_hw_vote 0>;
|
||||
qcom,swr_master_id = <1>;
|
||||
qcom,mipi-sdw-block-packing-mode = <0>;
|
||||
swrm-io-base = <0x6b10000 0x0>;
|
||||
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "swr_master_irq";
|
||||
qcom,swr-num-ports = <13>;
|
||||
qcom,swr-clock-stop-mode0 = <1>;
|
||||
qcom,swr-port-mapping = <1 SPKR_L 0x1>,
|
||||
<2 SPKR_L_COMP 0xF>, <3 SPKR_L_BOOST 0x3>,
|
||||
<4 SPKR_R 0x1>, <5 SPKR_R_COMP 0xF>,
|
||||
<6 SPKR_R_BOOST 0x3>, <7 PBR 0x3>,
|
||||
<8 SPKR_HAPT 0x3>, <9 OCPM 0x3>,
|
||||
<10 SPKR_L_VI 0x3>, <11 SPKR_R_VI 0x3>,
|
||||
<12 SPKR_IPCM 0x3>, <13 CPS 0x3>;
|
||||
qcom,swr-num-dev = <2>;
|
||||
qcom,dynamic-port-map-supported = <0>;
|
||||
wsa884x_0220: wsa884x@02170220 {
|
||||
compatible = "qcom,wsa884x";
|
||||
reg = <0x4 0x2170220>;
|
||||
qcom,spkr-sd-n-node = <&wsa_spkr_en02>;
|
||||
qcom,lpass-cdc-handle = <&lpass_cdc>;
|
||||
qcom,wsa-macro-handle = <&wsa_macro>;
|
||||
qcom,swr-wsa-port-params =
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>, <OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>, <OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>, <OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>, <OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>;
|
||||
cdc-vdd-1p8-supply = <&L15B>;
|
||||
qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-1p8-current = <20000>;
|
||||
qcom,cdc-vdd-1p8-lpm-supported = <1>;
|
||||
qcom,cdc-static-supplies = "cdc-vdd-1p8";
|
||||
sound-name-prefix = "SpkrLeft";
|
||||
};
|
||||
|
||||
wsa884x_0221: wsa884x@02170221 {
|
||||
compatible = "qcom,wsa884x";
|
||||
reg = <0x4 0x2170221>;
|
||||
qcom,spkr-sd-n-node = <&wsa_spkr_en13>;
|
||||
qcom,lpass-cdc-handle = <&lpass_cdc>;
|
||||
qcom,wsa-macro-handle = <&wsa_macro>;
|
||||
qcom,swr-wsa-port-params =
|
||||
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>, <OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>, <OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>,
|
||||
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>, <OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>, <OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>,
|
||||
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>, <OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>, <OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>,
|
||||
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>, <OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>, <OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>;
|
||||
cdc-vdd-1p8-supply = <&L15B>;
|
||||
qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-1p8-current = <20000>;
|
||||
qcom,cdc-vdd-1p8-lpm-supported = <1>;
|
||||
qcom,cdc-static-supplies = "cdc-vdd-1p8";
|
||||
sound-name-prefix = "SpkrRight";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
wsa2_macro: wsa2-macro@6AA0000 {
|
||||
compatible = "qcom,lpass-cdc-wsa2-macro";
|
||||
reg = <0x6AA0000 0x0>;
|
||||
wsa_data_fs_ctl_reg = <0x6B6F000>;
|
||||
qcom,wsa2-swr-gpios = <&wsa2_swr_gpios>;
|
||||
qcom,wsa-bat-cfgs= <1>, <1>;
|
||||
qcom,wsa-rloads= <2>, <2>;
|
||||
qcom,wsa-system-gains= <0 9>, <0 9>;
|
||||
qcom,wsa2-bcl-pmic-params = /bits/ 8 <0x00 0x03 0x48>;
|
||||
qcom,default-clk-id = <WSA2_TX_CORE_CLK>;
|
||||
qcom,thermal-max-state = <11>;
|
||||
qcom,noise-gate-mode = <2>;
|
||||
#cooling-cells = <2>;
|
||||
status = "disabled";
|
||||
swr3: wsa2_swr_master {
|
||||
compatible = "qcom,swr-mstr";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "lpass_core_hw_vote",
|
||||
"lpass_audio_hw_vote";
|
||||
clocks = <&lpass_core_hw_vote 0>,
|
||||
<&lpass_audio_hw_vote 0>;
|
||||
qcom,swr_master_id = <4>;
|
||||
qcom,mipi-sdw-block-packing-mode = <0>;
|
||||
swrm-io-base = <0x6ab0000 0x0>;
|
||||
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "swr_master_irq";
|
||||
qcom,swr-num-ports = <13>;
|
||||
qcom,swr-clock-stop-mode0 = <1>;
|
||||
qcom,swr-port-mapping = <1 SPKR_L 0x1>,
|
||||
<2 SPKR_L_COMP 0xF>, <3 SPKR_L_BOOST 0x3>,
|
||||
<4 SPKR_R 0x1>, <5 SPKR_R_COMP 0xF>,
|
||||
<6 SPKR_R_BOOST 0x3>, <7 PBR 0x3>,
|
||||
<8 SPKR_HAPT 0x3>, <9 OCPM 0x3>,
|
||||
<10 SPKR_L_VI 0x3>, <11 SPKR_R_VI 0x3>,
|
||||
<12 SPKR_IPCM 0x3>, <13 CPS 0x3>;
|
||||
qcom,swr-num-dev = <2>;
|
||||
qcom,dynamic-port-map-supported = <0>;
|
||||
wsa884x_2_0220: wsa884x@02170220 {
|
||||
compatible = "qcom,wsa884x_2";
|
||||
reg = <0x4 0x2170220>;
|
||||
qcom,spkr-sd-n-node = <&wsa_spkr_en02>;
|
||||
qcom,lpass-cdc-handle = <&lpass_cdc>;
|
||||
qcom,wsa-macro-handle = <&wsa2_macro>;
|
||||
qcom,swr-wsa-port-params =
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>, <OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>, <OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>, <OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>, <OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>;
|
||||
cdc-vdd-1p8-supply = <&L15B>;
|
||||
qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-1p8-current = <20000>;
|
||||
qcom,cdc-vdd-1p8-lpm-supported = <1>;
|
||||
qcom,cdc-static-supplies = "cdc-vdd-1p8";
|
||||
sound-name-prefix = "Spkr2Left";
|
||||
};
|
||||
|
||||
wsa884x_2_0221: wsa884x@02170221 {
|
||||
compatible = "qcom,wsa884x_2";
|
||||
reg = <0x4 0x2170221>;
|
||||
qcom,spkr-sd-n-node = <&wsa_spkr_en13>;
|
||||
qcom,lpass-cdc-handle = <&lpass_cdc>;
|
||||
qcom,wsa-macro-handle = <&wsa2_macro>;
|
||||
qcom,swr-wsa-port-params =
|
||||
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>, <OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>, <OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>,
|
||||
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>, <OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>, <OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>,
|
||||
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>, <OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>, <OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>,
|
||||
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>, <OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>, <OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>;
|
||||
cdc-vdd-1p8-supply = <&L15B>;
|
||||
qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-1p8-current = <20000>;
|
||||
qcom,cdc-vdd-1p8-lpm-supported = <1>;
|
||||
qcom,cdc-static-supplies = "cdc-vdd-1p8";
|
||||
sound-name-prefix = "Spkr2Right";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
wcd939x_codec: wcd939x-codec {
|
||||
compatible = "qcom,wcd939x-codec";
|
||||
qcom,split-codec = <1>;
|
||||
qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
|
||||
<0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>,
|
||||
<2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
|
||||
<3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
|
||||
<4 DSD_R 0x2 0 DSD_R>, <5 HIFI_PCM_L 0x1 0 HIFI_PCM_L>,
|
||||
<5 HIFI_PCM_R 0x2 0 HIFI_PCM_R>;
|
||||
|
||||
qcom,tx_swr_ch_map = <0 ADC1 0x1 0 SWRM_TX1_CH1>,
|
||||
<0 ADC2 0x2 0 SWRM_TX1_CH2>,
|
||||
<1 ADC3 0x1 0 SWRM_TX1_CH3>,
|
||||
<1 ADC4 0x2 0 SWRM_TX1_CH4>,
|
||||
<2 DMIC0 0x1 0 SWRM_TX2_CH1>,
|
||||
<2 DMIC1 0x2 0 SWRM_TX2_CH2>,
|
||||
<2 MBHC 0x4 0 SWRM_TX2_CH3>,
|
||||
<2 DMIC2 0x4 0 SWRM_TX2_CH3>,
|
||||
<2 DMIC3 0x8 0 SWRM_TX2_CH4>,
|
||||
<3 DMIC4 0x1 0 SWRM_TX3_CH1>,
|
||||
<3 DMIC5 0x2 0 SWRM_TX3_CH2>,
|
||||
<3 DMIC6 0x4 0 SWRM_TX3_CH3>,
|
||||
<3 DMIC7 0x8 0 SWRM_TX3_CH4>;
|
||||
|
||||
qcom,swr-tx-port-params =
|
||||
<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL0 LANE2>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,
|
||||
<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,
|
||||
<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL2 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>;
|
||||
|
||||
qcom,wcd-rst-gpio-node = <&wcd939x_rst_gpio>;
|
||||
qcom,rx-slave = <&wcd939x_rx_slave>;
|
||||
qcom,tx-slave = <&wcd939x_tx_slave>;
|
||||
|
||||
cdc-vdd-rx-supply = <&L15B>;
|
||||
qcom,cdc-vdd-rx-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-rx-current = <30000>;
|
||||
qcom,cdc-vdd-rx-lpm-supported = <1>;
|
||||
|
||||
cdc-vdd-tx-supply = <&L15B>;
|
||||
qcom,cdc-vdd-tx-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-tx-current = <30000>;
|
||||
qcom,cdc-vdd-tx-lpm-supported = <1>;
|
||||
|
||||
cdc-vdd-buck-supply = <&L15B>;
|
||||
qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-buck-current = <650000>;
|
||||
qcom,cdc-vdd-buck-lpm-supported = <1>;
|
||||
|
||||
cdc-vdd-mic-bias-supply = <&BOB1>;
|
||||
qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>;
|
||||
qcom,cdc-vdd-mic-bias-current = <30000>;
|
||||
|
||||
cdc-vdd-px-supply = <&L3C>;
|
||||
qcom,cdc-vdd-px-voltage = <1200000 1200000>;
|
||||
qcom,cdc-vdd-px-current = <5000>;
|
||||
qcom,cdc-vdd-px-lpm-supported = <1>;
|
||||
|
||||
qcom,cdc-vdd-px-rem-supported = <1>;
|
||||
|
||||
qcom,cdc-micbias1-mv = <1800>;
|
||||
qcom,cdc-micbias2-mv = <1800>;
|
||||
qcom,cdc-micbias3-mv = <1800>;
|
||||
qcom,cdc-micbias4-mv = <1800>;
|
||||
|
||||
qcom,cdc-static-supplies = "cdc-vdd-rx",
|
||||
"cdc-vdd-tx",
|
||||
"cdc-vdd-mic-bias";
|
||||
qcom,cdc-on-demand-supplies = "cdc-vdd-buck",
|
||||
"cdc-vdd-px";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&spf_core_platform {
|
||||
pineapple_snd: sound {
|
||||
qcom,model = "pineapple-mtp-snd-card";
|
||||
qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>, <1>, <1>;
|
||||
qcom,mi2s-tdm-is-hw-vote-needed = <1>, <1>, <1>, <1>, <1>, <1>, <1>;
|
||||
qcom,wcn-bt = <1>;
|
||||
qcom,ext-disp-audio-rx = <0>;
|
||||
qcom,tdm-max-slots = <8>;
|
||||
qcom,tdm-clk-attribute = <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>;
|
||||
qcom,mi2s-clk-attribute = <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>;
|
||||
qcom,audio-core-list = <0>, <1>;
|
||||
qcom,audio-routing =
|
||||
"AMIC1", "Analog Mic1",
|
||||
"AMIC1", "MIC BIAS1",
|
||||
"AMIC2", "Analog Mic2",
|
||||
"AMIC2", "MIC BIAS2",
|
||||
"AMIC3", "Analog Mic3",
|
||||
"AMIC3", "MIC BIAS3",
|
||||
"AMIC4", "Analog Mic4",
|
||||
"AMIC4", "MIC BIAS3",
|
||||
"AMIC5", "Analog Mic5",
|
||||
"AMIC5", "MIC BIAS4",
|
||||
"VA AMIC1", "Analog Mic1",
|
||||
"VA AMIC1", "VA MIC BIAS1",
|
||||
"VA AMIC2", "Analog Mic2",
|
||||
"VA AMIC2", "VA MIC BIAS2",
|
||||
"VA AMIC3", "Analog Mic3",
|
||||
"VA AMIC3", "VA MIC BIAS3",
|
||||
"VA AMIC4", "Analog Mic4",
|
||||
"VA AMIC4", "VA MIC BIAS3",
|
||||
"VA AMIC5", "Analog Mic5",
|
||||
"VA AMIC5", "VA MIC BIAS4",
|
||||
"TX DMIC0", "Digital Mic0",
|
||||
"TX DMIC0", "MIC BIAS3",
|
||||
"TX DMIC1", "Digital Mic1",
|
||||
"TX DMIC1", "MIC BIAS3",
|
||||
"TX DMIC2", "Digital Mic2",
|
||||
"TX DMIC2", "MIC BIAS1",
|
||||
"TX DMIC3", "Digital Mic3",
|
||||
"TX DMIC3", "MIC BIAS1",
|
||||
"IN1_HPHL", "HPHL_OUT",
|
||||
"IN2_HPHR", "HPHR_OUT",
|
||||
"IN3_EAR", "AUX_OUT",
|
||||
"WSA SRC0_INP", "SRC0",
|
||||
"WSA_TX DEC0_INP", "TX DEC0 MUX",
|
||||
"WSA_TX DEC1_INP", "TX DEC1 MUX",
|
||||
"RX_TX DEC0_INP", "TX DEC0 MUX",
|
||||
"RX_TX DEC1_INP", "TX DEC1 MUX",
|
||||
"RX_TX DEC2_INP", "TX DEC2 MUX",
|
||||
"RX_TX DEC3_INP", "TX DEC3 MUX",
|
||||
"SpkrLeft IN", "WSA_SPK1 OUT",
|
||||
"SpkrRight IN", "WSA_SPK2 OUT",
|
||||
"TX SWR_INPUT", "WCD_TX_OUTPUT",
|
||||
"VA SWR_INPUT", "VA_SWR_CLK",
|
||||
"VA SWR_INPUT", "WCD_TX_OUTPUT",
|
||||
"VA_AIF1 CAP", "VA_SWR_CLK",
|
||||
"VA_AIF2 CAP", "VA_SWR_CLK",
|
||||
"VA_AIF3 CAP", "VA_SWR_CLK",
|
||||
"VA DMIC0", "Digital Mic0",
|
||||
"VA DMIC1", "Digital Mic1",
|
||||
"VA DMIC2", "Digital Mic2",
|
||||
"VA DMIC3", "Digital Mic3",
|
||||
"VA DMIC0", "VA MIC BIAS3",
|
||||
"VA DMIC1", "VA MIC BIAS3",
|
||||
"VA DMIC2", "VA MIC BIAS1",
|
||||
"VA DMIC3", "VA MIC BIAS1";
|
||||
qcom,msm-mbhc-usbc-audio-supported = <0>;
|
||||
qcom,msm-mbhc-hphl-swh = <1>;
|
||||
qcom,msm-mbhc-gnd-swh = <1>;
|
||||
|
||||
qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>;
|
||||
qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>;
|
||||
qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>;
|
||||
asoc-codec = <&stub_codec>, <&lpass_cdc>,
|
||||
<&wcd939x_codec>, <&swr_haptics>,
|
||||
<&wsa884x_0220>, <&wsa884x_0221>;
|
||||
asoc-codec-names = "msm-stub-codec.1", "lpass-cdc",
|
||||
"wcd939x_codec", "swr-haptics",
|
||||
"wsa-codec1", "wsa-codec2";
|
||||
qcom,wsa-max-devs = <2>;
|
||||
qcom,msm_audio_ssr_devs = <&audio_gpr>, <&lpi_tlmm>,
|
||||
<&lpass_cdc>;
|
||||
|
||||
/*
|
||||
* ====================
|
||||
* UPD backend - WSA
|
||||
* ====================
|
||||
*
|
||||
* Mute/Unmute the interpolator
|
||||
* ------------------------------
|
||||
* Register: LPASS_WSA_CDC_RX0_RX_PATH_MIX_CTL - 0x6B00418
|
||||
*
|
||||
* Send control commands to the peripheral from the soundwire controller
|
||||
* -----------------------------------------------------------------------
|
||||
* Register: LPASS_WSA_SWR_MSTR_WSA_SWRM_CPUn_CMD_FIFO_WR_CMD - 0x6B14020
|
||||
*
|
||||
* Enable/Disable ear piece
|
||||
* --------------------------
|
||||
* Register: DIG_CTRL0_PA_FSM_EN - 0x3430
|
||||
*
|
||||
*/
|
||||
qcom,upd_backends_used = "wsa";
|
||||
qcom,upd_lpass_reg_addr = <0x6B00418 0x6B14020>;
|
||||
qcom,upd_ear_pa_reg_addr = <0x3430>;
|
||||
|
||||
/*
|
||||
* ====================
|
||||
* UPD backend - WCD
|
||||
* ====================
|
||||
*
|
||||
* Mute/Unmute the interpolator
|
||||
* ------------------------------
|
||||
* Register: LPASS_WCD_CDC_RX0_RX_PATH_MIX_CTL - 0x6AC0418
|
||||
*
|
||||
* Send control commands to the wcd from the soundwire controller
|
||||
* ----------------------------------------------------------------
|
||||
* Register: LPASS_WCD_SWR_MSTR_WSA_SWRM_CPUn_CMD_FIFO_WR_CMD - 0x6D34020
|
||||
*
|
||||
* Enable/Disable ear piece
|
||||
* --------------------------
|
||||
* Register: DIG_CTRL0_PA_FSM_EN - 0x300A
|
||||
*
|
||||
*/
|
||||
/*
|
||||
qcom,upd_backends_used = "wcd";
|
||||
qcom,upd_lpass_reg_addr = <0x6AC0418 0x6D34020>;
|
||||
qcom,upd_ear_pa_reg_addr = <0x300A>;
|
||||
*/
|
||||
};
|
||||
|
||||
cdc_pri_mi2s_gpios: pri_mi2s_pinctrl {
|
||||
status = "disabled";
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&i2s0_sck_active &i2s0_ws_active
|
||||
&i2s0_sd0_active &i2s0_sd1_active>;
|
||||
pinctrl-1 = <&i2s0_sck_sleep &i2s0_ws_sleep
|
||||
&i2s0_sd0_sleep &i2s0_sd1_sleep>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
fm_i2s1_gpios: fm_i2s1_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&i2s1_sck_active &i2s1_ws_active
|
||||
&i2s1_sd0_active>;
|
||||
pinctrl-1 = <&i2s1_sck_sleep &i2s1_ws_sleep
|
||||
&i2s1_sd0_sleep>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
cdc_tert_mi2s_gpios: tert_mi2s_pinctrl {
|
||||
status = "disabled";
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&lpi_i2s4_sck_active &lpi_i2s4_ws_active
|
||||
&lpi_i2s4_sd0_active &lpi_i2s4_sd1_active>;
|
||||
pinctrl-1 = <&lpi_i2s4_sck_sleep &lpi_i2s4_ws_sleep
|
||||
&lpi_i2s4_sd0_sleep &lpi_i2s4_sd1_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <185 187>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
cdc_quat_mi2s_gpios: quat_mi2s_pinctrl {
|
||||
status = "disabled";
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&quat_mi2s_sck_active &quat_mi2s_ws_active
|
||||
&quat_mi2s_sd0_active &quat_mi2s_sd1_active
|
||||
&quat_mi2s_sd2_active &quat_mi2s_sd3_active>;
|
||||
pinctrl-1 = <&quat_mi2s_sck_sleep &quat_mi2s_ws_sleep
|
||||
&quat_mi2s_sd0_sleep &quat_mi2s_sd1_sleep
|
||||
&quat_mi2s_sd2_sleep &quat_mi2s_sd3_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <166 169>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
cdc_quin_mi2s_gpios: quin_mi2s_pinctrl {
|
||||
status = "disabled";
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&lpi_i2s1_sck_active &lpi_i2s1_ws_active
|
||||
&lpi_i2s1_sd0_active &lpi_i2s1_sd1_active>;
|
||||
pinctrl-1 = <&lpi_i2s1_sck_sleep &lpi_i2s1_ws_sleep
|
||||
&lpi_i2s1_sd0_sleep &lpi_i2s1_sd1_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <171 172 174>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
cdc_sen_mi2s_gpios: sen_mi2s_pinctrl {
|
||||
status = "disabled";
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&lpi_i2s2_sck_active &lpi_i2s2_ws_active
|
||||
&lpi_i2s2_sd0_active &lpi_i2s2_sd1_active>;
|
||||
pinctrl-1 = <&lpi_i2s2_sck_sleep &lpi_i2s2_ws_sleep
|
||||
&lpi_i2s2_sd0_sleep &lpi_i2s2_sd1_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <176 181>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
cdc_sep_mi2s_gpios: sep_mi2s_pinctrl {
|
||||
status = "disabled";
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&lpi_i2s3_sck_active &lpi_i2s3_ws_active
|
||||
&lpi_i2s3_sd0_active &lpi_i2s3_sd1_active>;
|
||||
pinctrl-1 = <&lpi_i2s3_sck_sleep &lpi_i2s3_ws_sleep
|
||||
&lpi_i2s3_sd0_sleep &lpi_i2s3_sd1_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <177 182>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
wsa_swr_gpios: wsa_swr_clk_data_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&wsa_swr_clk_active &wsa_swr_data_active>;
|
||||
pinctrl-1 = <&wsa_swr_clk_sleep &wsa_swr_data_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <176>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
wsa2_swr_gpios: wsa2_swr_clk_data_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&wsa2_swr_clk_active &wsa2_swr_data_active>;
|
||||
pinctrl-1 = <&wsa2_swr_clk_sleep &wsa2_swr_data_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <181>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
rx_swr_gpios: rx_swr_clk_data_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&rx_swr_clk_active &rx_swr_data_active
|
||||
&rx_swr_data1_active>;
|
||||
pinctrl-1 = <&rx_swr_clk_sleep &rx_swr_data_sleep
|
||||
&rx_swr_data1_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <169>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
va_swr_gpios: tx_swr_clk_data_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&tx_swr_clk_active &tx_swr_data0_active
|
||||
&tx_swr_data1_active &tx_swr_data2_active>;
|
||||
pinctrl-1 = <&tx_swr_clk_sleep &tx_swr_data0_sleep
|
||||
&tx_swr_data1_sleep &tx_swr_data2_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,chip-wakeup-reg = <0xf1a6008>;
|
||||
qcom,chip-wakeup-maskbit = <7>;
|
||||
qcom,chip-wakeup-default-val = <0x1>;
|
||||
qcom,tlmm-pins = <166>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
cdc_dmic01_gpios: cdc_dmic01_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&cdc_dmic01_clk_active &cdc_dmic01_data_active>;
|
||||
pinctrl-1 = <&cdc_dmic01_clk_sleep &cdc_dmic01_data_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <171 172>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
cdc_dmic23_gpios: cdc_dmic23_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&cdc_dmic23_clk_active &cdc_dmic23_data_active>;
|
||||
pinctrl-1 = <&cdc_dmic23_clk_sleep &cdc_dmic23_data_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <174>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
cdc_dmic45_gpios: cdc_dmic45_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&cdc_dmic45_clk_active &cdc_dmic45_data_active>;
|
||||
pinctrl-1 = <&cdc_dmic45_clk_sleep &cdc_dmic45_data_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <177>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
cdc_dmic67_gpios: cdc_dmic67_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&cdc_dmic67_clk_active &cdc_dmic67_data_active>;
|
||||
pinctrl-1 = <&cdc_dmic67_clk_sleep &cdc_dmic67_data_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <182>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
wsa_spkr_en02: wsa_spkr_en1_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&spkr_02_sd_n_active>;
|
||||
pinctrl-1 = <&spkr_02_sd_n_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
};
|
||||
|
||||
wsa_spkr_en13: wsa_spkr_en2_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&spkr_13_sd_n_active>;
|
||||
pinctrl-1 = <&spkr_13_sd_n_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
};
|
||||
|
||||
wcd939x_rst_gpio: msm_cdc_pinctrl@32 {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&wcd939x_reset_active>;
|
||||
pinctrl-1 = <&wcd939x_reset_sleep>;
|
||||
};
|
||||
|
||||
clock_audio_va_1: va_core_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK>;
|
||||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||||
qcom,codec-lpass-clk-id = <0x307>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_wsa_1: wsa_core_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_2>;
|
||||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||||
qcom,codec-lpass-clk-id = <0x309>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_wsa_2: wsa2_core_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_9>;
|
||||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||||
qcom,codec-lpass-clk-id = <0x310>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_rx_1: rx_core_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_4>;
|
||||
qcom,codec-lpass-ext-clk-freq = <22579200>;
|
||||
qcom,codec-lpass-clk-id = <0x30E>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_rx_tx: rx_core_tx_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_10>;
|
||||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||||
qcom,codec-lpass-clk-id = <0x312>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_tx_1: tx_core_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_6>;
|
||||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||||
qcom,codec-lpass-clk-id = <0x30C>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_wsa_tx: wsa_core_tx_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_11>;
|
||||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||||
qcom,codec-lpass-clk-id = <0x314>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_wsa2_tx: wsa2_core_tx_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_12>;
|
||||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||||
qcom,codec-lpass-clk-id = <0x316>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_rx_mclk2_2x_clk: rx_mclk2_2x_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_13>;
|
||||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||||
qcom,codec-lpass-clk-id = <0x318>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&adsp_loader {
|
||||
status = "ok";
|
||||
};
|
||||
15
qcom/audio/pineapple-audio-qrd-sku2.dts
Normal file
15
qcom/audio/pineapple-audio-qrd-sku2.dts
Normal file
@@ -0,0 +1,15 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "pineapple-audio-qrd-sku2.dtsi"
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Pineapple QRD";
|
||||
compatible = "qcom,pineapple-qrd", "qcom,pineapple", "qcom,qrd";
|
||||
qcom,msm-id = <557 0x10000>, <557 0x20000>, <577 0x10000>, <577 0x20000>;
|
||||
qcom,board-id = <0x5000B 0>;
|
||||
};
|
||||
11
qcom/audio/pineapple-audio-qrd-sku2.dtsi
Normal file
11
qcom/audio/pineapple-audio-qrd-sku2.dtsi
Normal file
@@ -0,0 +1,11 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "pineapple-audio-qrd.dtsi"
|
||||
|
||||
&pineapple_snd {
|
||||
qcom,model = "pineapple-qrd-sku2-snd-card";
|
||||
};
|
||||
|
||||
15
qcom/audio/pineapple-audio-qrd.dts
Normal file
15
qcom/audio/pineapple-audio-qrd.dts
Normal file
@@ -0,0 +1,15 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "pineapple-audio-qrd.dtsi"
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Pineapple QRD";
|
||||
compatible = "qcom,pineapple-qrd", "qcom,pineapple", "qcom,qrd";
|
||||
qcom,msm-id = <557 0x10000>, <557 0x20000>, <577 0x10000>, <577 0x20000>;
|
||||
qcom,board-id = <0x1000B 0>, <11 0>;
|
||||
};
|
||||
108
qcom/audio/pineapple-audio-qrd.dtsi
Normal file
108
qcom/audio/pineapple-audio-qrd.dtsi
Normal file
@@ -0,0 +1,108 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "pineapple-audio-overlay.dtsi"
|
||||
&tx_swr_clk_active {
|
||||
config {
|
||||
drive-strength = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&tx_swr_data0_active {
|
||||
config {
|
||||
drive-strength = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&tx_swr_data1_active {
|
||||
config {
|
||||
drive-strength = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&tx_swr_data2_active {
|
||||
config {
|
||||
drive-strength = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&wsa_macro {
|
||||
qcom,wsa-bat-cfgs = <2>, <2>;
|
||||
};
|
||||
|
||||
&wsa2_macro {
|
||||
qcom,wsa-bat-cfgs = <2>, <2>;
|
||||
};
|
||||
|
||||
&wcd939x_codec {
|
||||
cdc-vdd-px-supply = <&L15B>;
|
||||
qcom,cdc-vdd-px-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-px-current = <650000>;
|
||||
qcom,cdc-vdd-px-lpm-supported = <1>;
|
||||
/* 0 for digital crosstalk disabled,
|
||||
* 1 for digital crosstalk with local sensed a-xtalk enabled, and
|
||||
* 2 for digital crosstalk with remote sensed a-xtalk enabled.
|
||||
*/
|
||||
qcom,usbcss-hs-xtalk-config = <2>;
|
||||
qcom,usbcss-hs-rdson = <600>;
|
||||
qcom,usbcss-hs-r2 = <7550>;
|
||||
qcom,usbcss-hs-r3 = <1>;
|
||||
qcom,usbcss-hs-r4 = <330>;
|
||||
qcom,usbcss-hs-r5 = <5>;
|
||||
qcom,usbcss-hs-r6 = <1>;
|
||||
qcom,usbcss-hs-r7 = <5>;
|
||||
qcom,usbcss-hs-lin-k-aud = <13>;
|
||||
qcom,usbcss-hs-lin-k-gnd = <13>;
|
||||
};
|
||||
|
||||
&pineapple_snd {
|
||||
qcom,model = "pineapple-qrd-snd-card";
|
||||
|
||||
qcom,audio-routing =
|
||||
"AMIC1", "Analog Mic1",
|
||||
"AMIC1", "MIC BIAS1",
|
||||
"AMIC2", "Analog Mic2",
|
||||
"AMIC2", "MIC BIAS2",
|
||||
"AMIC3", "Analog Mic3",
|
||||
"AMIC3", "MIC BIAS3",
|
||||
"AMIC4", "Analog Mic4",
|
||||
"AMIC4", "MIC BIAS3",
|
||||
"AMIC5", "Analog Mic5",
|
||||
"AMIC5", "MIC BIAS4",
|
||||
"VA AMIC1", "Analog Mic1",
|
||||
"VA AMIC1", "VA MIC BIAS1",
|
||||
"VA AMIC2", "Analog Mic2",
|
||||
"VA AMIC2", "VA MIC BIAS2",
|
||||
"VA AMIC3", "Analog Mic3",
|
||||
"VA AMIC3", "VA MIC BIAS3",
|
||||
"VA AMIC4", "Analog Mic4",
|
||||
"VA AMIC4", "VA MIC BIAS3",
|
||||
"VA AMIC5", "Analog Mic5",
|
||||
"VA AMIC5", "VA MIC BIAS4",
|
||||
"IN1_HPHL", "HPHL_OUT",
|
||||
"IN2_HPHR", "HPHR_OUT",
|
||||
"IN3_EAR", "AUX_OUT",
|
||||
"WSA SRC0_INP", "SRC0",
|
||||
"WSA_TX DEC0_INP", "TX DEC0 MUX",
|
||||
"WSA_TX DEC1_INP", "TX DEC1 MUX",
|
||||
"RX_TX DEC0_INP", "TX DEC0 MUX",
|
||||
"RX_TX DEC1_INP", "TX DEC1 MUX",
|
||||
"RX_TX DEC2_INP", "TX DEC2 MUX",
|
||||
"RX_TX DEC3_INP", "TX DEC3 MUX",
|
||||
"SpkrLeft IN", "WSA_SPK1 OUT",
|
||||
"SpkrRight IN", "WSA_SPK2 OUT",
|
||||
"TX SWR_INPUT", "WCD_TX_OUTPUT",
|
||||
"VA SWR_INPUT", "VA_SWR_CLK",
|
||||
"VA SWR_INPUT", "WCD_TX_OUTPUT",
|
||||
"VA_AIF1 CAP", "VA_SWR_CLK",
|
||||
"VA_AIF2 CAP", "VA_SWR_CLK",
|
||||
"VA_AIF3 CAP", "VA_SWR_CLK";
|
||||
|
||||
qcom,msm-mbhc-usbc-audio-supported = <1>;
|
||||
qcom,msm-mbhc-hphl-swh = <0>;
|
||||
qcom,msm-mbhc-gnd-swh = <0>;
|
||||
qcom,wcd-disable-legacy-surge;
|
||||
};
|
||||
|
||||
15
qcom/audio/pineapple-audio-rcm.dts
Normal file
15
qcom/audio/pineapple-audio-rcm.dts
Normal file
@@ -0,0 +1,15 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "pineapple-audio-cdp.dtsi"
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Pineapple RCM";
|
||||
compatible = "qcom,pineapple-rcm", "qcom,pineapple", "qcom,pineapplep-rcm", "qcom,pineapplep", "qcom,rcm";
|
||||
qcom,msm-id = <557 0x10000>, <577 0x10000>, <557 0x20000>, <577 0x20000>;
|
||||
qcom,board-id = <0x15 0>;
|
||||
};
|
||||
15
qcom/audio/pineapple-audio-rumi.dts
Normal file
15
qcom/audio/pineapple-audio-rumi.dts
Normal file
@@ -0,0 +1,15 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "pineapple-audio-rumi.dtsi"
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Pineapple RUMI";
|
||||
compatible = "qcom,pineapple-rumi", "qcom,pineapple", "qcom,rumi";
|
||||
qcom,msm-id = <557 0x10000>, <557 0x20000>, <577 0x10000>, <577 0x20000>;
|
||||
qcom,board-id = <15 0>;
|
||||
};
|
||||
12
qcom/audio/pineapple-audio-rumi.dtsi
Normal file
12
qcom/audio/pineapple-audio-rumi.dtsi
Normal file
@@ -0,0 +1,12 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "pineapple-audio-overlay.dtsi"
|
||||
|
||||
&pineapple_snd {
|
||||
compatible = "qcom,pineapple-asoc-snd-stub";
|
||||
asoc-codec = <&stub_codec>;
|
||||
asoc-codec-names = "msm-stub-codec.1";
|
||||
};
|
||||
15
qcom/audio/pineapple-audio-wsa883x-cdp.dts
Normal file
15
qcom/audio/pineapple-audio-wsa883x-cdp.dts
Normal file
@@ -0,0 +1,15 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "pineapple-audio-wsa883x-cdp.dtsi"
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Pineapple CDP - WSA883X";
|
||||
compatible = "qcom,pineapple-cdp", "qcom,pineapple", "qcom,cdp";
|
||||
qcom,msm-id = <557 0x10000>, <557 0x20000>, <577 0x10000>, <577 0x20000>;
|
||||
qcom,board-id = <0x01000001 0>;
|
||||
};
|
||||
92
qcom/audio/pineapple-audio-wsa883x-cdp.dtsi
Normal file
92
qcom/audio/pineapple-audio-wsa883x-cdp.dtsi
Normal file
@@ -0,0 +1,92 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "pineapple-audio-cdp.dtsi"
|
||||
|
||||
&pineapple_snd {
|
||||
qcom,model = "pineapple-cdp-wsa883x-snd-card";
|
||||
asoc-codec = <&stub_codec>, <&lpass_cdc>,
|
||||
<&wcd939x_codec>, <&swr_haptics>,
|
||||
<&wsa883x_0221>, <&wsa883x_0222>;
|
||||
asoc-codec-names = "msm-stub-codec.1", "lpass-cdc",
|
||||
"wcd939x_codec", "swr-haptics",
|
||||
"wsa-codec1", "wsa-codec2";
|
||||
};
|
||||
|
||||
&wsa_macro {
|
||||
qcom,wsa-bat-cfgs= <0>, <0>;
|
||||
};
|
||||
|
||||
&wsa884x_0220 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wsa884x_0221 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&swr0 {
|
||||
wsa883x_0221: wsa883x@02170221 {
|
||||
compatible = "qcom,wsa883x";
|
||||
reg = <0x2 0x2170221>;
|
||||
qcom,spkr-sd-n-node = <&wsa_spkr_en02>;
|
||||
qcom,lpass-cdc-handle = <&lpass_cdc>;
|
||||
cdc-vdd-1p8-supply = <&L15B>;
|
||||
qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-1p8-current = <20000>;
|
||||
qcom,cdc-static-supplies = "cdc-vdd-1p8";
|
||||
sound-name-prefix = "SpkrLeft";
|
||||
};
|
||||
|
||||
wsa883x_0222: wsa883x@02170222 {
|
||||
compatible = "qcom,wsa883x";
|
||||
reg = <0x2 0x2170222>;
|
||||
qcom,spkr-sd-n-node = <&wsa_spkr_en13>;
|
||||
qcom,lpass-cdc-handle = <&lpass_cdc>;
|
||||
cdc-vdd-1p8-supply = <&L15B>;
|
||||
qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-1p8-current = <20000>;
|
||||
qcom,cdc-static-supplies = "cdc-vdd-1p8";
|
||||
sound-name-prefix = "SpkrRight";
|
||||
};
|
||||
};
|
||||
|
||||
&wsa2_macro {
|
||||
qcom,wsa-bat-cfgs= <0>, <0>;
|
||||
};
|
||||
|
||||
&wsa884x_2_0220 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wsa884x_2_0221 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&swr3 {
|
||||
wsa883x_2_0221: wsa883x@02170221 {
|
||||
compatible = "qcom,wsa883x_2";
|
||||
reg = <0x2 0x2170221>;
|
||||
qcom,spkr-sd-n-node = <&wsa_spkr_en02>;
|
||||
qcom,lpass-cdc-handle = <&lpass_cdc>;
|
||||
cdc-vdd-1p8-supply = <&L15B>;
|
||||
qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-1p8-current = <20000>;
|
||||
qcom,cdc-static-supplies = "cdc-vdd-1p8";
|
||||
sound-name-prefix = "Spkr2Left";
|
||||
};
|
||||
|
||||
wsa883x_2_0222: wsa883x@02170222 {
|
||||
compatible = "qcom,wsa883x";
|
||||
reg = <0x2 0x2170222>;
|
||||
qcom,spkr-sd-n-node = <&wsa_spkr_en13>;
|
||||
qcom,lpass-cdc-handle = <&lpass_cdc>;
|
||||
cdc-vdd-1p8-supply = <&L15B>;
|
||||
qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-1p8-current = <20000>;
|
||||
qcom,cdc-static-supplies = "cdc-vdd-1p8";
|
||||
sound-name-prefix = "Spkr2Right";
|
||||
};
|
||||
};
|
||||
21
qcom/audio/pineapple-audio.dts
Normal file
21
qcom/audio/pineapple-audio.dts
Normal file
@@ -0,0 +1,21 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/clock/qcom,gcc-pineapple.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interconnect/qcom,pineapple.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
|
||||
#include "pineapple-audio.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Pineapple";
|
||||
compatible = "qcom,pineapple";
|
||||
qcom,msm-id = <557 0x10000>, <557 0x20000>, <577 0x10000>, <577 0x20000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
175
qcom/audio/pineapple-audio.dtsi
Normal file
175
qcom/audio/pineapple-audio.dtsi
Normal file
@@ -0,0 +1,175 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <bindings/qcom,audio-ext-clk.h>
|
||||
#include <bindings/qcom,gpr.h>
|
||||
#include "msm-audio-lpass.dtsi"
|
||||
|
||||
&soc {
|
||||
spf_core_platform: spf_core_platform {
|
||||
compatible = "qcom,spf-core-platform";
|
||||
};
|
||||
|
||||
lpass_core_hw_vote: vote_lpass_core_hw {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_CORE_HW_VOTE>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
lpass_audio_hw_vote: vote_lpass_audio_hw {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_AUDIO_HW_VOTE>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&glink_edge {
|
||||
audio_gpr: qcom,gpr {
|
||||
compatible = "qcom,gpr";
|
||||
qcom,glink-channels = "adsp_apps";
|
||||
qcom,intents = <0x200 20>;
|
||||
reg = <GPR_DOMAIN_ADSP>;
|
||||
|
||||
spf_core {
|
||||
compatible = "qcom,spf_core";
|
||||
reg = <GPR_SVC_ADSP_CORE>;
|
||||
};
|
||||
|
||||
audio-pkt {
|
||||
compatible = "qcom,audio-pkt";
|
||||
qcom,audiopkt-ch-name = "apr_audio_svc";
|
||||
reg = <GPR_SVC_MAX>;
|
||||
};
|
||||
|
||||
audio_prm: q6prm {
|
||||
compatible = "qcom,audio_prm";
|
||||
reg = <GPR_SVC_ASM>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spf_core_platform {
|
||||
|
||||
msm_audio_ion: qcom,msm-audio-ion {
|
||||
compatible = "qcom,msm-audio-ion";
|
||||
qcom,smmu-version = <2>;
|
||||
qcom,smmu-enabled;
|
||||
iommus = <&apps_smmu 0x1001 0x0080>, <&apps_smmu 0x1061 0x0>;
|
||||
qcom,iommu-dma-addr-pool = <0x10000000 0x10000000>;
|
||||
qcom,smmu-sid-mask = /bits/ 64 <0xf>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
msm_audio_ion_cma: qcom,msm-audio-ion-cma {
|
||||
compatible = "qcom,msm-audio-ion-cma";
|
||||
};
|
||||
|
||||
lpi_tlmm: lpi_pinctrl@6E80000 {
|
||||
compatible = "qcom,lpi-pinctrl";
|
||||
reg = <0x6E80000 0x0>;
|
||||
qcom,gpios-count = <23>;
|
||||
qcom,slew-reg = <0x6E80000 0x0>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
qcom,lpi-offset-tbl = <0x00000000>, <0x00001000>,
|
||||
<0x00002000>, <0x00003000>,
|
||||
<0x00004000>, <0x00005000>,
|
||||
<0x00006000>, <0x00007000>,
|
||||
<0x00008000>, <0x00009000>,
|
||||
<0x0000A000>, <0x0000B000>,
|
||||
<0x0000C000>, <0x0000D000>,
|
||||
<0x0000E000>, <0x0000F000>,
|
||||
<0x00010000>, <0x00011000>,
|
||||
<0x00012000>, <0x00013000>,
|
||||
<0x00014000>, <0x00015000>,
|
||||
<0x00016000>;
|
||||
qcom,lpi-slew-offset-tbl = <0x0000000B>, <0x0000000B>,
|
||||
<0x0000000B>, <0x0000000B>,
|
||||
<0x0000000B>, <0x0000000B>,
|
||||
<0x0000000B>, <0x0000000B>,
|
||||
<0x0000000B>, <0x0000000B>,
|
||||
<0x0000000B>, <0x0000000B>,
|
||||
<0x0000000B>, <0x0000000B>,
|
||||
<0x0000000B>, <0x0000000B>,
|
||||
<0x0000000B>, <0x0000000B>,
|
||||
<0x0000000B>, <0x0000000B>,
|
||||
<0x0000000B>, <0x0000000B>,
|
||||
<0x0000000B>;
|
||||
|
||||
qcom,lpi-slew-base-tbl = <0x6E80000>, <0x6E81000>,
|
||||
<0x6E82000>, <0x6E83000>,
|
||||
<0x6E84000>, <0x6E85000>,
|
||||
<0x6E86000>, <0x6E87000>,
|
||||
<0x6E88000>, <0x6E89000>,
|
||||
<0x6E8A000>, <0x6E8B000>,
|
||||
<0x6E8C000>, <0x6E8D000>,
|
||||
<0x6E8E000>, <0x6E8F000>,
|
||||
<0x6E90000>, <0x6E91000>,
|
||||
<0x6E92000>, <0x6E93000>,
|
||||
<0x6E94000>, <0x6E95000>,
|
||||
<0x6E96000>;
|
||||
|
||||
clock-names = "lpass_core_hw_vote",
|
||||
"lpass_audio_hw_vote";
|
||||
clocks = <&lpass_core_hw_vote 0>,
|
||||
<&lpass_audio_hw_vote 0>;
|
||||
};
|
||||
|
||||
lpass_cdc: lpass-cdc {
|
||||
compatible = "qcom,lpass-cdc";
|
||||
clock-names = "lpass_core_hw_vote",
|
||||
"lpass_audio_hw_vote";
|
||||
clocks = <&lpass_core_hw_vote 0>,
|
||||
<&lpass_audio_hw_vote 0>;
|
||||
lpass-cdc-clk-rsc-mngr {
|
||||
compatible = "qcom,lpass-cdc-clk-rsc-mngr";
|
||||
};
|
||||
|
||||
va_macro: va-macro@6D44000 {
|
||||
swr2: va_swr_master {
|
||||
};
|
||||
};
|
||||
|
||||
tx_macro: tx-macro@6AE0000 {
|
||||
};
|
||||
|
||||
rx_macro: rx-macro@6AC0000 {
|
||||
swr1: rx_swr_master {
|
||||
};
|
||||
};
|
||||
|
||||
wsa_macro: wsa-macro@6B00000 {
|
||||
swr0: wsa_swr_master {
|
||||
};
|
||||
};
|
||||
|
||||
wsa2_macro: wsa2-macro@6AA0000 {
|
||||
swr3: wsa2_swr_master {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pineapple_snd: sound {
|
||||
compatible = "qcom,pineapple-asoc-snd";
|
||||
qcom,mi2s-audio-intf = <1>;
|
||||
qcom,tdm-audio-intf = <0>;
|
||||
qcom,auxpcm-audio-intf = <1>;
|
||||
qcom,wcn-bt = <0>;
|
||||
qcom,ext-disp-audio-rx = <0>;
|
||||
qcom,afe-rxtx-lb = <0>;
|
||||
|
||||
clock-names = "lpass_audio_hw_vote";
|
||||
clocks = <&lpass_audio_hw_vote 0>;
|
||||
wcd939x-i2c-handle = <&wcd_usbss>;
|
||||
};
|
||||
};
|
||||
|
||||
&aliases {
|
||||
swr0 = "/soc/spf_core_platform/lpass-cdc/wsa-macro@6B00000/wsa_swr_master";
|
||||
swr1 = "/soc/spf_core_platform/lpass-cdc/rx-macro@6AC0000/rx_swr_master";
|
||||
swr2 = "/soc/spf_core_platform/lpass-cdc/va-macro@6D44000/va_swr_master";
|
||||
swr3 = "/soc/spf_core_platform/lpass-cdc/wsa2-macro@6AA0000/wsa2_swr_master";
|
||||
};
|
||||
|
||||
2549
qcom/audio/pineapple-lpi.dtsi
Normal file
2549
qcom/audio/pineapple-lpi.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
15
qcom/audio/pineapplep-audio-hdk.dts
Normal file
15
qcom/audio/pineapplep-audio-hdk.dts
Normal file
@@ -0,0 +1,15 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "pineapplep-audio-hdk.dtsi"
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. PineappleP HDK";
|
||||
compatible = "qcom,pineapplep-hdk", "qcom,pineapplep", "qcom,hdk";
|
||||
qcom,msm-id = <577 0x10000>, <577 0x20000>;
|
||||
qcom,board-id = <0x1f 0>;
|
||||
};
|
||||
15
qcom/audio/pineapplep-audio-hdk.dtsi
Normal file
15
qcom/audio/pineapplep-audio-hdk.dtsi
Normal file
@@ -0,0 +1,15 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "pineapple-audio-qrd.dtsi"
|
||||
|
||||
&pineapple_snd {
|
||||
qcom,model = "pineapple-qrd-snd-card";
|
||||
|
||||
qcom,msm-mbhc-usbc-audio-supported = <0>;
|
||||
qcom,msm-mbhc-hphl-swh = <1>;
|
||||
qcom,msm-mbhc-gnd-swh = <1>;
|
||||
};
|
||||
|
||||
18
qcom/audio/sun-audio-atp.dts
Normal file
18
qcom/audio/sun-audio-atp.dts
Normal file
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sun-audio-atp.dtsi"
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun ATP";
|
||||
compatible = "qcom,sun-atp", "qcom,sun", "qcom,sunp-atp", "qcom,sunp",
|
||||
"qcom,atp";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
|
||||
<0x100026a 0x10000>, <0x100026a 0x20000>,
|
||||
<0x100027f 0x10000>, <0x100027f 0x20000>;
|
||||
qcom,board-id = <0x10021 0>;
|
||||
};
|
||||
18
qcom/audio/sun-audio-atp.dtsi
Normal file
18
qcom/audio/sun-audio-atp.dtsi
Normal file
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "sun-audio-cdp.dtsi"
|
||||
|
||||
&wsa_macro {
|
||||
qcom,wsa-bat-cfgs= <4>, <4>;
|
||||
};
|
||||
|
||||
&wsa2_macro {
|
||||
qcom,wsa-bat-cfgs= <4>, <4>;
|
||||
};
|
||||
|
||||
&swr_haptics {
|
||||
status = "disabled";
|
||||
};
|
||||
18
qcom/audio/sun-audio-cdp-nfc.dts
Normal file
18
qcom/audio/sun-audio-cdp-nfc.dts
Normal file
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sun-audio-cdp-nfc.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun CDP ST54L NFC";
|
||||
compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp", "qcom,cdp";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
|
||||
<0x100026a 0x10000>, <0x100026a 0x20000>,
|
||||
<0x100027f 0x10000>, <0x100027f 0x20000>;
|
||||
qcom,board-id = <0x50001 0>;
|
||||
};
|
||||
10
qcom/audio/sun-audio-cdp-nfc.dtsi
Normal file
10
qcom/audio/sun-audio-cdp-nfc.dtsi
Normal file
@@ -0,0 +1,10 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "sun-audio-cdp.dtsi"
|
||||
|
||||
&sun_snd {
|
||||
qcom,wcn-bt-ext = <0>;
|
||||
};
|
||||
17
qcom/audio/sun-audio-cdp.dts
Normal file
17
qcom/audio/sun-audio-cdp.dts
Normal file
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sun-audio-cdp.dtsi"
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun CDP";
|
||||
compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
|
||||
<0x100026a 0x10000>, <0x100026a 0x20000>,
|
||||
<0x100027f 0x10000>, <0x100027f 0x20000>;
|
||||
qcom,board-id = <1 0>, <0x50001 0>;
|
||||
};
|
||||
140
qcom/audio/sun-audio-cdp.dtsi
Normal file
140
qcom/audio/sun-audio-cdp.dtsi
Normal file
@@ -0,0 +1,140 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "sun-audio-overlay.dtsi"
|
||||
|
||||
&lpass_cdc {
|
||||
qcom,num-macros = <4>;
|
||||
};
|
||||
|
||||
&wsa2_macro {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cdc_pri_mi2s_gpios {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&fm_i2s1_gpios {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&cdc_tert_mi2s_gpios {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cdc_quat_mi2s_gpios {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cdc_quin_mi2s_gpios {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cdc_sen_mi2s_gpios {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cdc_sep_mi2s_gpios {
|
||||
status = "disabled";
|
||||
};
|
||||
&swr_haptics {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&sun_snd {
|
||||
qcom,model = "sun-cdp-snd-card";
|
||||
swr-haptics-unsupported;
|
||||
qcom,audio-routing =
|
||||
"AMIC1", "Analog Mic1",
|
||||
"AMIC1", "MIC BIAS1",
|
||||
"AMIC2", "Analog Mic2",
|
||||
"AMIC2", "MIC BIAS2",
|
||||
"AMIC3", "Analog Mic3",
|
||||
"AMIC3", "MIC BIAS1",
|
||||
"AMIC4", "Analog Mic4",
|
||||
"AMIC4", "MIC BIAS3",
|
||||
"AMIC5", "Analog Mic5",
|
||||
"AMIC5", "MIC BIAS4",
|
||||
"VA AMIC1", "Analog Mic1",
|
||||
"VA AMIC1", "VA MIC BIAS1",
|
||||
"VA AMIC2", "Analog Mic2",
|
||||
"VA AMIC2", "VA MIC BIAS2",
|
||||
"VA AMIC3", "Analog Mic3",
|
||||
"VA AMIC3", "VA MIC BIAS1",
|
||||
"VA AMIC4", "Analog Mic4",
|
||||
"VA AMIC4", "VA MIC BIAS3",
|
||||
"VA AMIC5", "Analog Mic5",
|
||||
"VA AMIC5", "VA MIC BIAS4",
|
||||
"TX DMIC0", "Digital Mic0",
|
||||
"TX DMIC0", "MIC BIAS1",
|
||||
"TX DMIC1", "Digital Mic1",
|
||||
"TX DMIC1", "MIC BIAS1",
|
||||
"TX DMIC2", "Digital Mic2",
|
||||
"TX DMIC2", "MIC BIAS3",
|
||||
"TX DMIC3", "Digital Mic3",
|
||||
"TX DMIC3", "MIC BIAS3",
|
||||
"TX DMIC4", "Digital Mic4",
|
||||
"TX DMIC4", "MIC BIAS3",
|
||||
"TX DMIC5", "Digital Mic5",
|
||||
"TX DMIC5", "MIC BIAS3",
|
||||
"TX DMIC6", "Digital Mic6",
|
||||
"TX DMIC6", "MIC BIAS4",
|
||||
"TX DMIC7", "Digital Mic7",
|
||||
"TX DMIC7", "MIC BIAS4",
|
||||
"IN1_HPHL", "HPHL_OUT",
|
||||
"IN2_HPHR", "HPHR_OUT",
|
||||
"IN3_EAR", "AUX_OUT",
|
||||
"WSA SRC0_INP", "SRC0",
|
||||
"WSA_TX DEC0_INP", "TX DEC0 MUX",
|
||||
"WSA_TX DEC1_INP", "TX DEC1 MUX",
|
||||
"RX_TX DEC0_INP", "TX DEC0 MUX",
|
||||
"RX_TX DEC1_INP", "TX DEC1 MUX",
|
||||
"RX_TX DEC2_INP", "TX DEC2 MUX",
|
||||
"RX_TX DEC3_INP", "TX DEC3 MUX",
|
||||
"SpkrLeft IN", "WSA_SPK1 OUT",
|
||||
"SpkrRight IN", "WSA_SPK2 OUT",
|
||||
"TX SWR_INPUT", "WCD_TX_OUTPUT",
|
||||
"VA SWR_INPUT", "VA_SWR_CLK",
|
||||
"VA SWR_INPUT", "WCD_TX_OUTPUT",
|
||||
"VA_AIF1 CAP", "VA_SWR_CLK",
|
||||
"VA_AIF2 CAP", "VA_SWR_CLK",
|
||||
"VA_AIF3 CAP", "VA_SWR_CLK",
|
||||
"VA DMIC0", "Digital Mic0",
|
||||
"VA DMIC1", "Digital Mic1",
|
||||
"VA DMIC2", "Digital Mic2",
|
||||
"VA DMIC3", "Digital Mic3",
|
||||
"VA DMIC4", "Digital Mic4",
|
||||
"VA DMIC5", "Digital Mic5",
|
||||
"VA DMIC6", "Digital Mic6",
|
||||
"VA DMIC7", "Digital Mic7",
|
||||
"VA DMIC0", "VA MIC BIAS1",
|
||||
"VA DMIC1", "VA MIC BIAS1",
|
||||
"VA DMIC2", "VA MIC BIAS1",
|
||||
"VA DMIC3", "VA MIC BIAS1",
|
||||
"VA DMIC4", "VA MIC BIAS3",
|
||||
"VA DMIC5", "VA MIC BIAS3",
|
||||
"VA DMIC6", "VA MIC BIAS4",
|
||||
"VA DMIC7", "VA MIC BIAS4";
|
||||
qcom,cdc-dmic67-gpios = <&cdc_dmic67_gpios>;
|
||||
asoc-codec = <&stub_codec>, <&lpass_cdc>,
|
||||
<&wcd939x_codec>, <&swr_haptics>,
|
||||
<&wsa884x_0220>, <&wsa884x_0221>;
|
||||
asoc-codec-names = "msm-stub-codec.1", "lpass-cdc",
|
||||
"wcd939x_codec", "swr-haptics",
|
||||
"wsa-codec1", "wsa-codec2";
|
||||
qcom,wsa-max-devs = <2>;
|
||||
qcom,pri-mi2s-gpios = <&cdc_pri_mi2s_gpios>;
|
||||
qcom,sec-mi2s-gpios = <&fm_i2s1_gpios>;
|
||||
qcom,tert-mi2s-gpios = <&cdc_tert_mi2s_gpios>;
|
||||
qcom,quat-mi2s-gpios = <&cdc_quat_mi2s_gpios>;
|
||||
qcom,quin-mi2s-gpios = <&cdc_quin_mi2s_gpios>;
|
||||
qcom,sen-mi2s-gpios = <&cdc_sen_mi2s_gpios>;
|
||||
qcom,sep-mi2s-gpios = <&cdc_sep_mi2s_gpios>;
|
||||
qcom,usbss-hsj-connect-enabled;
|
||||
qcom,msm-mbhc-hs-mic-max-threshold-mv = <1680>;
|
||||
wcd939x-i2c-handle = <&wcd_usbss>;
|
||||
qcom,wcn-bt-ext = <1>;
|
||||
};
|
||||
21
qcom/audio/sun-audio-hamilton-cdp.dts
Normal file
21
qcom/audio/sun-audio-hamilton-cdp.dts
Normal file
@@ -0,0 +1,21 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
/*This is CDP with Hamilton wlan*/
|
||||
|
||||
#include "sun-audio-hamilton-cdp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun CDP";
|
||||
compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp", "qcom,cdp";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
|
||||
<0x100026a 0x10000>, <0x100026a 0x20000>,
|
||||
<0x100027f 0x10000>, <0x100027f 0x20000>;
|
||||
qcom,board-id = <0x20001 0>, <0x60001 0>;
|
||||
};
|
||||
|
||||
14
qcom/audio/sun-audio-hamilton-cdp.dtsi
Normal file
14
qcom/audio/sun-audio-hamilton-cdp.dtsi
Normal file
@@ -0,0 +1,14 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/*This is CDP with Hamilton wlan*/
|
||||
#include "sun-audio-cdp.dtsi"
|
||||
&lpass_bt_swr {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&sun_snd {
|
||||
qcom,wcn-bt-ext = <0>;
|
||||
};
|
||||
22
qcom/audio/sun-audio-hamilton-mtp-3.5mm.dts
Normal file
22
qcom/audio/sun-audio-hamilton-mtp-3.5mm.dts
Normal file
@@ -0,0 +1,22 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
/*This is MTP with Hamilton + V8 + 3.5mm support*/
|
||||
|
||||
#include "sun-audio-hamilton-mtp-3.5mm.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun MTP Hamilton with 3.5mm";
|
||||
compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp",
|
||||
"qcom,mtp";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
|
||||
<0x100026a 0x10000>, <0x100026a 0x20000>,
|
||||
<0x100027f 0x10000>, <0x100027f 0x20000>;
|
||||
qcom,board-id = <0x60108 0>;
|
||||
};
|
||||
|
||||
17
qcom/audio/sun-audio-hamilton-mtp-3.5mm.dtsi
Normal file
17
qcom/audio/sun-audio-hamilton-mtp-3.5mm.dtsi
Normal file
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
/*This is MTP with Hamilton + V8 +3.5mm*/
|
||||
#include "sun-audio-hamilton-mtp.dtsi"
|
||||
|
||||
&sun_snd {
|
||||
qcom,msm-mbhc-usbc-audio-supported = <0>;
|
||||
qcom,msm-mbhc-hphl-swh = <1>;
|
||||
qcom,msm-mbhc-gnd-swh = <1>;
|
||||
qcom,wcn-bt-ext = <0>;
|
||||
};
|
||||
21
qcom/audio/sun-audio-hamilton-mtp-v2.dts
Normal file
21
qcom/audio/sun-audio-hamilton-mtp-v2.dts
Normal file
@@ -0,0 +1,21 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
/*This is MTP v2 with Hamilton + V8/V6 wlan*/
|
||||
|
||||
#include "sun-audio-hamilton-qmp-mtp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun MTP ST54L NFC";
|
||||
compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp";
|
||||
qcom,msm-id = <618 0x20000>, <639 0x20000>,
|
||||
<0x100026a 0x20000>,
|
||||
<0x100027f 0x20000>;
|
||||
qcom,board-id = <0x20008 0>, <0x50008 0>;
|
||||
};
|
||||
|
||||
21
qcom/audio/sun-audio-hamilton-mtp.dts
Normal file
21
qcom/audio/sun-audio-hamilton-mtp.dts
Normal file
@@ -0,0 +1,21 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
/*This is MTP with Hamilton + V8/V6 wlan*/
|
||||
|
||||
#include "sun-audio-hamilton-mtp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun MTP ST54L NFC";
|
||||
compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp";
|
||||
qcom,msm-id = <618 0x10000>, <639 0x10000>,
|
||||
<0x100026a 0x10000>,
|
||||
<0x100027f 0x10000>;
|
||||
qcom,board-id = <0x20008 0>, <0x50008 0>;
|
||||
};
|
||||
|
||||
18
qcom/audio/sun-audio-hamilton-mtp.dtsi
Normal file
18
qcom/audio/sun-audio-hamilton-mtp.dtsi
Normal file
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "sun-audio-mtp.dtsi"
|
||||
|
||||
&lpass_bt_swr {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&sun_snd {
|
||||
qcom,model = "sun-mtp-wsa883x-snd-card";
|
||||
qcom,msm_audio_ssr_devs = <&audio_gpr>, <&lpi_tlmm>,
|
||||
<&lpass_cdc>;
|
||||
qcom,wcn-bt-ext = <0>;
|
||||
};
|
||||
|
||||
18
qcom/audio/sun-audio-hamilton-qmp-mtp.dtsi
Normal file
18
qcom/audio/sun-audio-hamilton-qmp-mtp.dtsi
Normal file
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "sun-audio-mtp-qmp.dtsi"
|
||||
|
||||
&lpass_bt_swr {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&sun_snd {
|
||||
qcom,model = "sun-mtp-wsa883x_qmp-snd-card";
|
||||
qcom,msm_audio_ssr_devs = <&audio_gpr>, <&lpi_tlmm>,
|
||||
<&lpass_cdc>;
|
||||
qcom,wcn-bt-ext = <0>;
|
||||
};
|
||||
|
||||
17
qcom/audio/sun-audio-hamilton-rcm.dts
Normal file
17
qcom/audio/sun-audio-hamilton-rcm.dts
Normal file
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sun-audio-hamilton-cdp.dtsi"
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun RCM";
|
||||
compatible = "qcom,sun-rcm", "qcom,sun", "qcom,sunp-rcm", "qcom,sunp", "qcom,rcm";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
|
||||
<0x100026a 0x10000>, <0x100026a 0x20000>,
|
||||
<0x100027f 0x10000>, <0x100027f 0x20000>;
|
||||
qcom,board-id = <0x20015 0>, <0x40015 0>;
|
||||
};
|
||||
18
qcom/audio/sun-audio-hdk.dts
Normal file
18
qcom/audio/sun-audio-hdk.dts
Normal file
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sun-audio-hdk.dtsi"
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. SunP QRD HDK";
|
||||
compatible = "qcom,sunp-hdk", "qcom,sunp", "qcom,hdk";
|
||||
qcom,msm-id = <639 0x10000>, <639 0x20000>,
|
||||
<0x100026a 0x10000>, <0x100026a 0x20000>,
|
||||
<0x100027f 0x10000>, <0x100027f 0x20000>,
|
||||
<618 0x10000>, <618 0x20000>;
|
||||
qcom,board-id = <0x1001f 0>;
|
||||
};
|
||||
15
qcom/audio/sun-audio-hdk.dtsi
Normal file
15
qcom/audio/sun-audio-hdk.dtsi
Normal file
@@ -0,0 +1,15 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "sun-audio-qrd.dtsi"
|
||||
|
||||
&sun_snd {
|
||||
qcom,model = "sun-qrd-snd-card";
|
||||
|
||||
qcom,msm-mbhc-usbc-audio-supported = <0>;
|
||||
qcom,msm-mbhc-hphl-swh = <1>;
|
||||
qcom,msm-mbhc-gnd-swh = <1>;
|
||||
qcom,wcn-bt-ext = <0>;
|
||||
};
|
||||
26
qcom/audio/sun-audio-mtp-3.5mm.dts
Normal file
26
qcom/audio/sun-audio-mtp-3.5mm.dts
Normal file
@@ -0,0 +1,26 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
/*This is MTP with 3.5mm HS. */
|
||||
|
||||
#include "sun-audio-mtp.dtsi"
|
||||
|
||||
&sun_snd {
|
||||
qcom,msm-mbhc-usbc-audio-supported = <0>;
|
||||
qcom,msm-mbhc-hphl-swh = <1>;
|
||||
qcom,msm-mbhc-gnd-swh = <1>;
|
||||
};
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun MTP with 3.5mm";
|
||||
compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
|
||||
<0x100026a 0x10000>, <0x100026a 0x20000>,
|
||||
<0x100027f 0x10000>, <0x100027f 0x20000>;
|
||||
qcom,board-id = <0x60008 0>;
|
||||
};
|
||||
20
qcom/audio/sun-audio-mtp-nfc.dts
Normal file
20
qcom/audio/sun-audio-mtp-nfc.dts
Normal file
@@ -0,0 +1,20 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
/*This is MTP with Ganges wlan w/ v8 Power Grid */
|
||||
|
||||
#include "sun-audio-mtp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun MTP ST54L NFC";
|
||||
compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
|
||||
<0x100026a 0x10000>, <0x100026a 0x20000>,
|
||||
<0x100027f 0x10000>, <0x100027f 0x20000>;
|
||||
qcom,board-id = <0x30008 0>, <0x40008 0>;
|
||||
};
|
||||
18
qcom/audio/sun-audio-mtp-qmp.dts
Normal file
18
qcom/audio/sun-audio-mtp-qmp.dts
Normal file
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sun-audio-mtp-qmp.dtsi"
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun MTP QMP1000";
|
||||
compatible = "qcom,sun-mtp", "qcom,sun", "qcom,mtp", "qcom,sunp-mtp", "qcom,sunp";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
|
||||
<0x100026a 0x10000>, <0x100026a 0x20000>,
|
||||
<0x100027f 0x10000>, <0x100027f 0x20000>;
|
||||
qcom,board-id = <0x108 0>, <0x40108 0>;
|
||||
};
|
||||
166
qcom/audio/sun-audio-mtp-qmp.dtsi
Normal file
166
qcom/audio/sun-audio-mtp-qmp.dtsi
Normal file
@@ -0,0 +1,166 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "sun-audio-mtp.dtsi"
|
||||
|
||||
&swr2 {
|
||||
qmp01: qmp@04170232 {
|
||||
/*
|
||||
* reg = <Class_partID[7:0]
|
||||
* partID[15:8] manuID[7:0] manuID[15:8](version4bits_UniqueID4bits)
|
||||
*/
|
||||
reg = <0x0100 0x04170232>;
|
||||
compatible = "qcom,qmp-sdca-dmic";
|
||||
sound-name-prefix = "QMP_MIC01";
|
||||
qcom,codec-name = "qmp-dmic.01";
|
||||
qmp-vdd-supply = <&wcd_mb3_reg>;
|
||||
qcom,swr-tx-port-params =
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL2 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL2 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL2 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL2 LANE0>;
|
||||
reg-values = <0x401805B0 0x5
|
||||
0x401805B1 0x5
|
||||
0x401805B2 0x5
|
||||
0x401805B3 0x5
|
||||
0x401805B8 0x5>;
|
||||
};
|
||||
|
||||
qmp02: qmp@04170236 {
|
||||
reg = <0x0100 0x04170236>;
|
||||
compatible = "qcom,qmp-sdca-dmic";
|
||||
sound-name-prefix = "QMP_MIC02";
|
||||
qcom,codec-name = "qmp-dmic.02";
|
||||
qmp-vdd-supply = <&wcd_mb3_reg>;
|
||||
qcom,swr-tx-port-params =
|
||||
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>,
|
||||
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>,
|
||||
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>,
|
||||
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>;
|
||||
reg-values = <0x401805B0 0x5
|
||||
0x401805B1 0x5
|
||||
0x401805B2 0x5
|
||||
0x401805B3 0x5
|
||||
0x401805B8 0x5>;
|
||||
};
|
||||
|
||||
qmp03: qmp@04170230 {
|
||||
reg = <0x0100 0x04170230>;
|
||||
compatible = "qcom,qmp-sdca-dmic";
|
||||
sound-name-prefix = "QMP_MIC03";
|
||||
qcom,codec-name = "qmp-dmic.03";
|
||||
qmp-vdd-supply = <&wcd_mb1_reg>;
|
||||
qcom,swr-tx-port-params =
|
||||
<OFFSET1_VAL3 LANE0>, <OFFSET1_VAL2 LANE0>,
|
||||
<OFFSET1_VAL3 LANE0>, <OFFSET1_VAL2 LANE0>,
|
||||
<OFFSET1_VAL3 LANE0>, <OFFSET1_VAL2 LANE0>,
|
||||
<OFFSET1_VAL3 LANE0>, <OFFSET1_VAL2 LANE0>;
|
||||
reg-values = <0x401805B0 0x5
|
||||
0x401805B1 0x5
|
||||
0x401805B2 0x5
|
||||
0x401805B3 0x5
|
||||
0x401805B8 0x5>;
|
||||
};
|
||||
|
||||
qmp04: qmp@04170239 {
|
||||
reg = <0x0100 0x04170239>;
|
||||
compatible = "qcom,qmp-sdca-dmic";
|
||||
sound-name-prefix = "QMP_MIC04";
|
||||
qcom,codec-name = "qmp-dmic.04";
|
||||
qmp-vdd-supply = <&wcd_mb1_reg>;
|
||||
qcom,swr-tx-port-params =
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL2 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL2 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL2 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL2 LANE0>;
|
||||
reg-values = <0x401805B0 0x5
|
||||
0x401805B1 0x5
|
||||
0x401805B2 0x5
|
||||
0x401805B3 0x5
|
||||
0x401805B8 0x5>;
|
||||
};
|
||||
};
|
||||
|
||||
&sun_snd {
|
||||
qcom,model = "sun-mtp-wsa883x_qmp-snd-card";
|
||||
asoc-codec = <&stub_codec>, <&lpass_cdc>,
|
||||
<&wcd939x_codec>, <&swr_haptics>,
|
||||
<&wsa883x_0221>, <&wsa883x_0222>,
|
||||
<&qmp01>, <&qmp02>,
|
||||
<&qmp03>, <&qmp04>;
|
||||
asoc-codec-names = "msm-stub-codec.1", "lpass-cdc",
|
||||
"wcd939x_codec", "swr-haptics",
|
||||
"wsa-codec1", "wsa-codec2",
|
||||
"qmp-dmic.01", "qmp-dmic.02",
|
||||
"qmp-dmic.03", "qmp-dmic.04";
|
||||
qcom,qmp-mic = <1>;
|
||||
qcom,audio-routing =
|
||||
"AMIC1", "Analog Mic1",
|
||||
"AMIC1", "MIC BIAS1",
|
||||
"AMIC2", "Analog Mic2",
|
||||
"AMIC2", "MIC BIAS2",
|
||||
"AMIC3", "Analog Mic3",
|
||||
"AMIC3", "MIC BIAS3",
|
||||
"AMIC4", "Analog Mic4",
|
||||
"AMIC4", "MIC BIAS3",
|
||||
"AMIC5", "Analog Mic5",
|
||||
"AMIC5", "MIC BIAS4",
|
||||
"VA AMIC1", "Analog Mic1",
|
||||
"VA AMIC1", "VA MIC BIAS1",
|
||||
"VA AMIC2", "Analog Mic2",
|
||||
"VA AMIC2", "VA MIC BIAS2",
|
||||
"VA AMIC3", "Analog Mic3",
|
||||
"VA AMIC3", "VA MIC BIAS3",
|
||||
"VA AMIC4", "Analog Mic4",
|
||||
"VA AMIC4", "VA MIC BIAS3",
|
||||
"VA AMIC5", "Analog Mic5",
|
||||
"VA AMIC5", "VA MIC BIAS4",
|
||||
"TX DMIC0", "Digital Mic0",
|
||||
"TX DMIC0", "MIC BIAS1",
|
||||
"TX DMIC1", "Digital Mic1",
|
||||
"TX DMIC1", "MIC BIAS3",
|
||||
"TX DMIC2", "Digital Mic2",
|
||||
"TX DMIC2", "MIC BIAS3",
|
||||
"TX DMIC3", "Digital Mic3",
|
||||
"TX DMIC3", "MIC BIAS1",
|
||||
"IN1_HPHL", "HPHL_OUT",
|
||||
"IN2_HPHR", "HPHR_OUT",
|
||||
"IN3_EAR", "AUX_OUT",
|
||||
"WSA SRC0_INP", "SRC0",
|
||||
"WSA_TX DEC0_INP", "TX DEC0 MUX",
|
||||
"WSA_TX DEC1_INP", "TX DEC1 MUX",
|
||||
"RX_TX DEC0_INP", "TX DEC0 MUX",
|
||||
"RX_TX DEC1_INP", "TX DEC1 MUX",
|
||||
"RX_TX DEC2_INP", "TX DEC2 MUX",
|
||||
"RX_TX DEC3_INP", "TX DEC3 MUX",
|
||||
"SpkrLeft IN", "WSA_SPK1 OUT",
|
||||
"SpkrRight IN", "WSA_SPK2 OUT",
|
||||
"TX SWR_INPUT", "WCD_TX_OUTPUT",
|
||||
"TX SWR_INPUT", "QMP_MIC01 NORMAL_OUTPUT",
|
||||
"TX SWR_INPUT", "QMP_MIC02 NORMAL_OUTPUT",
|
||||
"TX SWR_INPUT", "QMP_MIC03 NORMAL_OUTPUT",
|
||||
"TX SWR_INPUT", "QMP_MIC04 NORMAL_OUTPUT",
|
||||
"VA SWR_INPUT", "VA_SWR_CLK",
|
||||
"VA SWR_INPUT", "WCD_TX_OUTPUT",
|
||||
"VA SWR_INPUT", "QMP_MIC01 LP_OUTPUT",
|
||||
"VA SWR_INPUT", "QMP_MIC02 LP_OUTPUT",
|
||||
"VA SWR_INPUT", "QMP_MIC03 LP_OUTPUT",
|
||||
"VA SWR_INPUT", "QMP_MIC04 LP_OUTPUT",
|
||||
"VA SWR_INPUT", "QMP_MIC01 VA_NORMAL_OUTPUT",
|
||||
"VA SWR_INPUT", "QMP_MIC02 VA_NORMAL_OUTPUT",
|
||||
"VA SWR_INPUT", "QMP_MIC03 VA_NORMAL_OUTPUT",
|
||||
"VA SWR_INPUT", "QMP_MIC04 VA_NORMAL_OUTPUT",
|
||||
"VA_AIF1 CAP", "VA_SWR_CLK",
|
||||
"VA_AIF2 CAP", "VA_SWR_CLK",
|
||||
"VA_AIF3 CAP", "VA_SWR_CLK",
|
||||
"VA DMIC0", "Digital Mic0",
|
||||
"VA DMIC1", "Digital Mic1",
|
||||
"VA DMIC2", "Digital Mic2",
|
||||
"VA DMIC3", "Digital Mic3",
|
||||
"VA DMIC0", "VA MIC BIAS3",
|
||||
"VA DMIC1", "VA MIC BIAS3",
|
||||
"VA DMIC2", "VA MIC BIAS1",
|
||||
"VA DMIC3", "VA MIC BIAS1";
|
||||
};
|
||||
17
qcom/audio/sun-audio-mtp.dts
Normal file
17
qcom/audio/sun-audio-mtp.dts
Normal file
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sun-audio-mtp.dtsi"
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun MTP";
|
||||
compatible = "qcom,sun-mtp", "qcom,sun", "qcom,mtp";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
|
||||
<0x100026a 0x10000>, <0x100026a 0x20000>,
|
||||
<0x100027f 0x10000>, <0x100027f 0x20000>;
|
||||
qcom,board-id = <8 0>;
|
||||
};
|
||||
179
qcom/audio/sun-audio-mtp.dtsi
Normal file
179
qcom/audio/sun-audio-mtp.dtsi
Normal file
@@ -0,0 +1,179 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "sun-audio-overlay.dtsi"
|
||||
|
||||
&lpi_tlmm {
|
||||
spkr_02_sd_n {
|
||||
lpi_spkr_02_sd_n_sleep: spkr_02_sd_n_sleep {
|
||||
mux {
|
||||
pins = "gpio17";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio17";
|
||||
drive-strength = <2>; /* 2 mA */
|
||||
bias-pull-down;
|
||||
input-enable;
|
||||
};
|
||||
};
|
||||
|
||||
lpi_spkr_02_sd_n_active: spkr_02_sd_n_active {
|
||||
mux {
|
||||
pins = "gpio17";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio17";
|
||||
drive-strength = <16>; /* 16 mA */
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
spkr_13_sd_n {
|
||||
lpi_spkr_13_sd_n_sleep: spkr_13_sd_n_sleep {
|
||||
mux {
|
||||
pins = "gpio18";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio18";
|
||||
drive-strength = <2>; /* 2 mA */
|
||||
bias-pull-down;
|
||||
input-enable;
|
||||
};
|
||||
};
|
||||
|
||||
lpi_spkr_13_sd_n_active: spkr_13_sd_n_active {
|
||||
mux {
|
||||
pins = "gpio18";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio18";
|
||||
drive-strength = <16>; /* 16 mA */
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&wsa_spkr_en02 {
|
||||
pinctrl-0 = <&lpi_spkr_02_sd_n_active>;
|
||||
pinctrl-1 = <&lpi_spkr_02_sd_n_sleep>;
|
||||
};
|
||||
|
||||
&wsa_spkr_en13 {
|
||||
pinctrl-0 = <&lpi_spkr_13_sd_n_active>;
|
||||
pinctrl-1 = <&lpi_spkr_13_sd_n_sleep>;
|
||||
};
|
||||
|
||||
&fm_i2s1_gpios {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&sun_snd {
|
||||
qcom,model = "sun-mtp-wsa883x-snd-card";
|
||||
qcom,sec-mi2s-gpios = <&fm_i2s1_gpios>;
|
||||
asoc-codec = <&stub_codec>, <&lpass_cdc>,
|
||||
<&wcd939x_codec>, <&swr_haptics>,
|
||||
<&wsa883x_0221>, <&wsa883x_0222>;
|
||||
|
||||
qcom,msm-mbhc-usbc-audio-supported = <1>;
|
||||
qcom,msm-mbhc-hphl-swh = <0>;
|
||||
qcom,msm-mbhc-gnd-swh = <0>;
|
||||
qcom,wcn-bt-ext = <1>;
|
||||
qcom,wcd-disable-legacy-surge;
|
||||
wcd939x-i2c-handle = <&wcd_usbss>;
|
||||
};
|
||||
|
||||
&wsa884x_0220 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wsa884x_0221 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wsa884x_2_0220 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wsa884x_2_0221 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&swr0 {
|
||||
wsa883x_0221: wsa883x@02170221 {
|
||||
compatible = "qcom,wsa883x";
|
||||
reg = <0x2 0x2170221>;
|
||||
qcom,spkr-sd-n-node = <&wsa_spkr_en02>;
|
||||
qcom,lpass-cdc-handle = <&lpass_cdc>;
|
||||
cdc-vdd-1p8-supply = <&L15B>;
|
||||
qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-1p8-current = <20000>;
|
||||
qcom,cdc-vdd-1p8-lpm-supported = <1>;
|
||||
qcom,cdc-static-supplies = "cdc-vdd-1p8";
|
||||
sound-name-prefix = "SpkrLeft";
|
||||
};
|
||||
|
||||
wsa883x_0222: wsa883x@02170222 {
|
||||
compatible = "qcom,wsa883x";
|
||||
reg = <0x2 0x2170222>;
|
||||
qcom,spkr-sd-n-node = <&wsa_spkr_en13>;
|
||||
qcom,lpass-cdc-handle = <&lpass_cdc>;
|
||||
cdc-vdd-1p8-supply = <&L15B>;
|
||||
qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-1p8-current = <20000>;
|
||||
qcom,cdc-vdd-1p8-lpm-supported = <1>;
|
||||
qcom,cdc-static-supplies = "cdc-vdd-1p8";
|
||||
sound-name-prefix = "SpkrRight";
|
||||
};
|
||||
};
|
||||
|
||||
&swr3 {
|
||||
wsa883x_2_0221: wsa883x@02170221 {
|
||||
compatible = "qcom,wsa883x_2";
|
||||
reg = <0x2 0x2170221>;
|
||||
qcom,spkr-sd-n-node = <&wsa_spkr_en02>;
|
||||
qcom,lpass-cdc-handle = <&lpass_cdc>;
|
||||
cdc-vdd-1p8-supply = <&L15B>;
|
||||
qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-1p8-current = <20000>;
|
||||
qcom,cdc-vdd-1p8-lpm-supported = <1>;
|
||||
qcom,cdc-static-supplies = "cdc-vdd-1p8";
|
||||
sound-name-prefix = "Spkr2Left";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wsa883x_2_0222: wsa883x@02170222 {
|
||||
compatible = "qcom,wsa883x";
|
||||
reg = <0x2 0x2170222>;
|
||||
qcom,spkr-sd-n-node = <&wsa_spkr_en13>;
|
||||
qcom,lpass-cdc-handle = <&lpass_cdc>;
|
||||
cdc-vdd-1p8-supply = <&L15B>;
|
||||
qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-1p8-current = <20000>;
|
||||
qcom,cdc-vdd-1p8-lpm-supported = <1>;
|
||||
qcom,cdc-static-supplies = "cdc-vdd-1p8";
|
||||
sound-name-prefix = "Spkr2Right";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
&wsa_macro {
|
||||
qcom,wsa-bat-cfgs= <0>, <0>;
|
||||
};
|
||||
|
||||
&wsa2_macro {
|
||||
qcom,wsa-bat-cfgs= <0>, <0>;
|
||||
};
|
||||
873
qcom/audio/sun-audio-overlay.dtsi
Normal file
873
qcom/audio/sun-audio-overlay.dtsi
Normal file
@@ -0,0 +1,873 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <bindings/qcom,audio-ext-clk.h>
|
||||
#include <bindings/qcom,lpass-cdc-clk-rsc.h>
|
||||
#include <bindings/audio-codec-port-types.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include "sun-lpi.dtsi"
|
||||
|
||||
&lpass_cdc {
|
||||
qcom,num-macros = <5>;
|
||||
qcom,lpass-cdc-version = <7>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
lpass-cdc-clk-rsc-mngr {
|
||||
compatible = "qcom,lpass-cdc-clk-rsc-mngr";
|
||||
qcom,fs-gen-sequence = <0x3000 0x1 0x1>, <0x3004 0x3 0x3>,
|
||||
<0x3004 0x3 0x1>, <0x3080 0x2 0x2>;
|
||||
qcom,rx_mclk_mode_muxsel = <0x06BEC0D8>;
|
||||
qcom,wsa_mclk_mode_muxsel = <0x06BEA110>;
|
||||
clock-names = "tx_core_clk", "rx_core_clk", "wsa_core_clk",
|
||||
"wsa2_core_clk", "rx_tx_core_clk",
|
||||
"wsa_tx_core_clk", "wsa2_tx_core_clk", "va_core_clk";
|
||||
clocks = <&clock_audio_tx_1 0>, <&clock_audio_rx_1 0>,
|
||||
<&clock_audio_wsa_1 0>,
|
||||
<&clock_audio_wsa_2 0>, <&clock_audio_rx_tx 0>,
|
||||
<&clock_audio_wsa_tx 0>, <&clock_audio_wsa2_tx 0>,
|
||||
<&clock_audio_va_1 0>;
|
||||
};
|
||||
|
||||
va_macro: va-macro@7660000 {
|
||||
compatible = "qcom,lpass-cdc-va-macro";
|
||||
reg = <0x7660000 0x0>;
|
||||
clock-names = "lpass_audio_hw_vote";
|
||||
clocks = <&lpass_audio_hw_vote 0>;
|
||||
/*
|
||||
* Clk divding factors for each DMIC pair.
|
||||
* Valid entries for each DMIC pair:
|
||||
* 2, 3, 4, 6, 8, 16
|
||||
*
|
||||
* These factors are translated to corresponding config values
|
||||
* for the following registers,
|
||||
* -- LPASS_VA_TOP_CSR_DMIC0_CTL,
|
||||
* -- LPASS_VA_TOP_CSR_DMIC1_CTL,
|
||||
* -- LPASS_VA_TOP_CSR_DMIC2_CTL,
|
||||
* -- LPASS_VA_TOP_CSR_DMIC3_CTL,
|
||||
*/
|
||||
qcom,va-dmic-clk-div-factor = <16 16 16 16>;
|
||||
qcom,va-clk-mux-select = <1>;
|
||||
qcom,default-clk-id = <TX_CORE_CLK>;
|
||||
qcom,use-clk-id = <VA_CORE_CLK>;
|
||||
qcom,is-used-swr-gpio = <1>;
|
||||
qcom,va-swr-gpios = <&va_swr_gpios>;
|
||||
swr2: va_swr_master {
|
||||
compatible = "qcom,swr-mstr";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "lpass_core_hw_vote",
|
||||
"lpass_audio_hw_vote";
|
||||
clocks = <&lpass_core_hw_vote 0>,
|
||||
<&lpass_audio_hw_vote 0>;
|
||||
qcom,swr_master_id = <3>;
|
||||
qcom,mipi-sdw-block-packing-mode = <1>;
|
||||
swrm-io-base = <0x7630000 0x0>;
|
||||
interrupts =
|
||||
<GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "swr_master_irq", "swr_wake_irq";
|
||||
qcom,swr-wakeup-required = <1>;
|
||||
qcom,swr-num-ports = <5>;
|
||||
qcom,swr-port-mapping = <1 SWRM_TX_PCM_OUT 0x3>,
|
||||
<2 SWRM_TX1_CH1 0x1>, <2 SWRM_TX1_CH2 0x2>,
|
||||
<2 SWRM_TX1_CH3 0x4>, <2 SWRM_TX1_CH4 0x8>,
|
||||
<3 SWRM_TX2_CH1 0x1>, <3 SWRM_TX2_CH2 0x2>,
|
||||
<3 SWRM_TX2_CH3 0x4>, <3 SWRM_TX2_CH4 0x8>,
|
||||
<4 SWRM_TX3_CH1 0x1>, <4 SWRM_TX3_CH2 0x2>,
|
||||
<4 SWRM_TX3_CH3 0x4>, <4 SWRM_TX3_CH4 0x8>,
|
||||
<5 SWRM_TX_PCM_IN 0x3>;
|
||||
qcom,swr-num-dev = <5>;
|
||||
qcom,swr-clock-stop-mode0 = <1>;
|
||||
qcom,swr-mstr-irq-wakeup-capable = <1>;
|
||||
qcom,is-always-on = <1>;
|
||||
wcd939x_tx_slave: wcd939x-tx-slave {
|
||||
compatible = "qcom,wcd939x-slave";
|
||||
reg = <0x0E 0x01170223>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tx_macro: tx-macro@6AE0000 {
|
||||
compatible = "qcom,lpass-cdc-tx-macro";
|
||||
reg = <0x6AE0000 0x0>;
|
||||
qcom,default-clk-id = <TX_CORE_CLK>;
|
||||
/*
|
||||
* Clk divding factors for each DMIC pair.
|
||||
* Valid entries for each DMIC pair:
|
||||
* 2, 3, 4, 6, 8, 16
|
||||
*
|
||||
* These factors are translated to corresponding config values
|
||||
* for the following registers,
|
||||
* -- LPASS_VA_TOP_CSR_DMIC0_CTL,
|
||||
* -- LPASS_VA_TOP_CSR_DMIC1_CTL,
|
||||
* -- LPASS_VA_TOP_CSR_DMIC2_CTL,
|
||||
* -- LPASS_VA_TOP_CSR_DMIC3_CTL,
|
||||
*/
|
||||
qcom,tx-dmic-clk-div-factor = <4 4 4 4>;
|
||||
qcom,is-used-swr-gpio = <0>;
|
||||
};
|
||||
|
||||
rx_macro: rx-macro@6AC0000 {
|
||||
compatible = "qcom,lpass-cdc-rx-macro";
|
||||
reg = <0x6AC0000 0x0>;
|
||||
qcom,rx-swr-gpios = <&rx_swr_gpios>;
|
||||
qcom,rx_mclk_mode_muxsel = <0x06BEC0D8>;
|
||||
qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x03 0x48>;
|
||||
qcom,default-clk-id = <RX_TX_CORE_CLK>;
|
||||
clock-names = "rx_mclk2_2x_clk";
|
||||
clocks = <&clock_audio_rx_mclk2_2x_clk 0>;
|
||||
swr1: rx_swr_master {
|
||||
compatible = "qcom,swr-mstr";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "lpass_core_hw_vote",
|
||||
"lpass_audio_hw_vote";
|
||||
clocks = <&lpass_core_hw_vote 0>,
|
||||
<&lpass_audio_hw_vote 0>;
|
||||
qcom,swr_master_id = <2>;
|
||||
qcom,mipi-sdw-block-packing-mode = <1>;
|
||||
swrm-io-base = <0x6ad0000 0x0>;
|
||||
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "swr_master_irq";
|
||||
qcom,swr-num-ports = <12>;
|
||||
qcom,swr-port-mapping = <1 HPH_L 0x1>,
|
||||
<1 HPH_R 0x2>, <2 CLSH 0x3>,
|
||||
<3 COMP_L 0x1>, <3 COMP_R 0x2>,
|
||||
<4 LO 0x1>, <5 DSD_L 0x1>,
|
||||
<5 DSD_R 0x2>, <6 PCM_OUT1 0x01>,
|
||||
<7 GPPO 0x03>, <8 HAPT 0x03>,
|
||||
<9 HIFI_PCM_L 0x01>, <9 HIFI_PCM_R 0x2>,
|
||||
<10 HPTH 0x03>, <11 CMPT 0x03>, <12 IPCM 0x03>;
|
||||
|
||||
/* num-dev is 2 if WCD RX and PMIC SWR Slaves are connected */
|
||||
/* num-dev is 1 if only WCD RX slave is connected */
|
||||
qcom,swr-num-dev = <1>;
|
||||
|
||||
qcom,swr-clock-stop-mode0 = <1>;
|
||||
wcd939x_rx_slave: wcd939x-rx-slave {
|
||||
compatible = "qcom,wcd939x-slave";
|
||||
reg = <0x0E 0x01170224>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
wsa_macro: wsa-macro@6B00000 {
|
||||
compatible = "qcom,lpass-cdc-wsa-macro";
|
||||
reg = <0x6B00000 0x0>;
|
||||
wsa_data_fs_ctl_reg = <0x6B6F000>;
|
||||
qcom,wsa-swr-gpios = <&wsa_swr_gpios>;
|
||||
qcom,wsa-bat-cfgs= <1>, <1>;
|
||||
qcom,wsa-rloads= <2>, <2>;
|
||||
qcom,wsa-system-gains= <0 9>, <0 9>;
|
||||
qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x03 0x48>;
|
||||
qcom,default-clk-id = <WSA_TX_CORE_CLK>;
|
||||
qcom,thermal-max-state = <11>;
|
||||
qcom,noise-gate-mode = <2>;
|
||||
#cooling-cells = <2>;
|
||||
swr0: wsa_swr_master {
|
||||
compatible = "qcom,swr-mstr";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "lpass_core_hw_vote",
|
||||
"lpass_audio_hw_vote";
|
||||
clocks = <&lpass_core_hw_vote 0>,
|
||||
<&lpass_audio_hw_vote 0>;
|
||||
qcom,swr_master_id = <1>;
|
||||
qcom,mipi-sdw-block-packing-mode = <0>;
|
||||
swrm-io-base = <0x6b10000 0x0>;
|
||||
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "swr_master_irq";
|
||||
qcom,swr-num-ports = <13>;
|
||||
qcom,swr-clock-stop-mode0 = <1>;
|
||||
qcom,swr-port-mapping = <1 SPKR_L 0x1>,
|
||||
<2 SPKR_L_COMP 0xF>, <3 SPKR_L_BOOST 0x3>,
|
||||
<4 SPKR_R 0x1>, <5 SPKR_R_COMP 0xF>,
|
||||
<6 SPKR_R_BOOST 0x3>, <7 PBR 0x3>,
|
||||
<8 SPKR_HAPT 0x3>, <9 OCPM 0x3>,
|
||||
<10 SPKR_L_VI 0x3>, <11 SPKR_R_VI 0x3>,
|
||||
<12 SPKR_IPCM 0x3>, <13 CPS 0x3>;
|
||||
qcom,swr-num-dev = <2>;
|
||||
qcom,dynamic-port-map-supported = <0>;
|
||||
wsa884x_0220: wsa884x@02170220 {
|
||||
compatible = "qcom,wsa884x";
|
||||
reg = <0x4 0x2170220>;
|
||||
qcom,spkr-sd-n-node = <&wsa_spkr_en02>;
|
||||
qcom,lpass-cdc-handle = <&lpass_cdc>;
|
||||
qcom,wsa-macro-handle = <&wsa_macro>;
|
||||
qcom,swr-wsa-port-params =
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>, <OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>, <OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>, <OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>, <OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>;
|
||||
cdc-vdd-1p8-supply = <&L15B>;
|
||||
qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-1p8-current = <20000>;
|
||||
qcom,cdc-vdd-1p8-lpm-supported = <1>;
|
||||
qcom,cdc-static-supplies = "cdc-vdd-1p8";
|
||||
sound-name-prefix = "SpkrLeft";
|
||||
};
|
||||
|
||||
wsa884x_0221: wsa884x@02170221 {
|
||||
compatible = "qcom,wsa884x";
|
||||
reg = <0x4 0x2170221>;
|
||||
qcom,spkr-sd-n-node = <&wsa_spkr_en13>;
|
||||
qcom,lpass-cdc-handle = <&lpass_cdc>;
|
||||
qcom,wsa-macro-handle = <&wsa_macro>;
|
||||
qcom,swr-wsa-port-params =
|
||||
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>, <OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>, <OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>,
|
||||
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>, <OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>, <OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>,
|
||||
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>, <OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>, <OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>,
|
||||
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>, <OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>, <OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>;
|
||||
cdc-vdd-1p8-supply = <&L15B>;
|
||||
qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-1p8-current = <20000>;
|
||||
qcom,cdc-vdd-1p8-lpm-supported = <1>;
|
||||
qcom,cdc-static-supplies = "cdc-vdd-1p8";
|
||||
sound-name-prefix = "SpkrRight";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
wsa2_macro: wsa2-macro@6AA0000 {
|
||||
compatible = "qcom,lpass-cdc-wsa2-macro";
|
||||
reg = <0x6AA0000 0x0>;
|
||||
wsa_data_fs_ctl_reg = <0x6B6F000>;
|
||||
qcom,wsa2-swr-gpios = <&wsa2_swr_gpios>;
|
||||
qcom,wsa-bat-cfgs= <1>, <1>;
|
||||
qcom,wsa-rloads= <2>, <2>;
|
||||
qcom,wsa-system-gains= <0 9>, <0 9>;
|
||||
qcom,wsa2-bcl-pmic-params = /bits/ 8 <0x00 0x03 0x48>;
|
||||
qcom,default-clk-id = <WSA2_TX_CORE_CLK>;
|
||||
qcom,thermal-max-state = <11>;
|
||||
qcom,noise-gate-mode = <2>;
|
||||
#cooling-cells = <2>;
|
||||
swr3: wsa2_swr_master {
|
||||
compatible = "qcom,swr-mstr";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "lpass_core_hw_vote",
|
||||
"lpass_audio_hw_vote";
|
||||
clocks = <&lpass_core_hw_vote 0>,
|
||||
<&lpass_audio_hw_vote 0>;
|
||||
qcom,swr_master_id = <4>;
|
||||
qcom,mipi-sdw-block-packing-mode = <0>;
|
||||
swrm-io-base = <0x6ab0000 0x0>;
|
||||
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "swr_master_irq";
|
||||
qcom,swr-num-ports = <13>;
|
||||
qcom,swr-clock-stop-mode0 = <1>;
|
||||
qcom,swr-port-mapping = <1 SPKR_L 0x1>,
|
||||
<2 SPKR_L_COMP 0xF>, <3 SPKR_L_BOOST 0x3>,
|
||||
<4 SPKR_R 0x1>, <5 SPKR_R_COMP 0xF>,
|
||||
<6 SPKR_R_BOOST 0x3>, <7 PBR 0x3>,
|
||||
<8 SPKR_HAPT 0x1>, <9 OCPM 0x1>,
|
||||
<10 SPKR_L_VI 0x3>, <11 SPKR_R_VI 0x3>,
|
||||
<12 SPKR_IPCM 0x3>, <13 CPS 0x3>;
|
||||
qcom,swr-num-dev = <3>;
|
||||
qcom,dynamic-port-map-supported = <0>;
|
||||
wsa884x_2_0220: wsa884x@02170220 {
|
||||
status = "disabled";
|
||||
compatible = "qcom,wsa884x_2";
|
||||
reg = <0x4 0x2170220>;
|
||||
qcom,spkr-sd-n-node = <&wsa_spkr_en02>;
|
||||
qcom,lpass-cdc-handle = <&lpass_cdc>;
|
||||
qcom,wsa-macro-handle = <&wsa2_macro>;
|
||||
qcom,swr-wsa-port-params =
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>, <OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>, <OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>, <OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>, <OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>;
|
||||
cdc-vdd-1p8-supply = <&L15B>;
|
||||
qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-1p8-current = <20000>;
|
||||
qcom,cdc-vdd-1p8-lpm-supported = <1>;
|
||||
qcom,cdc-static-supplies = "cdc-vdd-1p8";
|
||||
sound-name-prefix = "Spkr2Left";
|
||||
};
|
||||
|
||||
wsa884x_2_0221: wsa884x@02170221 {
|
||||
status = "disabled";
|
||||
compatible = "qcom,wsa884x_2";
|
||||
reg = <0x4 0x2170221>;
|
||||
qcom,spkr-sd-n-node = <&wsa_spkr_en13>;
|
||||
qcom,lpass-cdc-handle = <&lpass_cdc>;
|
||||
qcom,wsa-macro-handle = <&wsa2_macro>;
|
||||
qcom,swr-wsa-port-params =
|
||||
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>, <OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>, <OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>,
|
||||
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>, <OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>, <OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>,
|
||||
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>, <OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>, <OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>,
|
||||
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>, <OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>, <OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>;
|
||||
cdc-vdd-1p8-supply = <&L15B>;
|
||||
qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-1p8-current = <20000>;
|
||||
qcom,cdc-vdd-1p8-lpm-supported = <1>;
|
||||
qcom,cdc-static-supplies = "cdc-vdd-1p8";
|
||||
sound-name-prefix = "Spkr2Right";
|
||||
};
|
||||
|
||||
swr_haptics: swr_haptics@f0170220 {
|
||||
compatible = "qcom,pmih010x-swr-haptics";
|
||||
reg = <0x03 0xf0170220>;
|
||||
swr-slave-supply = <&hap_swr_slave_reg>;
|
||||
qcom,rx_swr_ch_map = <0 0x01 0x01 0 OCPM>;
|
||||
qcom,rx_swr_vi_ch_map = <2 0x02 0x03 1200000 SPKR_L_VI>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
wcd939x_codec: wcd939x-codec {
|
||||
compatible = "qcom,wcd939x-codec";
|
||||
qcom,split-codec = <1>;
|
||||
qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
|
||||
<0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>,
|
||||
<2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
|
||||
<3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
|
||||
<4 DSD_R 0x2 0 DSD_R>, <5 HIFI_PCM_L 0x1 0 HIFI_PCM_L>,
|
||||
<5 HIFI_PCM_R 0x2 0 HIFI_PCM_R>;
|
||||
|
||||
qcom,tx_swr_ch_map = <0 ADC1 0x1 0 SWRM_TX1_CH1>,
|
||||
<0 ADC2 0x2 0 SWRM_TX1_CH2>,
|
||||
<1 ADC3 0x1 0 SWRM_TX1_CH3>,
|
||||
<1 ADC4 0x2 0 SWRM_TX1_CH4>,
|
||||
<2 DMIC0 0x1 0 SWRM_TX2_CH1>,
|
||||
<2 DMIC1 0x2 0 SWRM_TX2_CH2>,
|
||||
<2 MBHC 0x4 0 SWRM_TX2_CH3>,
|
||||
<2 DMIC2 0x4 0 SWRM_TX2_CH3>,
|
||||
<2 DMIC3 0x8 0 SWRM_TX2_CH4>,
|
||||
<3 DMIC4 0x1 0 SWRM_TX3_CH1>,
|
||||
<3 DMIC5 0x2 0 SWRM_TX3_CH2>,
|
||||
<3 DMIC6 0x4 0 SWRM_TX3_CH3>,
|
||||
<3 DMIC7 0x8 0 SWRM_TX3_CH4>;
|
||||
|
||||
qcom,swr-tx-port-params =
|
||||
<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL0 LANE2>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,
|
||||
<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,
|
||||
<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL2 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>;
|
||||
|
||||
qcom,wcd-rst-gpio-node = <&wcd939x_rst_gpio>;
|
||||
qcom,rx-slave = <&wcd939x_rx_slave>;
|
||||
qcom,tx-slave = <&wcd939x_tx_slave>;
|
||||
|
||||
cdc-vdd-rx-supply = <&L15B>;
|
||||
qcom,cdc-vdd-rx-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-rx-current = <30000>;
|
||||
qcom,cdc-vdd-rx-lpm-supported = <1>;
|
||||
|
||||
cdc-vdd-tx-supply = <&L15B>;
|
||||
qcom,cdc-vdd-tx-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-tx-current = <30000>;
|
||||
qcom,cdc-vdd-tx-lpm-supported = <1>;
|
||||
|
||||
cdc-vdd-buck-supply = <&L15B>;
|
||||
qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-buck-current = <650000>;
|
||||
qcom,cdc-vdd-buck-lpm-supported = <1>;
|
||||
|
||||
cdc-vdd-mic-bias-supply = <&BOB1>;
|
||||
qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>;
|
||||
qcom,cdc-vdd-mic-bias-current = <30000>;
|
||||
|
||||
cdc-vdd-px-supply = <&L2I>;
|
||||
qcom,cdc-vdd-px-voltage = <1200000 1200000>;
|
||||
qcom,cdc-vdd-px-current = <5000>;
|
||||
qcom,cdc-vdd-px-lpm-supported = <1>;
|
||||
|
||||
qcom,cdc-vdd-px-rem-supported = <1>;
|
||||
|
||||
qcom,cdc-micbias1-mv = <1800>;
|
||||
qcom,cdc-micbias2-mv = <1800>;
|
||||
qcom,cdc-micbias3-mv = <1800>;
|
||||
qcom,cdc-micbias4-mv = <1800>;
|
||||
|
||||
qcom,cdc-static-supplies = "cdc-vdd-rx",
|
||||
"cdc-vdd-tx",
|
||||
"cdc-vdd-mic-bias";
|
||||
qcom,cdc-on-demand-supplies = "cdc-vdd-buck",
|
||||
"cdc-vdd-px";
|
||||
|
||||
wcd_mb1_reg: qcom,wcd-mb1-reg {
|
||||
regulator-name = "wcd-mb1-reg";
|
||||
};
|
||||
|
||||
wcd_mb2_reg: qcom,wcd-mb2-reg {
|
||||
regulator-name = "wcd-mb2-reg";
|
||||
};
|
||||
|
||||
wcd_mb3_reg: qcom,wcd-mb3-reg {
|
||||
regulator-name = "wcd-mb3-reg";
|
||||
};
|
||||
|
||||
wcd_mb4_reg: qcom,wcd-mb4-reg {
|
||||
regulator-name = "wcd-mb4-reg";
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&lpass_bt_swr {
|
||||
clock-names = "bt_swr_mclk_clk", "bt_swr_mclk_clk_2x",
|
||||
"lpass_core_hw_vote", "lpass_audio_hw_vote";
|
||||
clocks = <&clock_audio_bt_swr_mclk_clk 0>, <&clock_audio_bt_swr_mclk_clk_2x 0>,
|
||||
<&lpass_core_hw_vote 0>, <&lpass_audio_hw_vote 0>;
|
||||
qcom,bt-swr-gpios = <&bt_swr_gpios>;
|
||||
};
|
||||
|
||||
&swr4 {
|
||||
compatible = "qcom,swr-mstr";
|
||||
qcom,swr_master_id = <5>;
|
||||
clock-names = "lpass_core_hw_vote",
|
||||
"lpass_audio_hw_vote";
|
||||
clocks = <&lpass_core_hw_vote 0>,
|
||||
<&lpass_audio_hw_vote 0>;
|
||||
swrm-io-base = <0x06CA0000 0x0>;
|
||||
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "swr_master_irq";
|
||||
qcom,swr-num-ports = <7>;
|
||||
qcom,swr-port-mapping = <1 BT_AUDIO_RX1 0x3>,
|
||||
<2 BT_AUDIO_RX2 0x3>, <3 BT_AUDIO_RX3 0x3>,
|
||||
<5 BT_AUDIO_TX1 0x3>, <6 BT_AUDIO_TX2 0x3>,
|
||||
<7 BT_AUDIO_TX3 0x3>, <8 FM_AUDIO_TX1 0x3>;
|
||||
qcom,swr-num-dev = <1>;
|
||||
};
|
||||
|
||||
&spf_core_platform {
|
||||
sun_snd: sound {
|
||||
qcom,model = "sun-mtp-snd-card";
|
||||
qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>, <1>, <1>;
|
||||
qcom,mi2s-tdm-is-hw-vote-needed = <1>, <1>, <1>, <1>, <1>, <1>, <1>;
|
||||
qcom,wcn-bt = <1>;
|
||||
qcom,ext-disp-audio-rx = <1>;
|
||||
qcom,tdm-max-slots = <8>;
|
||||
qcom,tdm-clk-attribute = <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>;
|
||||
qcom,mi2s-clk-attribute = <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>;
|
||||
qcom,audio-core-list = <0>, <1>;
|
||||
/*
|
||||
* Add this property,
|
||||
* To Enable swr haptics through OPCM port.
|
||||
* This will include wsa2 dailinks.
|
||||
*/
|
||||
qcom,dedicated-wsa2;
|
||||
qcom,audio-routing =
|
||||
"AMIC1", "Analog Mic1",
|
||||
"AMIC1", "MIC BIAS1",
|
||||
"AMIC2", "Analog Mic2",
|
||||
"AMIC2", "MIC BIAS2",
|
||||
"AMIC3", "Analog Mic3",
|
||||
"AMIC3", "MIC BIAS3",
|
||||
"AMIC4", "Analog Mic4",
|
||||
"AMIC4", "MIC BIAS3",
|
||||
"AMIC5", "Analog Mic5",
|
||||
"AMIC5", "MIC BIAS4",
|
||||
"VA AMIC1", "Analog Mic1",
|
||||
"VA AMIC1", "VA MIC BIAS1",
|
||||
"VA AMIC2", "Analog Mic2",
|
||||
"VA AMIC2", "VA MIC BIAS2",
|
||||
"VA AMIC3", "Analog Mic3",
|
||||
"VA AMIC3", "VA MIC BIAS3",
|
||||
"VA AMIC4", "Analog Mic4",
|
||||
"VA AMIC4", "VA MIC BIAS3",
|
||||
"VA AMIC5", "Analog Mic5",
|
||||
"VA AMIC5", "VA MIC BIAS4",
|
||||
"TX DMIC0", "Digital Mic0",
|
||||
"TX DMIC0", "MIC BIAS1",
|
||||
"TX DMIC1", "Digital Mic1",
|
||||
"TX DMIC1", "MIC BIAS3",
|
||||
"TX DMIC2", "Digital Mic2",
|
||||
"TX DMIC2", "MIC BIAS3",
|
||||
"TX DMIC3", "Digital Mic3",
|
||||
"TX DMIC3", "MIC BIAS1",
|
||||
"IN1_HPHL", "HPHL_OUT",
|
||||
"IN2_HPHR", "HPHR_OUT",
|
||||
"IN3_EAR", "AUX_OUT",
|
||||
"HAP_IN", "WSA2_HAPT OUT",
|
||||
"WSA SRC0_INP", "SRC0",
|
||||
"WSA_TX DEC0_INP", "TX DEC0 MUX",
|
||||
"WSA_TX DEC1_INP", "TX DEC1 MUX",
|
||||
"RX_TX DEC0_INP", "TX DEC0 MUX",
|
||||
"RX_TX DEC1_INP", "TX DEC1 MUX",
|
||||
"RX_TX DEC2_INP", "TX DEC2 MUX",
|
||||
"RX_TX DEC3_INP", "TX DEC3 MUX",
|
||||
"SpkrLeft IN", "WSA_SPK1 OUT",
|
||||
"SpkrRight IN", "WSA_SPK2 OUT",
|
||||
"TX SWR_INPUT", "WCD_TX_OUTPUT",
|
||||
"VA SWR_INPUT", "VA_SWR_CLK",
|
||||
"VA SWR_INPUT", "WCD_TX_OUTPUT",
|
||||
"VA_AIF1 CAP", "VA_SWR_CLK",
|
||||
"VA_AIF2 CAP", "VA_SWR_CLK",
|
||||
"VA_AIF3 CAP", "VA_SWR_CLK",
|
||||
"VA DMIC0", "Digital Mic0",
|
||||
"VA DMIC1", "Digital Mic1",
|
||||
"VA DMIC2", "Digital Mic2",
|
||||
"VA DMIC3", "Digital Mic3",
|
||||
"VA DMIC0", "VA MIC BIAS1",
|
||||
"VA DMIC1", "VA MIC BIAS3",
|
||||
"VA DMIC2", "VA MIC BIAS3",
|
||||
"VA DMIC3", "VA MIC BIAS1";
|
||||
qcom,msm-mbhc-usbc-audio-supported = <0>;
|
||||
qcom,msm-mbhc-hphl-swh = <1>;
|
||||
qcom,msm-mbhc-gnd-swh = <1>;
|
||||
|
||||
qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>;
|
||||
qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>;
|
||||
qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>;
|
||||
asoc-codec = <&stub_codec>, <&lpass_cdc>,
|
||||
<&wcd939x_codec>, <&swr_haptics>,
|
||||
<&wsa884x_0220>, <&wsa884x_0221>;
|
||||
asoc-codec-names = "msm-stub-codec.1", "lpass-cdc",
|
||||
"wcd939x_codec", "swr-haptics",
|
||||
"wsa-codec1", "wsa-codec2";
|
||||
qcom,wsa-max-devs = <2>;
|
||||
qcom,msm_audio_ssr_devs = <&audio_gpr>, <&lpi_tlmm>,
|
||||
<&lpass_cdc>, <&lpass_bt_swr>;
|
||||
|
||||
/*
|
||||
* ====================
|
||||
* UPD backend - WSA
|
||||
* ====================
|
||||
*
|
||||
* Mute/Unmute the interpolator
|
||||
* ------------------------------
|
||||
* Register: LPASS_WSA_CDC_RX0_RX_PATH_MIX_CTL - 0x6B00418
|
||||
*
|
||||
* Send control commands to the peripheral from the soundwire controller
|
||||
* -----------------------------------------------------------------------
|
||||
* Register: LPASS_WSA_SWR_MSTR_WSA_SWRM_CPUn_CMD_FIFO_WR_CMD - 0x6B14020
|
||||
*
|
||||
* Enable/Disable ear piece
|
||||
* --------------------------
|
||||
* Register: DIG_CTRL0_PA_FSM_EN - 0x3430
|
||||
*
|
||||
*/
|
||||
qcom,upd_backends_used = "wsa";
|
||||
qcom,upd_lpass_reg_addr = <0x6B00418 0x6B14020>;
|
||||
qcom,upd_ear_pa_reg_addr = <0x3430>;
|
||||
|
||||
/*
|
||||
* ====================
|
||||
* UPD backend - WCD
|
||||
* ====================
|
||||
*
|
||||
* Mute/Unmute the interpolator
|
||||
* ------------------------------
|
||||
* Register: LPASS_WCD_CDC_RX0_RX_PATH_MIX_CTL - 0x6AC0418
|
||||
*
|
||||
* Send control commands to the wcd from the soundwire controller
|
||||
* ----------------------------------------------------------------
|
||||
* Register: LPASS_WCD_SWR_MSTR_WSA_SWRM_CPUn_CMD_FIFO_WR_CMD - 0x7634020
|
||||
*
|
||||
* Enable/Disable ear piece
|
||||
* --------------------------
|
||||
* Register: DIG_CTRL0_PA_FSM_EN - 0x300A
|
||||
*
|
||||
*/
|
||||
/*
|
||||
qcom,upd_backends_used = "wcd";
|
||||
qcom,upd_lpass_reg_addr = <0x6AC0418 0x7634020>;
|
||||
qcom,upd_ear_pa_reg_addr = <0x300A>;
|
||||
*/
|
||||
};
|
||||
|
||||
cdc_pri_mi2s_gpios: pri_mi2s_pinctrl {
|
||||
status = "disabled";
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&i2s0_sck_active &i2s0_ws_active
|
||||
&i2s0_sd0_active &i2s0_sd1_active>;
|
||||
pinctrl-1 = <&i2s0_sck_sleep &i2s0_ws_sleep
|
||||
&i2s0_sd0_sleep &i2s0_sd1_sleep>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
fm_i2s1_gpios: fm_i2s1_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&i2s1_sck_active &i2s1_ws_active
|
||||
&i2s1_sd0_active>;
|
||||
pinctrl-1 = <&i2s1_sck_sleep &i2s1_ws_sleep
|
||||
&i2s1_sd0_sleep>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
cdc_tert_mi2s_gpios: tert_mi2s_pinctrl {
|
||||
status = "disabled";
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&lpi_i2s4_sck_active &lpi_i2s4_ws_active
|
||||
&lpi_i2s4_sd0_active &lpi_i2s4_sd1_active>;
|
||||
pinctrl-1 = <&lpi_i2s4_sck_sleep &lpi_i2s4_ws_sleep
|
||||
&lpi_i2s4_sd0_sleep &lpi_i2s4_sd1_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <185 187>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
cdc_quat_mi2s_gpios: quat_mi2s_pinctrl {
|
||||
status = "disabled";
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&quat_mi2s_sck_active &quat_mi2s_ws_active
|
||||
&quat_mi2s_sd0_active &quat_mi2s_sd1_active
|
||||
&quat_mi2s_sd2_active &quat_mi2s_sd3_active>;
|
||||
pinctrl-1 = <&quat_mi2s_sck_sleep &quat_mi2s_ws_sleep
|
||||
&quat_mi2s_sd0_sleep &quat_mi2s_sd1_sleep
|
||||
&quat_mi2s_sd2_sleep &quat_mi2s_sd3_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <166 169>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
cdc_quin_mi2s_gpios: quin_mi2s_pinctrl {
|
||||
status = "disabled";
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&lpi_i2s1_sck_active &lpi_i2s1_ws_active
|
||||
&lpi_i2s1_sd0_active &lpi_i2s1_sd1_active>;
|
||||
pinctrl-1 = <&lpi_i2s1_sck_sleep &lpi_i2s1_ws_sleep
|
||||
&lpi_i2s1_sd0_sleep &lpi_i2s1_sd1_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <171 172 174>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
cdc_sen_mi2s_gpios: sen_mi2s_pinctrl {
|
||||
status = "disabled";
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&lpi_i2s2_sck_active &lpi_i2s2_ws_active
|
||||
&lpi_i2s2_sd0_active &lpi_i2s2_sd1_active>;
|
||||
pinctrl-1 = <&lpi_i2s2_sck_sleep &lpi_i2s2_ws_sleep
|
||||
&lpi_i2s2_sd0_sleep &lpi_i2s2_sd1_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <176 181>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
cdc_sep_mi2s_gpios: sep_mi2s_pinctrl {
|
||||
status = "disabled";
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&lpi_i2s3_sck_active &lpi_i2s3_ws_active
|
||||
&lpi_i2s3_sd0_active &lpi_i2s3_sd1_active>;
|
||||
pinctrl-1 = <&lpi_i2s3_sck_sleep &lpi_i2s3_ws_sleep
|
||||
&lpi_i2s3_sd0_sleep &lpi_i2s3_sd1_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <177 182>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
wsa_swr_gpios: wsa_swr_clk_data_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&wsa_swr_clk_active &wsa_swr_data_active>;
|
||||
pinctrl-1 = <&wsa_swr_clk_sleep &wsa_swr_data_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <176>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
wsa2_swr_gpios: wsa2_swr_clk_data_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&wsa2_swr_clk_active &wsa2_swr_data_active>;
|
||||
pinctrl-1 = <&wsa2_swr_clk_sleep &wsa2_swr_data_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <181>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
rx_swr_gpios: rx_swr_clk_data_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&rx_swr_clk_active &rx_swr_data_active
|
||||
&rx_swr_data1_active>;
|
||||
pinctrl-1 = <&rx_swr_clk_sleep &rx_swr_data_sleep
|
||||
&rx_swr_data1_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <169>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
va_swr_gpios: tx_swr_clk_data_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&tx_swr_clk_active &tx_swr_data0_active
|
||||
&tx_swr_data1_active &tx_swr_data2_active>;
|
||||
pinctrl-1 = <&tx_swr_clk_sleep &tx_swr_data0_sleep
|
||||
&tx_swr_data1_sleep &tx_swr_data2_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,chip-wakeup-reg = <0xf1a6008>;
|
||||
qcom,chip-wakeup-maskbit = <7>;
|
||||
qcom,chip-wakeup-default-val = <0x1>;
|
||||
qcom,tlmm-pins = <166>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
cdc_dmic01_gpios: cdc_dmic01_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&cdc_dmic01_clk_active &cdc_dmic01_data_active>;
|
||||
pinctrl-1 = <&cdc_dmic01_clk_sleep &cdc_dmic01_data_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <171 172>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
cdc_dmic23_gpios: cdc_dmic23_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&cdc_dmic23_clk_active &cdc_dmic23_data_active>;
|
||||
pinctrl-1 = <&cdc_dmic23_clk_sleep &cdc_dmic23_data_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <174>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
cdc_dmic45_gpios: cdc_dmic45_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&cdc_dmic45_clk_active &cdc_dmic45_data_active>;
|
||||
pinctrl-1 = <&cdc_dmic45_clk_sleep &cdc_dmic45_data_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <177>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
cdc_dmic67_gpios: cdc_dmic67_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&cdc_dmic67_clk_active &cdc_dmic67_data_active>;
|
||||
pinctrl-1 = <&cdc_dmic67_clk_sleep &cdc_dmic67_data_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <182>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
bt_swr_gpios: bt_swr_clk_data_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&bt_swr_clk_active &bt_swr_data_active>;
|
||||
pinctrl-1 = <&bt_swr_clk_sleep &bt_swr_data_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
wsa_spkr_en02: wsa_spkr_en1_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&spkr_02_sd_n_active>;
|
||||
pinctrl-1 = <&spkr_02_sd_n_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
};
|
||||
|
||||
wsa_spkr_en13: wsa_spkr_en2_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&spkr_13_sd_n_active>;
|
||||
pinctrl-1 = <&spkr_13_sd_n_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
};
|
||||
|
||||
wcd939x_rst_gpio: msm_cdc_pinctrl@32 {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&wcd939x_reset_active>;
|
||||
pinctrl-1 = <&wcd939x_reset_sleep>;
|
||||
};
|
||||
|
||||
clock_audio_va_1: va_core_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK>;
|
||||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||||
qcom,codec-lpass-clk-id = <0x307>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_wsa_1: wsa_core_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_2>;
|
||||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||||
qcom,codec-lpass-clk-id = <0x309>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_wsa_2: wsa2_core_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_9>;
|
||||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||||
qcom,codec-lpass-clk-id = <0x310>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_rx_1: rx_core_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_4>;
|
||||
qcom,codec-lpass-ext-clk-freq = <22579200>;
|
||||
qcom,codec-lpass-clk-id = <0x30E>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_rx_tx: rx_core_tx_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_10>;
|
||||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||||
qcom,codec-lpass-clk-id = <0x312>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_tx_1: tx_core_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_6>;
|
||||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||||
qcom,codec-lpass-clk-id = <0x30C>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_wsa_tx: wsa_core_tx_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_11>;
|
||||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||||
qcom,codec-lpass-clk-id = <0x314>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_wsa2_tx: wsa2_core_tx_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_12>;
|
||||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||||
qcom,codec-lpass-clk-id = <0x316>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_rx_mclk2_2x_clk: rx_mclk2_2x_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_13>;
|
||||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||||
qcom,codec-lpass-clk-id = <0x318>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_bt_swr_mclk_clk: bt_swr_mclk_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_15>;
|
||||
qcom,codec-lpass-ext-clk-freq = <24576000>;
|
||||
qcom,codec-lpass-clk-id = <0x31A>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_bt_swr_mclk_clk_2x: bt_swr_mclk_clk_2x {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_16>;
|
||||
qcom,codec-lpass-ext-clk-freq = <24576000>;
|
||||
qcom,codec-lpass-clk-id = <0x31B>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&adsp_loader {
|
||||
status = "ok";
|
||||
};
|
||||
17
qcom/audio/sun-audio-qrd-sku2.dts
Normal file
17
qcom/audio/sun-audio-qrd-sku2.dts
Normal file
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sun-audio-qrd-sku2.dtsi"
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun QRD";
|
||||
compatible = "qcom,sun-qrd", "qcom,sun", "qcom,qrd";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
|
||||
<0x100026a 0x10000>, <0x100026a 0x20000>,
|
||||
<0x100027f 0x10000>, <0x100027f 0x20000>;
|
||||
qcom,board-id = <0x2000B 0>;
|
||||
};
|
||||
18
qcom/audio/sun-audio-qrd-sku2.dtsi
Normal file
18
qcom/audio/sun-audio-qrd-sku2.dtsi
Normal file
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "sun-audio-qrd.dtsi"
|
||||
&wsa_macro {
|
||||
qcom,wsa-bat-cfgs = <1>, <1>;
|
||||
};
|
||||
|
||||
&wsa2_macro {
|
||||
qcom,wsa-bat-cfgs = <1>, <1>;
|
||||
};
|
||||
|
||||
&sun_snd {
|
||||
qcom,model = "sun-qrd-sku2-snd-card";
|
||||
qcom,wcn-bt-ext = <1>;
|
||||
};
|
||||
17
qcom/audio/sun-audio-qrd.dts
Normal file
17
qcom/audio/sun-audio-qrd.dts
Normal file
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sun-audio-qrd.dtsi"
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun QRD";
|
||||
compatible = "qcom,sun-qrd", "qcom,sun", "qcom,qrd";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
|
||||
<0x100026a 0x10000>, <0x100026a 0x20000>,
|
||||
<0x100027f 0x10000>, <0x100027f 0x20000>;
|
||||
qcom,board-id = <0x1000B 0>, <0x3000B 0>;
|
||||
};
|
||||
110
qcom/audio/sun-audio-qrd.dtsi
Normal file
110
qcom/audio/sun-audio-qrd.dtsi
Normal file
@@ -0,0 +1,110 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "sun-audio-overlay.dtsi"
|
||||
&tx_swr_clk_active {
|
||||
config {
|
||||
drive-strength = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&tx_swr_data0_active {
|
||||
config {
|
||||
drive-strength = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&tx_swr_data1_active {
|
||||
config {
|
||||
drive-strength = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&tx_swr_data2_active {
|
||||
config {
|
||||
drive-strength = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&wsa_macro {
|
||||
qcom,wsa-bat-cfgs = <2>, <2>;
|
||||
};
|
||||
|
||||
&wsa2_macro {
|
||||
qcom,wsa-bat-cfgs = <2>, <2>;
|
||||
};
|
||||
|
||||
&wcd939x_codec {
|
||||
cdc-vdd-px-supply = <&L15B>;
|
||||
qcom,cdc-vdd-px-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-px-current = <650000>;
|
||||
qcom,cdc-vdd-px-lpm-supported = <1>;
|
||||
/* 0 for digital crosstalk disabled,
|
||||
* 1 for digital crosstalk with local sensed a-xtalk enabled, and
|
||||
* 2 for digital crosstalk with remote sensed a-xtalk enabled.
|
||||
*/
|
||||
qcom,usbcss-hs-xtalk-config = <0>;
|
||||
qcom,usbcss-hs-rdson = <600>;
|
||||
qcom,usbcss-hs-r2 = <7550>;
|
||||
qcom,usbcss-hs-r3 = <1>;
|
||||
qcom,usbcss-hs-r4 = <330>;
|
||||
qcom,usbcss-hs-r5 = <5>;
|
||||
qcom,usbcss-hs-r6 = <1>;
|
||||
qcom,usbcss-hs-r7 = <5>;
|
||||
qcom,usbcss-hs-lin-k-aud = <13>;
|
||||
qcom,usbcss-hs-lin-k-gnd = <13>;
|
||||
};
|
||||
|
||||
&sun_snd {
|
||||
qcom,model = "sun-qrd-snd-card";
|
||||
|
||||
qcom,audio-routing =
|
||||
"AMIC1", "Analog Mic1",
|
||||
"AMIC1", "MIC BIAS1",
|
||||
"AMIC2", "Analog Mic2",
|
||||
"AMIC2", "MIC BIAS2",
|
||||
"AMIC3", "Analog Mic3",
|
||||
"AMIC3", "MIC BIAS3",
|
||||
"AMIC4", "Analog Mic4",
|
||||
"AMIC4", "MIC BIAS3",
|
||||
"AMIC5", "Analog Mic5",
|
||||
"AMIC5", "MIC BIAS4",
|
||||
"VA AMIC1", "Analog Mic1",
|
||||
"VA AMIC1", "VA MIC BIAS1",
|
||||
"VA AMIC2", "Analog Mic2",
|
||||
"VA AMIC2", "VA MIC BIAS2",
|
||||
"VA AMIC3", "Analog Mic3",
|
||||
"VA AMIC3", "VA MIC BIAS3",
|
||||
"VA AMIC4", "Analog Mic4",
|
||||
"VA AMIC4", "VA MIC BIAS3",
|
||||
"VA AMIC5", "Analog Mic5",
|
||||
"VA AMIC5", "VA MIC BIAS4",
|
||||
"IN1_HPHL", "HPHL_OUT",
|
||||
"IN2_HPHR", "HPHR_OUT",
|
||||
"IN3_EAR", "AUX_OUT",
|
||||
"WSA SRC0_INP", "SRC0",
|
||||
"WSA_TX DEC0_INP", "TX DEC0 MUX",
|
||||
"WSA_TX DEC1_INP", "TX DEC1 MUX",
|
||||
"RX_TX DEC0_INP", "TX DEC0 MUX",
|
||||
"RX_TX DEC1_INP", "TX DEC1 MUX",
|
||||
"RX_TX DEC2_INP", "TX DEC2 MUX",
|
||||
"RX_TX DEC3_INP", "TX DEC3 MUX",
|
||||
"SpkrLeft IN", "WSA_SPK1 OUT",
|
||||
"SpkrRight IN", "WSA_SPK2 OUT",
|
||||
"TX SWR_INPUT", "WCD_TX_OUTPUT",
|
||||
"VA SWR_INPUT", "VA_SWR_CLK",
|
||||
"VA SWR_INPUT", "WCD_TX_OUTPUT",
|
||||
"VA_AIF1 CAP", "VA_SWR_CLK",
|
||||
"VA_AIF2 CAP", "VA_SWR_CLK",
|
||||
"VA_AIF3 CAP", "VA_SWR_CLK";
|
||||
|
||||
qcom,msm-mbhc-usbc-audio-supported = <1>;
|
||||
qcom,msm-mbhc-hphl-swh = <0>;
|
||||
qcom,msm-mbhc-gnd-swh = <0>;
|
||||
qcom,msm-mbhc-hs-mic-max-threshold-mv = <1670>;
|
||||
qcom,wcn-bt-ext = <1>;
|
||||
qcom,wcd-disable-legacy-surge;
|
||||
wcd939x-i2c-handle = <&wcd_usbss>;
|
||||
};
|
||||
17
qcom/audio/sun-audio-rcm.dts
Normal file
17
qcom/audio/sun-audio-rcm.dts
Normal file
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sun-audio-cdp.dtsi"
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun RCM";
|
||||
compatible = "qcom,sun-rcm", "qcom,sun", "qcom,sunp-rcm", "qcom,sunp", "qcom,rcm";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
|
||||
<0x100026a 0x10000>, <0x100026a 0x20000>,
|
||||
<0x100027f 0x10000>, <0x100027f 0x20000>;
|
||||
qcom,board-id = <0x15 0>, <0x30015 0>;
|
||||
};
|
||||
17
qcom/audio/sun-audio-rumi.dts
Normal file
17
qcom/audio/sun-audio-rumi.dts
Normal file
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sun-audio-rumi.dtsi"
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun RUMI";
|
||||
compatible = "qcom,sun-rumi", "qcom,sun", "qcom,rumi";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
|
||||
<0x100026a 0x10000>, <0x100026a 0x20000>,
|
||||
<0x100027f 0x10000>, <0x100027f 0x20000>;
|
||||
qcom,board-id = <15 0>;
|
||||
};
|
||||
18
qcom/audio/sun-audio-rumi.dtsi
Normal file
18
qcom/audio/sun-audio-rumi.dtsi
Normal file
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "sun-audio-overlay.dtsi"
|
||||
|
||||
&swr_haptics {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
&sun_snd {
|
||||
compatible = "qcom,sun-asoc-snd-stub";
|
||||
asoc-codec = <&stub_codec>;
|
||||
asoc-codec-names = "msm-stub-codec.1";
|
||||
qcom,wcn-bt-ext = <1>;
|
||||
};
|
||||
23
qcom/audio/sun-audio.dts
Normal file
23
qcom/audio/sun-audio.dts
Normal file
@@ -0,0 +1,23 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/clock/qcom,gcc-sun.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interconnect/qcom,sun.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
|
||||
#include "sun-audio.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun";
|
||||
compatible = "qcom,sun";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
|
||||
<0x100026a 0x10000>, <0x100026a 0x20000>,
|
||||
<0x100027f 0x10000>, <0x100027f 0x20000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
192
qcom/audio/sun-audio.dtsi
Normal file
192
qcom/audio/sun-audio.dtsi
Normal file
@@ -0,0 +1,192 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <bindings/qcom,audio-ext-clk.h>
|
||||
#include <bindings/qcom,gpr.h>
|
||||
#include "msm-audio-lpass.dtsi"
|
||||
|
||||
&soc {
|
||||
spf_core_platform: spf_core_platform {
|
||||
compatible = "qcom,spf-core-platform";
|
||||
};
|
||||
|
||||
lpass_core_hw_vote: vote_lpass_core_hw {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_CORE_HW_VOTE>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
lpass_audio_hw_vote: vote_lpass_audio_hw {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_AUDIO_HW_VOTE>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&remoteproc_adsp_glink {
|
||||
audio_gpr: qcom,gpr {
|
||||
compatible = "qcom,gpr";
|
||||
qcom,glink-channels = "adsp_apps";
|
||||
qcom,intents = <0x200 20>;
|
||||
qcom,ch-sched-rt;
|
||||
reg = <GPR_DOMAIN_ADSP>;
|
||||
|
||||
spf_core {
|
||||
compatible = "qcom,spf_core";
|
||||
reg = <GPR_SVC_ADSP_CORE>;
|
||||
};
|
||||
|
||||
audio-pkt {
|
||||
compatible = "qcom,audio-pkt";
|
||||
qcom,audiopkt-ch-name = "apr_audio_svc";
|
||||
reg = <GPR_SVC_MAX>;
|
||||
};
|
||||
|
||||
audio_prm: q6prm {
|
||||
compatible = "qcom,audio_prm";
|
||||
qcom,sleep-api-supported = <1>;
|
||||
reg = <GPR_SVC_ASM>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spf_core_platform {
|
||||
|
||||
msm_audio_ion: qcom,msm-audio-ion {
|
||||
compatible = "qcom,msm-audio-ion";
|
||||
qcom,smmu-version = <2>;
|
||||
qcom,smmu-enabled;
|
||||
iommus = <&apps_smmu 0x1001 0x0080>, <&apps_smmu 0x1041 0x20>;
|
||||
memory-region = <&audio_cnss_resv_region>;
|
||||
qcom,iommu-group = <&cnss_audio_iommu_group0>;
|
||||
qcom,smmu-sid-mask = /bits/ 64 <0xf>;
|
||||
dma-coherent;
|
||||
|
||||
audio_cnss_resv_region: audio_cnss_resv_region {
|
||||
iommu-addresses = <&msm_audio_ion 0x00000000 0x18000000>,
|
||||
<&msm_audio_ion 0xb0000000 0x50000000>;
|
||||
};
|
||||
};
|
||||
|
||||
msm_audio_ion_cma: qcom,msm-audio-ion-cma {
|
||||
compatible = "qcom,msm-audio-ion-cma";
|
||||
};
|
||||
|
||||
lpi_tlmm: lpi_pinctrl@07760000 {
|
||||
compatible = "qcom,lpi-pinctrl";
|
||||
reg = <0x07760000 0x0>;
|
||||
qcom,gpios-count = <23>;
|
||||
qcom,slew-reg = <0x07760000 0x0>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
qcom,lpi-offset-tbl = <0x00000000>, <0x00001000>,
|
||||
<0x00002000>, <0x00003000>,
|
||||
<0x00004000>, <0x00005000>,
|
||||
<0x00006000>, <0x00007000>,
|
||||
<0x00008000>, <0x00009000>,
|
||||
<0x0000A000>, <0x0000B000>,
|
||||
<0x0000C000>, <0x0000D000>,
|
||||
<0x0000E000>, <0x0000F000>,
|
||||
<0x00010000>, <0x00011000>,
|
||||
<0x00012000>, <0x00013000>,
|
||||
<0x00014000>, <0x00015000>,
|
||||
<0x00016000>;
|
||||
qcom,lpi-slew-offset-tbl = <0x0000000B>, <0x0000000B>,
|
||||
<0x0000000B>, <0x0000000B>,
|
||||
<0x0000000B>, <0x0000000B>,
|
||||
<0x0000000B>, <0x0000000B>,
|
||||
<0x0000000B>, <0x0000000B>,
|
||||
<0x0000000B>, <0x0000000B>,
|
||||
<0x0000000B>, <0x0000000B>,
|
||||
<0x0000000B>, <0x0000000B>,
|
||||
<0x0000000B>, <0x0000000B>,
|
||||
<0x0000000B>, <0x0000000B>,
|
||||
<0x0000000B>, <0x0000000B>,
|
||||
<0x0000000B>;
|
||||
|
||||
qcom,lpi-slew-base-tbl = <0x7760000>, <0x7761000>,
|
||||
<0x7762000>, <0x7763000>,
|
||||
<0x7764000>, <0x7765000>,
|
||||
<0x7766000>, <0x7767000>,
|
||||
<0x7768000>, <0x7769000>,
|
||||
<0x776A000>, <0x776B000>,
|
||||
<0x776C000>, <0x776D000>,
|
||||
<0x776E000>, <0x776F000>,
|
||||
<0x7770000>, <0x7771000>,
|
||||
<0x7772000>, <0x7773000>,
|
||||
<0x7774000>, <0x7775000>,
|
||||
<0x7776000>;
|
||||
|
||||
clock-names = "lpass_core_hw_vote",
|
||||
"lpass_audio_hw_vote";
|
||||
clocks = <&lpass_core_hw_vote 0>,
|
||||
<&lpass_audio_hw_vote 0>;
|
||||
};
|
||||
|
||||
lpass_cdc: lpass-cdc {
|
||||
compatible = "qcom,lpass-cdc";
|
||||
clock-names = "lpass_core_hw_vote",
|
||||
"lpass_audio_hw_vote";
|
||||
clocks = <&lpass_core_hw_vote 0>,
|
||||
<&lpass_audio_hw_vote 0>;
|
||||
lpass-cdc-clk-rsc-mngr {
|
||||
compatible = "qcom,lpass-cdc-clk-rsc-mngr";
|
||||
};
|
||||
|
||||
va_macro: va-macro@7660000 {
|
||||
swr2: va_swr_master {
|
||||
};
|
||||
};
|
||||
|
||||
tx_macro: tx-macro@6AE0000 {
|
||||
};
|
||||
|
||||
rx_macro: rx-macro@6AC0000 {
|
||||
swr1: rx_swr_master {
|
||||
};
|
||||
};
|
||||
|
||||
wsa_macro: wsa-macro@6B00000 {
|
||||
swr0: wsa_swr_master {
|
||||
};
|
||||
};
|
||||
|
||||
wsa2_macro: wsa2-macro@6AA0000 {
|
||||
swr3: wsa2_swr_master {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lpass_bt_swr: lpass_bt_swr@6CA0000 {
|
||||
compatible = "qcom,lpass-bt-swr";
|
||||
swr4: bt_swr_mstr {
|
||||
};
|
||||
};
|
||||
|
||||
sun_snd: sound {
|
||||
compatible = "qcom,sun-asoc-snd";
|
||||
qcom,mi2s-audio-intf = <1>;
|
||||
qcom,tdm-audio-intf = <0>;
|
||||
qcom,auxpcm-audio-intf = <1>;
|
||||
qcom,wcn-bt = <1>;
|
||||
qcom,ext-disp-audio-rx = <0>;
|
||||
qcom,afe-rxtx-lb = <0>;
|
||||
|
||||
clock-names = "lpass_audio_hw_vote";
|
||||
clocks = <&lpass_audio_hw_vote 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&aliases {
|
||||
swr0 = "/soc/spf_core_platform/lpass-cdc/wsa-macro@6B00000/wsa_swr_master";
|
||||
swr1 = "/soc/spf_core_platform/lpass-cdc/rx-macro@6AC0000/rx_swr_master";
|
||||
swr2 = "/soc/spf_core_platform/lpass-cdc/va-macro@7660000/va_swr_master";
|
||||
swr3 = "/soc/spf_core_platform/lpass-cdc/wsa2-macro@6AA0000/wsa2_swr_master";
|
||||
swr4 = "/soc/spf_core_platform/lpass_bt_swr@6CA0000/bt_swr_mstr";
|
||||
};
|
||||
|
||||
&adsp_loader {
|
||||
/delete-property/ qcom,adsp-state;
|
||||
};
|
||||
2578
qcom/audio/sun-lpi.dtsi
Normal file
2578
qcom/audio/sun-lpi.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
17
qcom/audio/tuna-audio-atp.dts
Normal file
17
qcom/audio/tuna-audio-atp.dts
Normal file
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "tuna-audio-atp.dtsi"
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Tuna ATP";
|
||||
compatible = "qcom,tuna-atp", "qcom,tuna", "qcom,tunap-atp", "qcom,tunap",
|
||||
"qcom,atp";
|
||||
|
||||
qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>;
|
||||
qcom,board-id = <33 0>;
|
||||
};
|
||||
47
qcom/audio/tuna-audio-atp.dtsi
Normal file
47
qcom/audio/tuna-audio-atp.dtsi
Normal file
@@ -0,0 +1,47 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "tuna-audio-cdp.dtsi"
|
||||
|
||||
&tuna_snd {
|
||||
qcom,wcn-btfm = <0>;
|
||||
qcom,ext-disp-audio-rx = <0>;
|
||||
qcom,wcd-disabled =<1>;
|
||||
qcom,audio-routing =
|
||||
"TX DMIC0", "Digital Mic0",
|
||||
"TX DMIC1", "Digital Mic1",
|
||||
"TX DMIC2", "Digital Mic2",
|
||||
"TX DMIC3", "Digital Mic3";
|
||||
qcom,wsa-max-devs = <0>;
|
||||
};
|
||||
|
||||
&swr0 {
|
||||
qcom,swr-num-dev = <0>;
|
||||
wsa884x_0220: wsa884x@02170220 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wsa884x_0221: wsa884x@02170221 {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
&wcd939x_codec {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wcd939x_rx_slave {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wcd939x_tx_slave {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
&wsa_macro {
|
||||
qcom,wsa-bat-cfgs= <4>, <4>;
|
||||
};
|
||||
|
||||
18
qcom/audio/tuna-audio-cdp.dts
Normal file
18
qcom/audio/tuna-audio-cdp.dts
Normal file
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "tuna-audio-cdp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Tuna CDP";
|
||||
compatible = "qcom,tuna-cdp", "qcom,tuna", "qcom,tunap-cdp", "qcom,tunap",
|
||||
"qcom,cdp";
|
||||
qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>;
|
||||
qcom,board-id = <1 0>;
|
||||
};
|
||||
|
||||
138
qcom/audio/tuna-audio-cdp.dtsi
Normal file
138
qcom/audio/tuna-audio-cdp.dtsi
Normal file
@@ -0,0 +1,138 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "tuna-audio-overlay.dtsi"
|
||||
|
||||
&cdc_pri_mi2s_gpios {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&fm_i2s1_gpios {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&cdc_quat_mi2s_gpios {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cdc_quin_mi2s_gpios {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cdc_sen_mi2s_gpios {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cdc_sep_mi2s_gpios {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wcd9378_codec {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wcd9378_rx_slave {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wcd9378_tx_slave {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wcd939x_codec {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wcd939x_tx_slave {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wcd939x_rx_slave {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&swr0 {
|
||||
wsa884x_0220: wsa884x@02170220 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
wsa884x_0221: wsa884x@02170221 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&tuna_snd {
|
||||
qcom,model = "tuna-cdp-snd-card";
|
||||
qcom,audio-routing =
|
||||
"AMIC1", "Analog Mic1",
|
||||
"AMIC1", "MIC BIAS1",
|
||||
"AMIC2", "Analog Mic2",
|
||||
"AMIC2", "MIC BIAS2",
|
||||
"AMIC3", "Analog Mic3",
|
||||
"AMIC3", "MIC BIAS3",
|
||||
"AMIC4", "Analog Mic4",
|
||||
"AMIC4", "MIC BIAS4",
|
||||
"VA AMIC1", "Analog Mic1",
|
||||
"VA AMIC1", "VA MIC BIAS1",
|
||||
"VA AMIC2", "Analog Mic2",
|
||||
"VA AMIC2", "VA MIC BIAS2",
|
||||
"VA AMIC3", "Analog Mic3",
|
||||
"VA AMIC3", "VA MIC BIAS3",
|
||||
"VA AMIC4", "Analog Mic4",
|
||||
"VA AMIC4", "VA MIC BIAS4",
|
||||
"TX DMIC0", "Digital Mic0",
|
||||
"TX DMIC0", "MIC BIAS1",
|
||||
"TX DMIC1", "Digital Mic1",
|
||||
"TX DMIC1", "MIC BIAS1",
|
||||
"TX DMIC2", "Digital Mic2",
|
||||
"TX DMIC2", "MIC BIAS3",
|
||||
"TX DMIC3", "Digital Mic3",
|
||||
"TX DMIC3", "MIC BIAS3",
|
||||
"IN1_HPHL", "HPHL_OUT",
|
||||
"IN2_HPHR", "HPHR_OUT",
|
||||
"IN3_EAR", "AUX_OUT",
|
||||
"WSA SRC0_INP", "SRC0",
|
||||
"WSA_TX DEC0_INP", "TX DEC0 MUX",
|
||||
"WSA_TX DEC1_INP", "TX DEC1 MUX",
|
||||
"RX_TX DEC0_INP", "TX DEC0 MUX",
|
||||
"RX_TX DEC1_INP", "TX DEC1 MUX",
|
||||
"RX_TX DEC2_INP", "TX DEC2 MUX",
|
||||
"RX_TX DEC3_INP", "TX DEC3 MUX",
|
||||
"SpkrLeft IN", "WSA_SPK1 OUT",
|
||||
"SpkrRight IN", "WSA_SPK2 OUT",
|
||||
"TX SWR_INPUT", "WCD_TX_OUTPUT",
|
||||
"VA SWR_INPUT", "VA_SWR_CLK",
|
||||
"VA SWR_INPUT", "WCD_TX_OUTPUT",
|
||||
"VA_AIF1 CAP", "VA_SWR_CLK",
|
||||
"VA_AIF2 CAP", "VA_SWR_CLK",
|
||||
"VA_AIF3 CAP", "VA_SWR_CLK",
|
||||
"VA DMIC0", "Digital Mic0",
|
||||
"VA DMIC1", "Digital Mic1",
|
||||
"VA DMIC2", "Digital Mic2",
|
||||
"VA DMIC3", "Digital Mic3",
|
||||
"VA DMIC0", "VA MIC BIAS1",
|
||||
"VA DMIC1", "VA MIC BIAS1",
|
||||
"VA DMIC2", "VA MIC BIAS3",
|
||||
"VA DMIC3", "VA MIC BIAS3";
|
||||
asoc-codec = <&stub_codec>, <&lpass_cdc>,
|
||||
<&wcd939x_codec>,
|
||||
<&wsa884x_0220>, <&wsa884x_0221>;
|
||||
asoc-codec-names = "msm-stub-codec.1", "lpass-cdc",
|
||||
"wcd939x_codec",
|
||||
"wsa-codec1", "wsa-codec2";
|
||||
qcom,wsa-max-devs = <2>;
|
||||
wcd939x-i2c-handle = <&wcd_usbss>;
|
||||
qcom,pri-mi2s-gpios = <&cdc_pri_mi2s_gpios>;
|
||||
qcom,sec-mi2s-gpios = <&fm_i2s1_gpios>;
|
||||
qcom,quat-mi2s-gpios = <&cdc_quat_mi2s_gpios>;
|
||||
qcom,quin-mi2s-gpios = <&cdc_quin_mi2s_gpios>;
|
||||
qcom,sen-mi2s-gpios = <&cdc_sen_mi2s_gpios>;
|
||||
qcom,sep-mi2s-gpios = <&cdc_sep_mi2s_gpios>;
|
||||
qcom,usbss-hsj-connect-enabled;
|
||||
qcom,msm-mbhc-usbc-audio-supported = <0>;
|
||||
qcom,msm-mbhc-hphl-swh = <1>;
|
||||
qcom,msm-mbhc-gnd-swh = <1>;
|
||||
qcom,msm-mbhc-hs-mic-max-threshold-mv = <1680>;
|
||||
};
|
||||
17
qcom/audio/tuna-audio-hamilton-mtp.dts
Normal file
17
qcom/audio/tuna-audio-hamilton-mtp.dts
Normal file
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "tuna-audio-hamilton-mtp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Tuna MTP + kiwi WLAN";
|
||||
compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap",
|
||||
"qcom,mtp";
|
||||
qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>;
|
||||
qcom,board-id = <8 2>;
|
||||
};
|
||||
18
qcom/audio/tuna-audio-hamilton-mtp.dtsi
Normal file
18
qcom/audio/tuna-audio-hamilton-mtp.dtsi
Normal file
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "tuna-audio-mtp.dtsi"
|
||||
|
||||
|
||||
&lpass_bt_swr {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&tuna_snd {
|
||||
qcom,model = "tuna-mtp-snd-card";
|
||||
qcom,wcn-bt = <1>;
|
||||
qcom,msm_audio_ssr_devs = <&audio_gpr>, <&lpi_tlmm>,
|
||||
<&lpass_cdc>;
|
||||
};
|
||||
17
qcom/audio/tuna-audio-hamilton-rcm.dts
Normal file
17
qcom/audio/tuna-audio-hamilton-rcm.dts
Normal file
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "tuna-audio-hamilton-rcm.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Tuna RCM + kiwi WLAN";
|
||||
compatible = "qcom,tuna-rcm", "qcom,tuna", "qcom,tunap-rcm", "qcom,tunap",
|
||||
"qcom,rcm";
|
||||
qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>;
|
||||
qcom,board-id = <21 1>;
|
||||
};
|
||||
16
qcom/audio/tuna-audio-hamilton-rcm.dtsi
Normal file
16
qcom/audio/tuna-audio-hamilton-rcm.dtsi
Normal file
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "tuna-audio-cdp.dtsi"
|
||||
|
||||
&lpass_bt_swr {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&tuna_snd {
|
||||
qcom,model = "tuna-cdp-snd-card";
|
||||
qcom,msm_audio_ssr_devs = <&audio_gpr>, <&lpi_tlmm>,
|
||||
<&lpass_cdc>;
|
||||
};
|
||||
18
qcom/audio/tuna-audio-mtp-qmp1000.dts
Normal file
18
qcom/audio/tuna-audio-mtp-qmp1000.dts
Normal file
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "tuna-audio-mtp-qmp1000.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Tuna MTP QMP1000";
|
||||
compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap",
|
||||
"qcom,mtp";
|
||||
qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>;
|
||||
qcom,board-id = <8 1>;
|
||||
};
|
||||
|
||||
166
qcom/audio/tuna-audio-mtp-qmp1000.dtsi
Normal file
166
qcom/audio/tuna-audio-mtp-qmp1000.dtsi
Normal file
@@ -0,0 +1,166 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "tuna-audio-mtp.dtsi"
|
||||
|
||||
&swr2 {
|
||||
qmp01: qmp@04170232 {
|
||||
/*
|
||||
* reg = <Class_partID[7:0]
|
||||
* partID[15:8] manuID[7:0] manuID[15:8](version4bits_UniqueID4bits)
|
||||
*/
|
||||
reg = <0x0100 0x04170232>;
|
||||
compatible = "qcom,qmp-sdca-dmic";
|
||||
sound-name-prefix = "QMP_MIC01";
|
||||
qcom,codec-name = "qmp-dmic.01";
|
||||
qmp-vdd-supply = <&wcd_mb3_reg>;
|
||||
qcom,swr-tx-port-params =
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL2 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL2 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL2 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL2 LANE0>;
|
||||
reg-values = <0x401805B0 0x5
|
||||
0x401805B1 0x5
|
||||
0x401805B2 0x5
|
||||
0x401805B3 0x5
|
||||
0x401805B8 0x5>;
|
||||
};
|
||||
|
||||
qmp02: qmp@04170236 {
|
||||
reg = <0x0100 0x04170236>;
|
||||
compatible = "qcom,qmp-sdca-dmic";
|
||||
sound-name-prefix = "QMP_MIC02";
|
||||
qcom,codec-name = "qmp-dmic.02";
|
||||
qmp-vdd-supply = <&wcd_mb3_reg>;
|
||||
qcom,swr-tx-port-params =
|
||||
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>,
|
||||
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>,
|
||||
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>,
|
||||
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>;
|
||||
reg-values = <0x401805B0 0x5
|
||||
0x401805B1 0x5
|
||||
0x401805B2 0x5
|
||||
0x401805B3 0x5
|
||||
0x401805B8 0x5>;
|
||||
};
|
||||
|
||||
qmp03: qmp@04170230 {
|
||||
reg = <0x0100 0x04170230>;
|
||||
compatible = "qcom,qmp-sdca-dmic";
|
||||
sound-name-prefix = "QMP_MIC03";
|
||||
qcom,codec-name = "qmp-dmic.03";
|
||||
qmp-vdd-supply = <&wcd_mb1_reg>;
|
||||
qcom,swr-tx-port-params =
|
||||
<OFFSET1_VAL3 LANE0>, <OFFSET1_VAL2 LANE0>,
|
||||
<OFFSET1_VAL3 LANE0>, <OFFSET1_VAL2 LANE0>,
|
||||
<OFFSET1_VAL3 LANE0>, <OFFSET1_VAL2 LANE0>,
|
||||
<OFFSET1_VAL3 LANE0>, <OFFSET1_VAL2 LANE0>;
|
||||
reg-values = <0x401805B0 0x5
|
||||
0x401805B1 0x5
|
||||
0x401805B2 0x5
|
||||
0x401805B3 0x5
|
||||
0x401805B8 0x5>;
|
||||
};
|
||||
|
||||
qmp04: qmp@04170239 {
|
||||
reg = <0x0100 0x04170239>;
|
||||
compatible = "qcom,qmp-sdca-dmic";
|
||||
sound-name-prefix = "QMP_MIC04";
|
||||
qcom,codec-name = "qmp-dmic.04";
|
||||
qmp-vdd-supply = <&wcd_mb1_reg>;
|
||||
qcom,swr-tx-port-params =
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL2 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL2 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL2 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL2 LANE0>;
|
||||
reg-values = <0x401805B0 0x5
|
||||
0x401805B1 0x5
|
||||
0x401805B2 0x5
|
||||
0x401805B3 0x5
|
||||
0x401805B8 0x5>;
|
||||
};
|
||||
};
|
||||
|
||||
&tuna_snd {
|
||||
qcom,model = "tuna-mtp-qmp-snd-card";
|
||||
asoc-codec = <&stub_codec>, <&lpass_cdc>,
|
||||
<&wcd9378_codec>,
|
||||
<&wsa884x_0220>, <&wsa884x_0221>,
|
||||
<&qmp01>, <&qmp02>,
|
||||
<&qmp03>, <&qmp04>;
|
||||
asoc-codec-names = "msm-stub-codec.1", "lpass-cdc",
|
||||
"wcd9378_codec",
|
||||
"wsa-codec1", "wsa-codec2",
|
||||
"qmp-dmic.01", "qmp-dmic.02",
|
||||
"qmp-dmic.03", "qmp-dmic.04";
|
||||
qcom,qmp-mic = <1>;
|
||||
qcom,audio-routing =
|
||||
"AMIC1", "Analog Mic1",
|
||||
"AMIC1", "MIC BIAS1",
|
||||
"AMIC2", "Analog Mic2",
|
||||
"AMIC2", "MIC BIAS2",
|
||||
"AMIC3", "Analog Mic3",
|
||||
"AMIC3", "MIC BIAS3",
|
||||
"AMIC4", "Analog Mic4",
|
||||
"AMIC4", "MIC BIAS3",
|
||||
"AMIC5", "Analog Mic5",
|
||||
"AMIC5", "MIC BIAS4",
|
||||
"VA AMIC1", "Analog Mic1",
|
||||
"VA AMIC1", "VA MIC BIAS1",
|
||||
"VA AMIC2", "Analog Mic2",
|
||||
"VA AMIC2", "VA MIC BIAS2",
|
||||
"VA AMIC3", "Analog Mic3",
|
||||
"VA AMIC3", "VA MIC BIAS3",
|
||||
"VA AMIC4", "Analog Mic4",
|
||||
"VA AMIC4", "VA MIC BIAS3",
|
||||
"VA AMIC5", "Analog Mic5",
|
||||
"VA AMIC5", "VA MIC BIAS4",
|
||||
"TX DMIC0", "Digital Mic0",
|
||||
"TX DMIC0", "MIC BIAS1",
|
||||
"TX DMIC1", "Digital Mic1",
|
||||
"TX DMIC1", "MIC BIAS3",
|
||||
"TX DMIC2", "Digital Mic2",
|
||||
"TX DMIC2", "MIC BIAS3",
|
||||
"TX DMIC3", "Digital Mic3",
|
||||
"TX DMIC3", "MIC BIAS1",
|
||||
"IN1_HPHL", "HPHL_OUT",
|
||||
"IN2_HPHR", "HPHR_OUT",
|
||||
"IN3_AUX", "AUX_OUT",
|
||||
"WSA SRC0_INP", "SRC0",
|
||||
"WSA_TX DEC0_INP", "TX DEC0 MUX",
|
||||
"WSA_TX DEC1_INP", "TX DEC1 MUX",
|
||||
"RX_TX DEC0_INP", "TX DEC0 MUX",
|
||||
"RX_TX DEC1_INP", "TX DEC1 MUX",
|
||||
"RX_TX DEC2_INP", "TX DEC2 MUX",
|
||||
"RX_TX DEC3_INP", "TX DEC3 MUX",
|
||||
"SpkrLeft IN", "WSA_SPK1 OUT",
|
||||
"SpkrRight IN", "WSA_SPK2 OUT",
|
||||
"TX SWR_INPUT", "WCD_TX_OUTPUT",
|
||||
"TX SWR_INPUT", "QMP_MIC01 NORMAL_OUTPUT",
|
||||
"TX SWR_INPUT", "QMP_MIC02 NORMAL_OUTPUT",
|
||||
"TX SWR_INPUT", "QMP_MIC03 NORMAL_OUTPUT",
|
||||
"TX SWR_INPUT", "QMP_MIC04 NORMAL_OUTPUT",
|
||||
"VA SWR_INPUT", "VA_SWR_CLK",
|
||||
"VA SWR_INPUT", "WCD_TX_OUTPUT",
|
||||
"VA SWR_INPUT", "QMP_MIC01 LP_OUTPUT",
|
||||
"VA SWR_INPUT", "QMP_MIC02 LP_OUTPUT",
|
||||
"VA SWR_INPUT", "QMP_MIC03 LP_OUTPUT",
|
||||
"VA SWR_INPUT", "QMP_MIC04 LP_OUTPUT",
|
||||
"VA SWR_INPUT", "QMP_MIC01 VA_NORMAL_OUTPUT",
|
||||
"VA SWR_INPUT", "QMP_MIC02 VA_NORMAL_OUTPUT",
|
||||
"VA SWR_INPUT", "QMP_MIC03 VA_NORMAL_OUTPUT",
|
||||
"VA SWR_INPUT", "QMP_MIC04 VA_NORMAL_OUTPUT",
|
||||
"VA_AIF1 CAP", "VA_SWR_CLK",
|
||||
"VA_AIF2 CAP", "VA_SWR_CLK",
|
||||
"VA_AIF3 CAP", "VA_SWR_CLK",
|
||||
"VA DMIC0", "Digital Mic0",
|
||||
"VA DMIC1", "Digital Mic1",
|
||||
"VA DMIC2", "Digital Mic2",
|
||||
"VA DMIC3", "Digital Mic3",
|
||||
"VA DMIC0", "VA MIC BIAS3",
|
||||
"VA DMIC1", "VA MIC BIAS3",
|
||||
"VA DMIC2", "VA MIC BIAS1",
|
||||
"VA DMIC3", "VA MIC BIAS1";
|
||||
};
|
||||
18
qcom/audio/tuna-audio-mtp.dts
Normal file
18
qcom/audio/tuna-audio-mtp.dts
Normal file
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "tuna-audio-mtp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Tuna MTP";
|
||||
compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap",
|
||||
"qcom,mtp";
|
||||
qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>;
|
||||
qcom,board-id = <8 0>, <8 4>;
|
||||
};
|
||||
|
||||
15
qcom/audio/tuna-audio-mtp.dtsi
Normal file
15
qcom/audio/tuna-audio-mtp.dtsi
Normal file
@@ -0,0 +1,15 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "tuna-audio-overlay.dtsi"
|
||||
|
||||
&wsa_macro {
|
||||
qcom,wsa-bat-cfgs= <1>, <1>;
|
||||
};
|
||||
|
||||
&tuna_snd {
|
||||
qcom,model = "tuna-mtp-snd-card";
|
||||
qcom,sec-mi2s-gpios = <&fm_i2s1_gpios>;
|
||||
};
|
||||
786
qcom/audio/tuna-audio-overlay.dtsi
Normal file
786
qcom/audio/tuna-audio-overlay.dtsi
Normal file
@@ -0,0 +1,786 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <bindings/qcom,audio-ext-clk.h>
|
||||
#include <bindings/qcom,lpass-cdc-clk-rsc.h>
|
||||
#include <bindings/audio-codec-port-types.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include "tuna-lpi.dtsi"
|
||||
|
||||
&lpass_cdc {
|
||||
qcom,num-macros = <4>;
|
||||
qcom,lpass-cdc-version = <7>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
lpass-cdc-clk-rsc-mngr {
|
||||
compatible = "qcom,lpass-cdc-clk-rsc-mngr";
|
||||
qcom,fs-gen-sequence = <0x3000 0x1 0x1>, <0x3004 0x3 0x3>,
|
||||
<0x3004 0x3 0x1>, <0x3080 0x2 0x2>;
|
||||
qcom,rx_mclk_mode_muxsel = <0x06BEC0D8>;
|
||||
qcom,wsa_mclk_mode_muxsel = <0x06BEA110>;
|
||||
clock-names = "tx_core_clk", "rx_core_clk", "wsa_core_clk",
|
||||
"rx_tx_core_clk", "wsa_tx_core_clk", "va_core_clk";
|
||||
clocks = <&clock_audio_tx_1 0>, <&clock_audio_rx_1 0>,
|
||||
<&clock_audio_wsa_1 0>, <&clock_audio_rx_tx 0>,
|
||||
<&clock_audio_wsa_tx 0>, <&clock_audio_va_1 0>;
|
||||
};
|
||||
|
||||
va_macro: va-macro@7660000 {
|
||||
compatible = "qcom,lpass-cdc-va-macro";
|
||||
reg = <0x7660000 0x0>;
|
||||
clock-names = "lpass_audio_hw_vote";
|
||||
clocks = <&lpass_audio_hw_vote 0>;
|
||||
/*
|
||||
* Clk divding factors for each DMIC pair.
|
||||
* Valid entries for each DMIC pair:
|
||||
* 2, 3, 4, 6, 8, 16
|
||||
*
|
||||
* These factors are translated to corresponding config values
|
||||
* for the following registers,
|
||||
* -- LPASS_VA_TOP_CSR_DMIC0_CTL,
|
||||
* -- LPASS_VA_TOP_CSR_DMIC1_CTL,
|
||||
* -- LPASS_VA_TOP_CSR_DMIC2_CTL,
|
||||
* -- LPASS_VA_TOP_CSR_DMIC3_CTL,
|
||||
*/
|
||||
qcom,va-dmic-clk-div-factor = <16 16 16 16>;
|
||||
qcom,va-clk-mux-select = <1>;
|
||||
qcom,default-clk-id = <TX_CORE_CLK>;
|
||||
qcom,use-clk-id = <VA_CORE_CLK>;
|
||||
qcom,is-used-swr-gpio = <1>;
|
||||
qcom,va-swr-gpios = <&va_swr_gpios>;
|
||||
swr2: va_swr_master {
|
||||
compatible = "qcom,swr-mstr";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "lpass_core_hw_vote",
|
||||
"lpass_audio_hw_vote";
|
||||
clocks = <&lpass_core_hw_vote 0>,
|
||||
<&lpass_audio_hw_vote 0>;
|
||||
qcom,swr_master_id = <3>;
|
||||
qcom,mipi-sdw-block-packing-mode = <1>;
|
||||
swrm-io-base = <0x7630000 0x0>;
|
||||
interrupts =
|
||||
<GIC_SPI 721 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "swr_master_irq", "swr_wake_irq";
|
||||
qcom,swr-wakeup-required = <1>;
|
||||
qcom,swr-num-ports = <5>;
|
||||
qcom,swr-port-mapping = <1 SWRM_TX_PCM_OUT 0x3>,
|
||||
<2 SWRM_TX1_CH1 0x1>, <2 SWRM_TX1_CH2 0x2>,
|
||||
<2 SWRM_TX1_CH3 0x4>, <2 SWRM_TX1_CH4 0x8>,
|
||||
<3 SWRM_TX2_CH1 0x1>, <3 SWRM_TX2_CH2 0x2>,
|
||||
<3 SWRM_TX2_CH3 0x4>, <3 SWRM_TX2_CH4 0x8>,
|
||||
<4 SWRM_TX3_CH1 0x1>, <4 SWRM_TX3_CH2 0x2>,
|
||||
<4 SWRM_TX3_CH3 0x4>, <4 SWRM_TX3_CH4 0x8>,
|
||||
<5 SWRM_TX_PCM_IN 0x3>;
|
||||
qcom,swr-num-dev = <5>;
|
||||
qcom,swr-clock-stop-mode0 = <1>;
|
||||
qcom,swr-mstr-irq-wakeup-capable = <1>;
|
||||
qcom,is-always-on = <1>;
|
||||
wcd9378_tx_slave: wcd9378-tx-slave {
|
||||
compatible = "qcom,wcd9378-slave";
|
||||
reg = <0x10 0x01170223>;
|
||||
};
|
||||
|
||||
wcd939x_tx_slave: wcd939x-tx-slave {
|
||||
status = "disabled";
|
||||
compatible = "qcom,wcd939x-slave";
|
||||
reg = <0x0E 0x01170223>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tx_macro: tx-macro@6AE0000 {
|
||||
compatible = "qcom,lpass-cdc-tx-macro";
|
||||
reg = <0x6AE0000 0x0>;
|
||||
qcom,default-clk-id = <TX_CORE_CLK>;
|
||||
/*
|
||||
* Clk divding factors for each DMIC pair.
|
||||
* Valid entries for each DMIC pair:
|
||||
* 2, 3, 4, 6, 8, 16
|
||||
*
|
||||
* These factors are translated to corresponding config values
|
||||
* for the following registers,
|
||||
* -- LPASS_VA_TOP_CSR_DMIC0_CTL,
|
||||
* -- LPASS_VA_TOP_CSR_DMIC1_CTL,
|
||||
* -- LPASS_VA_TOP_CSR_DMIC2_CTL,
|
||||
* -- LPASS_VA_TOP_CSR_DMIC3_CTL,
|
||||
*/
|
||||
qcom,tx-dmic-clk-div-factor = <4 4 4 4>;
|
||||
qcom,is-used-swr-gpio = <0>;
|
||||
};
|
||||
|
||||
rx_macro: rx-macro@6AC0000 {
|
||||
compatible = "qcom,lpass-cdc-rx-macro";
|
||||
reg = <0x6AC0000 0x0>;
|
||||
qcom,rx-swr-gpios = <&rx_swr_gpios>;
|
||||
qcom,rx_mclk_mode_muxsel = <0x06BEC0D8>;
|
||||
qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x03 0x48>;
|
||||
qcom,default-clk-id = <RX_TX_CORE_CLK>;
|
||||
clock-names = "rx_mclk2_2x_clk";
|
||||
clocks = <&clock_audio_rx_mclk2_2x_clk 0>;
|
||||
swr1: rx_swr_master {
|
||||
compatible = "qcom,swr-mstr";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "lpass_core_hw_vote",
|
||||
"lpass_audio_hw_vote";
|
||||
clocks = <&lpass_core_hw_vote 0>,
|
||||
<&lpass_audio_hw_vote 0>;
|
||||
qcom,swr_master_id = <2>;
|
||||
qcom,mipi-sdw-block-packing-mode = <1>;
|
||||
swrm-io-base = <0x6ad0000 0x0>;
|
||||
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "swr_master_irq";
|
||||
qcom,swr-num-ports = <12>;
|
||||
qcom,swr-port-mapping = <1 HPH_L 0x1>,
|
||||
<1 HPH_R 0x2>, <2 CLSH 0x3>,
|
||||
<3 COMP_L 0x1>, <3 COMP_R 0x2>,
|
||||
<4 LO 0x1>, <5 DSD_L 0x1>,
|
||||
<5 DSD_R 0x2>, <6 PCM_OUT1 0x01>,
|
||||
<7 GPPO 0x03>, <8 HAPT 0x03>,
|
||||
<9 HIFI_PCM_L 0x01>, <9 HIFI_PCM_R 0x2>,
|
||||
<10 HPTH 0x03>, <11 CMPT 0x03>, <12 IPCM 0x03>;
|
||||
|
||||
/* num-dev is 2 if WCD RX and PMIC SWR Slaves are connected */
|
||||
/* num-dev is 1 if only WCD RX slave is connected */
|
||||
qcom,swr-num-dev = <2>;
|
||||
qcom,swr-clock-stop-mode0 = <1>;
|
||||
swr_haptics: swr_haptics@f0170220 {
|
||||
compatible = "qcom,pmih010x-swr-haptics";
|
||||
reg = <0x03 0xf0170220>;
|
||||
qcom,rx_swr_ch_map = <0 0x01 0x01 0 PCM_OUT1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wcd9378_rx_slave: wcd9378-rx-slave {
|
||||
compatible = "qcom,wcd9378-slave";
|
||||
reg = <0x10 0x01170224>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
wcd939x_rx_slave: wcd939x-rx-slave {
|
||||
compatible = "qcom,wcd939x-slave";
|
||||
reg = <0x0E 0x01170224>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
wsa_macro: wsa-macro@6B00000 {
|
||||
compatible = "qcom,lpass-cdc-wsa-macro";
|
||||
reg = <0x6B00000 0x0>;
|
||||
wsa_data_fs_ctl_reg = <0x6B6F000>;
|
||||
qcom,wsa-swr-gpios = <&wsa_swr_gpios>;
|
||||
qcom,wsa-bat-cfgs= <1>, <1>;
|
||||
qcom,wsa-rloads= <2>, <2>;
|
||||
qcom,wsa-system-gains= <0 9>, <0 9>;
|
||||
qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x03 0x48>;
|
||||
qcom,default-clk-id = <WSA_TX_CORE_CLK>;
|
||||
qcom,thermal-max-state = <11>;
|
||||
qcom,noise-gate-mode = <2>;
|
||||
#cooling-cells = <2>;
|
||||
swr0: wsa_swr_master {
|
||||
compatible = "qcom,swr-mstr";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "lpass_core_hw_vote",
|
||||
"lpass_audio_hw_vote";
|
||||
clocks = <&lpass_core_hw_vote 0>,
|
||||
<&lpass_audio_hw_vote 0>;
|
||||
qcom,swr_master_id = <1>;
|
||||
qcom,mipi-sdw-block-packing-mode = <0>;
|
||||
swrm-io-base = <0x6b10000 0x0>;
|
||||
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "swr_master_irq";
|
||||
qcom,swr-num-ports = <13>;
|
||||
qcom,swr-clock-stop-mode0 = <1>;
|
||||
qcom,swr-port-mapping = <1 SPKR_L 0x1>,
|
||||
<2 SPKR_L_COMP 0xF>, <3 SPKR_L_BOOST 0x3>,
|
||||
<4 SPKR_R 0x1>, <5 SPKR_R_COMP 0xF>,
|
||||
<6 SPKR_R_BOOST 0x3>, <7 PBR 0x3>,
|
||||
<8 SPKR_HAPT 0x3>, <9 OCPM 0x3>,
|
||||
<10 SPKR_L_VI 0x3>, <11 SPKR_R_VI 0x3>,
|
||||
<12 SPKR_IPCM 0x3>, <13 CPS 0x3>;
|
||||
qcom,swr-num-dev = <2>;
|
||||
qcom,dynamic-port-map-supported = <0>;
|
||||
wsa884x_0220: wsa884x@02170220 {
|
||||
compatible = "qcom,wsa884x";
|
||||
reg = <0x4 0x2170220>;
|
||||
qcom,spkr-sd-n-node = <&wsa_spkr_en02>;
|
||||
qcom,lpass-cdc-handle = <&lpass_cdc>;
|
||||
qcom,wsa-macro-handle = <&wsa_macro>;
|
||||
qcom,swr-wsa-port-params =
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>,
|
||||
<OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>,
|
||||
<OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>,
|
||||
<OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>,
|
||||
<OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>,
|
||||
<OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>,
|
||||
<OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>,
|
||||
<OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>,
|
||||
<OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>;
|
||||
cdc-vdd-1p8-supply = <&L7B>;
|
||||
qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-1p8-current = <20000>;
|
||||
qcom,cdc-vdd-1p8-lpm-supported = <1>;
|
||||
qcom,cdc-static-supplies = "cdc-vdd-1p8";
|
||||
sound-name-prefix = "SpkrLeft";
|
||||
};
|
||||
|
||||
wsa884x_0221: wsa884x@02170221 {
|
||||
compatible = "qcom,wsa884x";
|
||||
reg = <0x4 0x2170221>;
|
||||
qcom,spkr-sd-n-node = <&wsa_spkr_en13>;
|
||||
qcom,lpass-cdc-handle = <&lpass_cdc>;
|
||||
qcom,wsa-macro-handle = <&wsa_macro>;
|
||||
qcom,swr-wsa-port-params =
|
||||
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>,
|
||||
<OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>,
|
||||
<OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>,
|
||||
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>,
|
||||
<OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>,
|
||||
<OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>,
|
||||
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>,
|
||||
<OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>,
|
||||
<OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>,
|
||||
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>,
|
||||
<OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>,
|
||||
<OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>;
|
||||
cdc-vdd-1p8-supply = <&L7B>;
|
||||
qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-1p8-current = <20000>;
|
||||
qcom,cdc-vdd-1p8-lpm-supported = <1>;
|
||||
qcom,cdc-static-supplies = "cdc-vdd-1p8";
|
||||
sound-name-prefix = "SpkrRight";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
wcd939x_codec: wcd939x-codec {
|
||||
compatible = "qcom,wcd939x-codec";
|
||||
status = "disabled";
|
||||
qcom,split-codec = <1>;
|
||||
qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
|
||||
<0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>,
|
||||
<2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
|
||||
<3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
|
||||
<4 DSD_R 0x2 0 DSD_R>, <5 HIFI_PCM_L 0x1 0 HIFI_PCM_L>,
|
||||
<5 HIFI_PCM_R 0x2 0 HIFI_PCM_R>;
|
||||
|
||||
qcom,tx_swr_ch_map = <0 ADC1 0x1 0 SWRM_TX1_CH1>,
|
||||
<0 ADC2 0x2 0 SWRM_TX1_CH2>,
|
||||
<1 ADC3 0x1 0 SWRM_TX1_CH3>,
|
||||
<1 ADC4 0x2 0 SWRM_TX1_CH4>,
|
||||
<2 DMIC0 0x1 0 SWRM_TX2_CH1>,
|
||||
<2 DMIC1 0x2 0 SWRM_TX2_CH2>,
|
||||
<2 MBHC 0x4 0 SWRM_TX2_CH3>,
|
||||
<2 DMIC2 0x4 0 SWRM_TX2_CH3>,
|
||||
<2 DMIC3 0x8 0 SWRM_TX2_CH4>,
|
||||
<3 DMIC4 0x1 0 SWRM_TX3_CH1>,
|
||||
<3 DMIC5 0x2 0 SWRM_TX3_CH2>,
|
||||
<3 DMIC6 0x4 0 SWRM_TX3_CH3>,
|
||||
<3 DMIC7 0x8 0 SWRM_TX3_CH4>;
|
||||
|
||||
qcom,swr-tx-port-params =
|
||||
<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL0 LANE2>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,
|
||||
<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL1 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,
|
||||
<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL2 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL2 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>;
|
||||
qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>;
|
||||
qcom,rx-slave = <&wcd939x_rx_slave>;
|
||||
qcom,tx-slave = <&wcd939x_tx_slave>;
|
||||
|
||||
cdc-vdd-rx-supply = <&L7B>;
|
||||
qcom,cdc-vdd-rx-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-rx-current = <45000>;
|
||||
qcom,cdc-vdd-rx-lpm-supported = <1>;
|
||||
|
||||
cdc-vdd-tx-supply = <&L7B>;
|
||||
qcom,cdc-vdd-tx-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-tx-current = <45000>;
|
||||
qcom,cdc-vdd-tx-lpm-supported = <1>;
|
||||
|
||||
cdc-vdd-buck-supply = <&L7B>;
|
||||
qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-buck-current = <650000>;
|
||||
qcom,cdc-vdd-buck-lpm-supported = <1>;
|
||||
|
||||
cdc-vdd-mic-bias-supply = <&BOB>;
|
||||
qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>;
|
||||
qcom,cdc-vdd-mic-bias-current = <30000>;
|
||||
|
||||
cdc-vdd-px-supply = <&L5B>;
|
||||
qcom,cdc-vdd-px-voltage = <1200000 1200000>;
|
||||
qcom,cdc-vdd-px-current = <15000>;
|
||||
qcom,cdc-vdd-px-lpm-supported = <1>;
|
||||
|
||||
qcom,cdc-vdd-px-rem-supported = <1>;
|
||||
|
||||
qcom,cdc-micbias1-mv = <1800>;
|
||||
qcom,cdc-micbias2-mv = <1800>;
|
||||
qcom,cdc-micbias3-mv = <1800>;
|
||||
qcom,cdc-micbias4-mv = <1800>;
|
||||
|
||||
qcom,cdc-static-supplies = "cdc-vdd-rx",
|
||||
"cdc-vdd-tx",
|
||||
"cdc-vdd-mic-bias";
|
||||
qcom,cdc-on-demand-supplies = "cdc-vdd-buck",
|
||||
"cdc-vdd-px";
|
||||
|
||||
wcd_mb1_reg: qcom,wcd-mb1-reg {
|
||||
regulator-name = "wcd-mb1-reg";
|
||||
};
|
||||
|
||||
wcd_mb2_reg: qcom,wcd-mb2-reg {
|
||||
regulator-name = "wcd-mb2-reg";
|
||||
};
|
||||
|
||||
wcd_mb3_reg: qcom,wcd-mb3-reg {
|
||||
regulator-name = "wcd-mb3-reg";
|
||||
};
|
||||
|
||||
wcd_mb4_reg: qcom,wcd-mb4-reg {
|
||||
regulator-name = "wcd-mb4-reg";
|
||||
};
|
||||
};
|
||||
|
||||
wcd9378_codec: wcd9378-codec {
|
||||
compatible = "qcom,wcd9378-codec";
|
||||
qcom,split-codec = <1>;
|
||||
qcom,wcd-mode = <1>;
|
||||
qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
|
||||
<0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>,
|
||||
<2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
|
||||
<3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
|
||||
<4 DSD_R 0x2 0 DSD_R>;
|
||||
qcom,tx_swr_ch_map = <0 ADC1 0x1 0 SWRM_TX1_CH1>,
|
||||
<1 ADC2 0x1 0 SWRM_TX1_CH2>,
|
||||
<2 ADC3 0x1 0 SWRM_TX1_CH3>,
|
||||
<3 DMIC0 0x4 0 SWRM_TX2_CH1>,
|
||||
<3 DMIC1 0x8 0 SWRM_TX2_CH2>,
|
||||
<3 MBHC 0x4 0 SWRM_TX2_CH3>,
|
||||
<4 DMIC2 0x1 0 SWRM_TX2_CH3>,
|
||||
<4 DMIC3 0x2 0 SWRM_TX2_CH4>,
|
||||
<4 DMIC4 0x3 0 SWRM_TX3_CH1>,
|
||||
<4 DMIC5 0x4 0 SWRM_TX3_CH2>;
|
||||
qcom,swr-tx-port-params =
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE1>,
|
||||
<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL1 LANE0>,
|
||||
<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL1 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,
|
||||
<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL2 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL2 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,
|
||||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>;
|
||||
qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>;
|
||||
qcom,rx-slave = <&wcd9378_rx_slave>;
|
||||
qcom,tx-slave = <&wcd9378_tx_slave>;
|
||||
|
||||
cdc-vdd-rxtx-supply = <&L7B>;
|
||||
qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-rxtx-current = <30000>;
|
||||
qcom,cdc-vdd-rxtx-lpm-supported = <1>;
|
||||
|
||||
cdc-vdd-io-supply = <&L5B>;
|
||||
qcom,cdc-vdd-io-voltage = <1200000 1200000>;
|
||||
qcom,cdc-vdd-io-current = <20000>;
|
||||
qcom,cdc-vdd-io-lpm-supported = <1>;
|
||||
|
||||
cdc-vdd-buck-supply = <&L7B>;
|
||||
qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
|
||||
qcom,cdc-vdd-buck-current = <650000>;
|
||||
qcom,cdc-vdd-buck-lpm-supported = <1>;
|
||||
|
||||
cdc-vdd-mic-bias-supply = <&BOB>;
|
||||
qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>;
|
||||
qcom,cdc-vdd-mic-bias-current = <40055>;
|
||||
|
||||
qcom,cdc-micbias1-mv = <1800>;
|
||||
qcom,cdc-micbias2-mv = <1800>;
|
||||
qcom,cdc-micbias3-mv = <1800>;
|
||||
|
||||
qcom,cdc-static-supplies = "cdc-vdd-rxtx",
|
||||
"cdc-vdd-io";
|
||||
qcom,cdc-on-demand-supplies = "cdc-vdd-buck";
|
||||
};
|
||||
};
|
||||
|
||||
&lpass_bt_swr {
|
||||
clock-names = "bt_swr_mclk_clk", "bt_swr_mclk_clk_2x",
|
||||
"lpass_core_hw_vote", "lpass_audio_hw_vote";
|
||||
clocks = <&clock_audio_bt_swr_mclk_clk 0>,
|
||||
<&clock_audio_bt_swr_mclk_clk_2x 0>,
|
||||
<&lpass_core_hw_vote 0>,
|
||||
<&lpass_audio_hw_vote 0>;
|
||||
qcom,bt-swr-gpios = <&bt_swr_gpios>;
|
||||
};
|
||||
|
||||
&swr4 {
|
||||
compatible = "qcom,swr-mstr";
|
||||
qcom,swr_master_id = <5>;
|
||||
clock-names = "lpass_core_hw_vote",
|
||||
"lpass_audio_hw_vote";
|
||||
clocks = <&lpass_core_hw_vote 0>,
|
||||
<&lpass_audio_hw_vote 0>;
|
||||
swrm-io-base = <0x06CA0000 0x0>;
|
||||
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "swr_master_irq";
|
||||
qcom,swr-num-ports = <7>;
|
||||
qcom,swr-port-mapping = <1 BT_AUDIO_RX1 0x3>,
|
||||
<2 BT_AUDIO_RX2 0x3>, <3 BT_AUDIO_RX3 0x3>,
|
||||
<5 BT_AUDIO_TX1 0x3>, <6 BT_AUDIO_TX2 0x3>,
|
||||
<7 BT_AUDIO_TX3 0x3>, <8 FM_AUDIO_TX1 0x3>;
|
||||
qcom,swr-num-dev = <1>;
|
||||
};
|
||||
|
||||
&spf_core_platform {
|
||||
tuna_snd: sound {
|
||||
qcom,model = "tuna-mtp-snd-card";
|
||||
qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>, <1>, <1>;
|
||||
qcom,mi2s-tdm-is-hw-vote-needed = <1>, <1>, <1>, <1>, <1>, <1>, <1>;
|
||||
qcom,wcn-bt = <1>;
|
||||
qcom,ext-disp-audio-rx = <0>;
|
||||
qcom,tdm-max-slots = <8>;
|
||||
qcom,tdm-clk-attribute = <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>;
|
||||
qcom,mi2s-clk-attribute = <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>;
|
||||
qcom,audio-core-list = <0>, <1>;
|
||||
qcom,audio-routing =
|
||||
"AMIC1", "Analog Mic1",
|
||||
"AMIC1", "MIC BIAS1",
|
||||
"AMIC2", "Analog Mic2",
|
||||
"AMIC2", "MIC BIAS2",
|
||||
"AMIC3", "Analog Mic3",
|
||||
"AMIC3", "MIC BIAS3",
|
||||
"AMIC4", "Analog Mic4",
|
||||
"AMIC4", "MIC BIAS3",
|
||||
"VA AMIC1", "Analog Mic1",
|
||||
"VA AMIC1", "VA MIC BIAS1",
|
||||
"VA AMIC2", "Analog Mic2",
|
||||
"VA AMIC2", "VA MIC BIAS2",
|
||||
"VA AMIC3", "Analog Mic3",
|
||||
"VA AMIC3", "VA MIC BIAS3",
|
||||
"VA AMIC4", "Analog Mic4",
|
||||
"VA AMIC4", "VA MIC BIAS3",
|
||||
"TX DMIC0", "Digital Mic0",
|
||||
"TX DMIC0", "MIC BIAS3",
|
||||
"TX DMIC1", "Digital Mic1",
|
||||
"TX DMIC1", "MIC BIAS3",
|
||||
"TX DMIC2", "Digital Mic2",
|
||||
"TX DMIC2", "MIC BIAS1",
|
||||
"TX DMIC3", "Digital Mic3",
|
||||
"TX DMIC3", "MIC BIAS1",
|
||||
"IN1_HPHL", "HPHL_OUT",
|
||||
"IN2_HPHR", "HPHR_OUT",
|
||||
"IN3_AUX", "AUX_OUT",
|
||||
"WSA SRC0_INP", "SRC0",
|
||||
"WSA_TX DEC0_INP", "TX DEC0 MUX",
|
||||
"WSA_TX DEC1_INP", "TX DEC1 MUX",
|
||||
"RX_TX DEC0_INP", "TX DEC0 MUX",
|
||||
"RX_TX DEC1_INP", "TX DEC1 MUX",
|
||||
"RX_TX DEC2_INP", "TX DEC2 MUX",
|
||||
"RX_TX DEC3_INP", "TX DEC3 MUX",
|
||||
"SpkrLeft IN", "WSA_SPK1 OUT",
|
||||
"SpkrRight IN", "WSA_SPK2 OUT",
|
||||
"VA SWR_INPUT", "VA_SWR_CLK",
|
||||
"VA_AIF1 CAP", "VA_SWR_CLK",
|
||||
"VA_AIF2 CAP", "VA_SWR_CLK",
|
||||
"VA_AIF3 CAP", "VA_SWR_CLK",
|
||||
"VA DMIC0", "Digital Mic0",
|
||||
"VA DMIC1", "Digital Mic1",
|
||||
"VA DMIC2", "Digital Mic2",
|
||||
"VA DMIC3", "Digital Mic3",
|
||||
"VA DMIC0", "VA MIC BIAS3",
|
||||
"VA DMIC1", "VA MIC BIAS3",
|
||||
"VA DMIC2", "VA MIC BIAS1",
|
||||
"VA DMIC3", "VA MIC BIAS1";
|
||||
qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>;
|
||||
qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>;
|
||||
asoc-codec = <&stub_codec>, <&lpass_cdc>,
|
||||
<&wcd9378_codec>, <&wsa884x_0220>,
|
||||
<&wsa884x_0221>;
|
||||
asoc-codec-names = "msm-stub-codec.1", "lpass-cdc",
|
||||
"wcd9378_codec", "wsa-codec1",
|
||||
"wsa-codec2";
|
||||
qcom,msm-mbhc-usbc-audio-supported = <0>;
|
||||
qcom,msm-mbhc-hphl-swh = <1>;
|
||||
qcom,msm-mbhc-gnd-swh = <1>;
|
||||
qcom,wsa-max-devs = <2>;
|
||||
qcom,msm_audio_ssr_devs = <&audio_gpr>, <&lpi_tlmm>,
|
||||
<&lpass_cdc>, <&lpass_bt_swr>;
|
||||
|
||||
};
|
||||
|
||||
cdc_pri_mi2s_gpios: pri_mi2s_pinctrl {
|
||||
status = "disabled";
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&i2s0_sck_active &i2s0_ws_active
|
||||
&i2s0_sd0_active &i2s0_sd1_active>;
|
||||
pinctrl-1 = <&i2s0_sck_sleep &i2s0_ws_sleep
|
||||
&i2s0_sd0_sleep &i2s0_sd1_sleep>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
fm_i2s1_gpios: fm_i2s1_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&i2s1_sck_active &i2s1_ws_active
|
||||
&i2s1_sd0_active>;
|
||||
pinctrl-1 = <&i2s1_sck_sleep &i2s1_ws_sleep
|
||||
&i2s1_sd0_sleep>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
cdc_quat_mi2s_gpios: quat_mi2s_pinctrl {
|
||||
status = "disabled";
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&quat_mi2s_sck_active &quat_mi2s_ws_active
|
||||
&quat_mi2s_sd0_active &quat_mi2s_sd1_active
|
||||
&quat_mi2s_sd2_active &quat_mi2s_sd3_active>;
|
||||
pinctrl-1 = <&quat_mi2s_sck_sleep &quat_mi2s_ws_sleep
|
||||
&quat_mi2s_sd0_sleep &quat_mi2s_sd1_sleep
|
||||
&quat_mi2s_sd2_sleep &quat_mi2s_sd3_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <138 143>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
cdc_quin_mi2s_gpios: quin_mi2s_pinctrl {
|
||||
status = "disabled";
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&lpi_i2s1_sck_active &lpi_i2s1_ws_active
|
||||
&lpi_i2s1_data0_active &lpi_i2s1_data1_active>;
|
||||
pinctrl-1 = <&lpi_i2s1_sck_sleep &lpi_i2s1_ws_sleep
|
||||
&lpi_i2s1_data0_sleep &lpi_i2s1_data1_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <144 147>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
cdc_sen_mi2s_gpios: sen_mi2s_pinctrl {
|
||||
status = "disabled";
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&lpi_i2s2_sck_active &lpi_i2s2_ws_active
|
||||
&lpi_i2s2_data0_active &lpi_i2s2_data1_active>;
|
||||
pinctrl-1 = <&lpi_i2s2_sck_sleep &lpi_i2s2_ws_sleep
|
||||
&lpi_i2s2_data0_sleep &lpi_i2s2_data1_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <148 151>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
cdc_sep_mi2s_gpios: sep_mi2s_pinctrl {
|
||||
status = "disabled";
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&lpi_i2s3_sck_active &lpi_i2s3_ws_active
|
||||
&lpi_i2s3_data0_active &lpi_i2s3_data1_active>;
|
||||
pinctrl-1 = <&lpi_i2s3_sck_sleep &lpi_i2s3_ws_sleep
|
||||
&lpi_i2s3_data0_sleep &lpi_i2s3_data1_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <153 156>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
wsa_swr_gpios: wsa_swr_clk_data_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&wsa_swr_clk_active &wsa_swr_data_active>;
|
||||
pinctrl-1 = <&wsa_swr_clk_sleep &wsa_swr_data_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <149>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
rx_swr_gpios: rx_swr_clk_data_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&rx_swr_clk_active &rx_swr_data_active
|
||||
&rx_swr_data1_active>;
|
||||
pinctrl-1 = <&rx_swr_clk_sleep &rx_swr_data_sleep
|
||||
&rx_swr_data1_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <142>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
va_swr_gpios: tx_swr_clk_data_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&tx_swr_clk_active &tx_swr_data0_active
|
||||
&tx_swr_data1_active &tx_swr_data2_active>;
|
||||
pinctrl-1 = <&tx_swr_clk_sleep &tx_swr_data0_sleep
|
||||
&tx_swr_data1_sleep &tx_swr_data2_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,chip-wakeup-reg = <0xf18b008>;
|
||||
qcom,chip-wakeup-maskbit = <7>;
|
||||
qcom,chip-wakeup-default-val = <0x1>;
|
||||
qcom,tlmm-pins = <139>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
cdc_dmic01_gpios: cdc_dmic01_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&cdc_dmic01_clk_active &cdc_dmic01_data_active>;
|
||||
pinctrl-1 = <&cdc_dmic01_clk_sleep &cdc_dmic01_data_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <144 145>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
cdc_dmic23_gpios: cdc_dmic23_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&cdc_dmic23_clk_active &cdc_dmic23_data_active>;
|
||||
pinctrl-1 = <&cdc_dmic23_clk_sleep &cdc_dmic23_data_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <146 147>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
cdc_dmic45_gpios: cdc_dmic45_pinctrl {
|
||||
status = "disabled";
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&cdc_dmic45_clk_active &cdc_dmic45_data_active>;
|
||||
pinctrl-1 = <&cdc_dmic45_clk_sleep &cdc_dmic45_data_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <150 151>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
cdc_dmic67_gpios: cdc_dmic67_pinctrl {
|
||||
status = "disabled";
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&cdc_dmic67_clk_active &cdc_dmic67_data_active>;
|
||||
pinctrl-1 = <&cdc_dmic67_clk_sleep &cdc_dmic67_data_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <155 156>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
bt_swr_gpios: bt_swr_clk_data_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&bt_swr_clk_active &bt_swr_data_active>;
|
||||
pinctrl-1 = <&bt_swr_clk_sleep &bt_swr_data_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
wsa_spkr_en02: wsa_spkr_en1_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&spkr_1_sd_n_active>;
|
||||
pinctrl-1 = <&spkr_1_sd_n_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
};
|
||||
|
||||
wsa_spkr_en13: wsa_spkr_en2_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&spkr_2_sd_n_active>;
|
||||
pinctrl-1 = <&spkr_2_sd_n_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
};
|
||||
|
||||
wcd_rst_gpio: msm_cdc_pinctrl@32 {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&wcd_reset_active>;
|
||||
pinctrl-1 = <&wcd_reset_sleep>;
|
||||
};
|
||||
|
||||
clock_audio_va_1: va_core_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK>;
|
||||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||||
qcom,codec-lpass-clk-id = <0x307>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_wsa_1: wsa_core_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_2>;
|
||||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||||
qcom,codec-lpass-clk-id = <0x309>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_rx_1: rx_core_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_4>;
|
||||
qcom,codec-lpass-ext-clk-freq = <22579200>;
|
||||
qcom,codec-lpass-clk-id = <0x30E>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_rx_tx: rx_core_tx_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_10>;
|
||||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||||
qcom,codec-lpass-clk-id = <0x312>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_tx_1: tx_core_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_6>;
|
||||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||||
qcom,codec-lpass-clk-id = <0x30C>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_wsa_tx: wsa_core_tx_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_11>;
|
||||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||||
qcom,codec-lpass-clk-id = <0x314>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_rx_mclk2_2x_clk: rx_mclk2_2x_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_13>;
|
||||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||||
qcom,codec-lpass-clk-id = <0x318>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_bt_swr_mclk_clk: bt_swr_mclk_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_15>;
|
||||
qcom,codec-lpass-ext-clk-freq = <24576000>;
|
||||
qcom,codec-lpass-clk-id = <0x31A>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_bt_swr_mclk_clk_2x: bt_swr_mclk_clk_2x {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_16>;
|
||||
qcom,codec-lpass-ext-clk-freq = <24576000>;
|
||||
qcom,codec-lpass-clk-id = <0x31B>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&adsp_loader {
|
||||
status = "ok";
|
||||
};
|
||||
17
qcom/audio/tuna-audio-qrd.dts
Normal file
17
qcom/audio/tuna-audio-qrd.dts
Normal file
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "tuna-audio-qrd.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Tuna QRD";
|
||||
compatible = "qcom,tuna-qrd", "qcom,tuna", "qcom,tunap-qrd", "qcom,tunap",
|
||||
"qcom,qrd";
|
||||
qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>;
|
||||
qcom,board-id = <11 0>;
|
||||
};
|
||||
148
qcom/audio/tuna-audio-qrd.dtsi
Normal file
148
qcom/audio/tuna-audio-qrd.dtsi
Normal file
@@ -0,0 +1,148 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
#include "tuna-audio-overlay.dtsi"
|
||||
&tx_swr_clk_active {
|
||||
config {
|
||||
drive-strength = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&tx_swr_data0_active {
|
||||
config {
|
||||
drive-strength = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&tx_swr_data1_active {
|
||||
config {
|
||||
drive-strength = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&tx_swr_data2_active {
|
||||
config {
|
||||
drive-strength = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&swr0 {
|
||||
wsa884x_0220: wsa884x@02170220 {
|
||||
qcom,spkr-sd-n-node = <&wsa_spkr_en13>;
|
||||
sound-name-prefix = "SpkrLeft";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
wsa884x_0221: wsa884x@02170221 {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
&wcd9378_codec {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wcd9378_rx_slave {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wcd9378_tx_slave {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wcd939x_tx_slave {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wcd939x_rx_slave {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wsa_macro {
|
||||
qcom,wsa-bat-cfgs = <1>, <1>;
|
||||
};
|
||||
|
||||
&swr_haptics {
|
||||
status = "okay";
|
||||
swr-slave-supply = <&hap_swr_slave_reg>;
|
||||
};
|
||||
|
||||
&wcd939x_codec {
|
||||
status = "okay";
|
||||
/* 0 for digital crosstalk disabled,
|
||||
* 1 for digital crosstalk with local sensed a-xtalk enabled, and
|
||||
* 2 for digital crosstalk with remote sensed a-xtalk enabled.
|
||||
*/
|
||||
qcom,usbcss-hs-xtalk-config = <0>;
|
||||
qcom,usbcss-hs-rdson = <600>;
|
||||
qcom,usbcss-hs-r2 = <7550>;
|
||||
qcom,usbcss-hs-r3 = <1>;
|
||||
qcom,usbcss-hs-r4 = <330>;
|
||||
qcom,usbcss-hs-r5 = <5>;
|
||||
qcom,usbcss-hs-r6 = <1>;
|
||||
qcom,usbcss-hs-r7 = <5>;
|
||||
qcom,usbcss-hs-lin-k-aud = <13>;
|
||||
qcom,usbcss-hs-lin-k-gnd = <13>;
|
||||
};
|
||||
|
||||
&cdc_dmic01_gpios {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cdc_dmic23_gpios {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&tuna_snd {
|
||||
qcom,model = "tuna-qrd-snd-card";
|
||||
qcom,audio-routing =
|
||||
"AMIC1", "Analog Mic1",
|
||||
"AMIC1", "MIC BIAS1",
|
||||
"AMIC2", "Analog Mic2",
|
||||
"AMIC2", "MIC BIAS2",
|
||||
"AMIC3", "Analog Mic3",
|
||||
"AMIC3", "MIC BIAS3",
|
||||
"AMIC4", "Analog Mic4",
|
||||
"AMIC4", "MIC BIAS4",
|
||||
"VA AMIC1", "Analog Mic1",
|
||||
"VA AMIC1", "VA MIC BIAS1",
|
||||
"VA AMIC2", "Analog Mic2",
|
||||
"VA AMIC2", "VA MIC BIAS2",
|
||||
"VA AMIC3", "Analog Mic3",
|
||||
"VA AMIC3", "VA MIC BIAS3",
|
||||
"VA AMIC4", "Analog Mic4",
|
||||
"VA AMIC4", "VA MIC BIAS4",
|
||||
"IN1_HPHL", "HPHL_OUT",
|
||||
"IN2_HPHR", "HPHR_OUT",
|
||||
"IN3_EAR", "AUX_OUT",
|
||||
"HAP_IN", "PCM_OUT",
|
||||
"WSA SRC0_INP", "SRC0",
|
||||
"WSA_TX DEC0_INP", "TX DEC0 MUX",
|
||||
"WSA_TX DEC1_INP", "TX DEC1 MUX",
|
||||
"RX_TX DEC0_INP", "TX DEC0 MUX",
|
||||
"RX_TX DEC1_INP", "TX DEC1 MUX",
|
||||
"RX_TX DEC2_INP", "TX DEC2 MUX",
|
||||
"RX_TX DEC3_INP", "TX DEC3 MUX",
|
||||
"SpkrLeft IN", "WSA_SPK1 OUT",
|
||||
"TX SWR_INPUT", "WCD_TX_OUTPUT",
|
||||
"VA SWR_INPUT", "VA_SWR_CLK",
|
||||
"VA SWR_INPUT", "WCD_TX_OUTPUT",
|
||||
"VA_AIF1 CAP", "VA_SWR_CLK",
|
||||
"VA_AIF2 CAP", "VA_SWR_CLK",
|
||||
"VA_AIF3 CAP", "VA_SWR_CLK";
|
||||
asoc-codec = <&stub_codec>, <&lpass_cdc>, <&swr_haptics>,
|
||||
<&wcd939x_codec>, <&wsa884x_0220>;
|
||||
asoc-codec-names = "msm-stub-codec.1", "lpass-cdc","swr-haptics",
|
||||
"wcd939x_codec", "wsa-codec1";
|
||||
qcom,ext-disp-audio-rx = <1>;
|
||||
qcom,wsa-max-devs = <1>;
|
||||
qcom,wcd-disable-legacy-surge;
|
||||
wcd939x-i2c-handle = <&wcd_usbss>;
|
||||
qcom,msm-mbhc-usbc-audio-supported = <1>;
|
||||
qcom,msm-mbhc-hphl-swh = <0>;
|
||||
qcom,msm-mbhc-gnd-swh = <0>;
|
||||
qcom,msm-mbhc-hs-mic-max-threshold-mv = <1670>;
|
||||
};
|
||||
|
||||
|
||||
16
qcom/audio/tuna-audio-rcm.dts
Normal file
16
qcom/audio/tuna-audio-rcm.dts
Normal file
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "tuna-audio-cdp.dtsi"
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Tuna RCM";
|
||||
compatible = "qcom,tuna-rcm", "qcom,tuna", "qcom,tunap-rcm", "qcom,tunap",
|
||||
"qcom,rcm";
|
||||
qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>;
|
||||
qcom,board-id = <21 0>;
|
||||
};
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user