859bb7cd14
git-subtree-dir: qcom/audio git-subtree-mainline:573108dc30git-subtree-split:6c0f9e7566
813 lines
27 KiB
Plaintext
813 lines
27 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <bindings/qcom,audio-ext-clk.h>
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#include <bindings/qcom,lpass-cdc-clk-rsc.h>
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#include <bindings/audio-codec-port-types.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "pineapple-lpi.dtsi"
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&lpass_cdc {
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qcom,num-macros = <4>;
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qcom,lpass-cdc-version = <7>;
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#address-cells = <1>;
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#size-cells = <1>;
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lpass-cdc-clk-rsc-mngr {
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compatible = "qcom,lpass-cdc-clk-rsc-mngr";
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qcom,fs-gen-sequence = <0x3000 0x1 0x1>, <0x3004 0x3 0x3>,
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<0x3004 0x3 0x1>, <0x3080 0x2 0x2>;
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qcom,rx_mclk_mode_muxsel = <0x06BEC0D8>;
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qcom,wsa_mclk_mode_muxsel = <0x06BEA100>;
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qcom,va_mclk_mode_muxsel = <0x06E28000>;
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clock-names = "tx_core_clk", "rx_core_clk", "wsa_core_clk",
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"wsa2_core_clk", "rx_tx_core_clk",
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"wsa_tx_core_clk", "wsa2_tx_core_clk", "va_core_clk";
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clocks = <&clock_audio_tx_1 0>, <&clock_audio_rx_1 0>,
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<&clock_audio_wsa_1 0>,
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<&clock_audio_wsa_2 0>, <&clock_audio_rx_tx 0>,
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<&clock_audio_wsa_tx 0>, <&clock_audio_wsa2_tx 0>,
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<&clock_audio_va_1 0>;
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};
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va_macro: va-macro@6D44000 {
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compatible = "qcom,lpass-cdc-va-macro";
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reg = <0x6D44000 0x0>;
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clock-names = "lpass_audio_hw_vote";
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clocks = <&lpass_audio_hw_vote 0>;
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qcom,va-dmic-sample-rate = <600000>;
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qcom,va-clk-mux-select = <1>;
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qcom,va-island-mode-muxsel = <0x06E28000>;
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qcom,default-clk-id = <TX_CORE_CLK>;
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qcom,use-clk-id = <VA_CORE_CLK>;
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qcom,is-used-swr-gpio = <1>;
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qcom,va-swr-gpios = <&va_swr_gpios>;
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swr2: va_swr_master {
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compatible = "qcom,swr-mstr";
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#address-cells = <2>;
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#size-cells = <0>;
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clock-names = "lpass_core_hw_vote",
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"lpass_audio_hw_vote";
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clocks = <&lpass_core_hw_vote 0>,
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<&lpass_audio_hw_vote 0>;
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qcom,swr_master_id = <3>;
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qcom,mipi-sdw-block-packing-mode = <1>;
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swrm-io-base = <0x6d30000 0x0>;
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interrupts =
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<GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "swr_master_irq", "swr_wake_irq";
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qcom,swr-wakeup-required = <1>;
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qcom,swr-num-ports = <5>;
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qcom,swr-port-mapping = <1 SWRM_TX_PCM_OUT 0x3>,
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<2 SWRM_TX1_CH1 0x1>, <2 SWRM_TX1_CH2 0x2>,
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<2 SWRM_TX1_CH3 0x4>, <2 SWRM_TX1_CH4 0x8>,
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<3 SWRM_TX2_CH1 0x1>, <3 SWRM_TX2_CH2 0x2>,
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<3 SWRM_TX2_CH3 0x4>, <3 SWRM_TX2_CH4 0x8>,
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<4 SWRM_TX3_CH1 0x1>, <4 SWRM_TX3_CH2 0x2>,
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<4 SWRM_TX3_CH3 0x4>, <4 SWRM_TX3_CH4 0x8>,
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<5 SWRM_TX_PCM_IN 0x3>;
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qcom,swr-num-dev = <5>;
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qcom,swr-clock-stop-mode0 = <1>;
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qcom,swr-mstr-irq-wakeup-capable = <1>;
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qcom,is-always-on = <1>;
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wcd939x_tx_slave: wcd939x-tx-slave {
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compatible = "qcom,wcd939x-slave";
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reg = <0x0E 0x01170223>;
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};
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swr_dmic_04: dmic_swr@58350223 {
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compatible = "qcom,swr-dmic";
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reg = <0x08 0x58350223>;
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sound-name-prefix = "SWR_MIC3";
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qcom,codec-name = "swr-dmic.04";
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qcom,swr-dmic-supply = <3>;
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qcom,wcd-handle = <&wcd939x_codec>;
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status = "disabled";
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};
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swr_dmic_03: dmic_swr@58350222 {
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compatible = "qcom,swr-dmic";
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reg = <0x08 0x58350222>;
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sound-name-prefix = "SWR_MIC2";
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qcom,codec-name = "swr-dmic.03";
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qcom,swr-dmic-supply = <1>;
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qcom,wcd-handle = <&wcd939x_codec>;
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status = "disabled";
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};
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swr_dmic_02: dmic_swr@58350221 {
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compatible = "qcom,swr-dmic";
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reg = <0x08 0x58350221>;
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sound-name-prefix = "SWR_MIC1";
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qcom,codec-name = "swr-dmic.02";
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qcom,swr-dmic-supply = <1>;
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qcom,wcd-handle = <&wcd939x_codec>;
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status = "disabled";
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};
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swr_dmic_01: dmic_swr@58350220 {
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compatible = "qcom,swr-dmic";
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reg = <0x08 0x58350220>;
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sound-name-prefix = "SWR_MIC0";
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qcom,codec-name = "swr-dmic.01";
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qcom,swr-dmic-supply = <3>;
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qcom,wcd-handle = <&wcd939x_codec>;
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status = "disabled";
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};
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};
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};
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tx_macro: tx-macro@6AE0000 {
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compatible = "qcom,lpass-cdc-tx-macro";
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reg = <0x6AE0000 0x0>;
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qcom,default-clk-id = <TX_CORE_CLK>;
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qcom,tx-dmic-sample-rate = <2400000>;
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qcom,is-used-swr-gpio = <0>;
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};
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rx_macro: rx-macro@6AC0000 {
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compatible = "qcom,lpass-cdc-rx-macro";
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reg = <0x6AC0000 0x0>;
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qcom,rx-swr-gpios = <&rx_swr_gpios>;
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qcom,rx_mclk_mode_muxsel = <0x06BEC0D8>;
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qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x03 0x48>;
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qcom,default-clk-id = <RX_TX_CORE_CLK>;
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clock-names = "rx_mclk2_2x_clk";
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clocks = <&clock_audio_rx_mclk2_2x_clk 0>;
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swr1: rx_swr_master {
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compatible = "qcom,swr-mstr";
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#address-cells = <2>;
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#size-cells = <0>;
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clock-names = "lpass_core_hw_vote",
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"lpass_audio_hw_vote";
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clocks = <&lpass_core_hw_vote 0>,
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<&lpass_audio_hw_vote 0>;
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qcom,swr_master_id = <2>;
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qcom,mipi-sdw-block-packing-mode = <1>;
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swrm-io-base = <0x6ad0000 0x0>;
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interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "swr_master_irq";
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qcom,swr-num-ports = <12>;
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qcom,swr-port-mapping = <1 HPH_L 0x1>,
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<1 HPH_R 0x2>, <2 CLSH 0x3>,
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<3 COMP_L 0x1>, <3 COMP_R 0x2>,
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<4 LO 0x1>, <5 DSD_L 0x1>,
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<5 DSD_R 0x2>, <6 PCM_OUT1 0x01>,
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<7 GPPO 0x03>, <8 HAPT 0x03>,
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<9 HIFI_PCM_L 0x01>, <9 HIFI_PCM_R 0x2>,
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<10 HPTH 0x03>, <11 CMPT 0x03>, <12 IPCM 0x03>;
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qcom,swr-num-dev = <2>;
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qcom,swr-clock-stop-mode0 = <1>;
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swr_haptics: swr_haptics@f0170220 {
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compatible = "qcom,pm8550b-swr-haptics";
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reg = <0x02 0xf0170220>;
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swr-slave-supply = <&hap_swr_slave_reg>;
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qcom,rx_swr_ch_map = <0 0x01 0x01 0 PCM_OUT1>;
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status = "disabled";
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};
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wcd939x_rx_slave: wcd939x-rx-slave {
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compatible = "qcom,wcd939x-slave";
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reg = <0x0E 0x01170224>;
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};
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};
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};
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wsa_macro: wsa-macro@6B00000 {
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compatible = "qcom,lpass-cdc-wsa-macro";
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reg = <0x6B00000 0x0>;
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wsa_data_fs_ctl_reg = <0x6B6F000>;
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qcom,wsa-swr-gpios = <&wsa_swr_gpios>;
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qcom,wsa-bat-cfgs= <1>, <1>;
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qcom,wsa-rloads= <2>, <2>;
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qcom,wsa-system-gains= <0 9>, <0 9>;
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qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x03 0x48>;
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qcom,default-clk-id = <WSA_TX_CORE_CLK>;
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qcom,thermal-max-state = <11>;
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qcom,noise-gate-mode = <2>;
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#cooling-cells = <2>;
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swr0: wsa_swr_master {
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compatible = "qcom,swr-mstr";
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#address-cells = <2>;
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#size-cells = <0>;
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clock-names = "lpass_core_hw_vote",
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"lpass_audio_hw_vote";
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clocks = <&lpass_core_hw_vote 0>,
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<&lpass_audio_hw_vote 0>;
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qcom,swr_master_id = <1>;
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qcom,mipi-sdw-block-packing-mode = <0>;
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swrm-io-base = <0x6b10000 0x0>;
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interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "swr_master_irq";
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qcom,swr-num-ports = <13>;
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qcom,swr-clock-stop-mode0 = <1>;
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qcom,swr-port-mapping = <1 SPKR_L 0x1>,
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<2 SPKR_L_COMP 0xF>, <3 SPKR_L_BOOST 0x3>,
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<4 SPKR_R 0x1>, <5 SPKR_R_COMP 0xF>,
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<6 SPKR_R_BOOST 0x3>, <7 PBR 0x3>,
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<8 SPKR_HAPT 0x3>, <9 OCPM 0x3>,
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<10 SPKR_L_VI 0x3>, <11 SPKR_R_VI 0x3>,
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<12 SPKR_IPCM 0x3>, <13 CPS 0x3>;
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qcom,swr-num-dev = <2>;
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qcom,dynamic-port-map-supported = <0>;
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wsa884x_0220: wsa884x@02170220 {
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compatible = "qcom,wsa884x";
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reg = <0x4 0x2170220>;
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qcom,spkr-sd-n-node = <&wsa_spkr_en02>;
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qcom,lpass-cdc-handle = <&lpass_cdc>;
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qcom,wsa-macro-handle = <&wsa_macro>;
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qcom,swr-wsa-port-params =
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<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>, <OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>,
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<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>, <OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>,
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<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>, <OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>,
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<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>, <OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>;
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cdc-vdd-1p8-supply = <&L15B>;
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qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
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qcom,cdc-vdd-1p8-current = <20000>;
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qcom,cdc-vdd-1p8-lpm-supported = <1>;
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qcom,cdc-static-supplies = "cdc-vdd-1p8";
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sound-name-prefix = "SpkrLeft";
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};
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wsa884x_0221: wsa884x@02170221 {
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compatible = "qcom,wsa884x";
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reg = <0x4 0x2170221>;
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qcom,spkr-sd-n-node = <&wsa_spkr_en13>;
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qcom,lpass-cdc-handle = <&lpass_cdc>;
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qcom,wsa-macro-handle = <&wsa_macro>;
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qcom,swr-wsa-port-params =
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<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>, <OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>, <OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>,
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<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>, <OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>, <OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>,
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<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>, <OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>, <OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>,
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<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>, <OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>, <OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>;
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cdc-vdd-1p8-supply = <&L15B>;
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qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
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qcom,cdc-vdd-1p8-current = <20000>;
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qcom,cdc-vdd-1p8-lpm-supported = <1>;
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qcom,cdc-static-supplies = "cdc-vdd-1p8";
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sound-name-prefix = "SpkrRight";
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};
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};
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};
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wsa2_macro: wsa2-macro@6AA0000 {
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compatible = "qcom,lpass-cdc-wsa2-macro";
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reg = <0x6AA0000 0x0>;
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wsa_data_fs_ctl_reg = <0x6B6F000>;
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qcom,wsa2-swr-gpios = <&wsa2_swr_gpios>;
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qcom,wsa-bat-cfgs= <1>, <1>;
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qcom,wsa-rloads= <2>, <2>;
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qcom,wsa-system-gains= <0 9>, <0 9>;
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qcom,wsa2-bcl-pmic-params = /bits/ 8 <0x00 0x03 0x48>;
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qcom,default-clk-id = <WSA2_TX_CORE_CLK>;
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qcom,thermal-max-state = <11>;
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qcom,noise-gate-mode = <2>;
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#cooling-cells = <2>;
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status = "disabled";
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swr3: wsa2_swr_master {
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compatible = "qcom,swr-mstr";
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#address-cells = <2>;
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#size-cells = <0>;
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clock-names = "lpass_core_hw_vote",
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"lpass_audio_hw_vote";
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clocks = <&lpass_core_hw_vote 0>,
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<&lpass_audio_hw_vote 0>;
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qcom,swr_master_id = <4>;
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qcom,mipi-sdw-block-packing-mode = <0>;
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swrm-io-base = <0x6ab0000 0x0>;
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interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "swr_master_irq";
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qcom,swr-num-ports = <13>;
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qcom,swr-clock-stop-mode0 = <1>;
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qcom,swr-port-mapping = <1 SPKR_L 0x1>,
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<2 SPKR_L_COMP 0xF>, <3 SPKR_L_BOOST 0x3>,
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<4 SPKR_R 0x1>, <5 SPKR_R_COMP 0xF>,
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<6 SPKR_R_BOOST 0x3>, <7 PBR 0x3>,
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<8 SPKR_HAPT 0x3>, <9 OCPM 0x3>,
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<10 SPKR_L_VI 0x3>, <11 SPKR_R_VI 0x3>,
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<12 SPKR_IPCM 0x3>, <13 CPS 0x3>;
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qcom,swr-num-dev = <2>;
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qcom,dynamic-port-map-supported = <0>;
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wsa884x_2_0220: wsa884x@02170220 {
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compatible = "qcom,wsa884x_2";
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reg = <0x4 0x2170220>;
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qcom,spkr-sd-n-node = <&wsa_spkr_en02>;
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qcom,lpass-cdc-handle = <&lpass_cdc>;
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qcom,wsa-macro-handle = <&wsa2_macro>;
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qcom,swr-wsa-port-params =
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<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>, <OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>,
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<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>, <OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>,
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<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>, <OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>,
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<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>, <OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>;
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cdc-vdd-1p8-supply = <&L15B>;
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qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
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qcom,cdc-vdd-1p8-current = <20000>;
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qcom,cdc-vdd-1p8-lpm-supported = <1>;
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qcom,cdc-static-supplies = "cdc-vdd-1p8";
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sound-name-prefix = "Spkr2Left";
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};
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wsa884x_2_0221: wsa884x@02170221 {
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compatible = "qcom,wsa884x_2";
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reg = <0x4 0x2170221>;
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qcom,spkr-sd-n-node = <&wsa_spkr_en13>;
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qcom,lpass-cdc-handle = <&lpass_cdc>;
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qcom,wsa-macro-handle = <&wsa2_macro>;
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qcom,swr-wsa-port-params =
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<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>, <OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>, <OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>,
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<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>, <OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>, <OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>,
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<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>, <OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>, <OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>,
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<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>, <OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>, <OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>;
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cdc-vdd-1p8-supply = <&L15B>;
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qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
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qcom,cdc-vdd-1p8-current = <20000>;
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qcom,cdc-vdd-1p8-lpm-supported = <1>;
|
||
qcom,cdc-static-supplies = "cdc-vdd-1p8";
|
||
sound-name-prefix = "Spkr2Right";
|
||
};
|
||
};
|
||
};
|
||
|
||
wcd939x_codec: wcd939x-codec {
|
||
compatible = "qcom,wcd939x-codec";
|
||
qcom,split-codec = <1>;
|
||
qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
|
||
<0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>,
|
||
<2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
|
||
<3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
|
||
<4 DSD_R 0x2 0 DSD_R>, <5 HIFI_PCM_L 0x1 0 HIFI_PCM_L>,
|
||
<5 HIFI_PCM_R 0x2 0 HIFI_PCM_R>;
|
||
|
||
qcom,tx_swr_ch_map = <0 ADC1 0x1 0 SWRM_TX1_CH1>,
|
||
<0 ADC2 0x2 0 SWRM_TX1_CH2>,
|
||
<1 ADC3 0x1 0 SWRM_TX1_CH3>,
|
||
<1 ADC4 0x2 0 SWRM_TX1_CH4>,
|
||
<2 DMIC0 0x1 0 SWRM_TX2_CH1>,
|
||
<2 DMIC1 0x2 0 SWRM_TX2_CH2>,
|
||
<2 MBHC 0x4 0 SWRM_TX2_CH3>,
|
||
<2 DMIC2 0x4 0 SWRM_TX2_CH3>,
|
||
<2 DMIC3 0x8 0 SWRM_TX2_CH4>,
|
||
<3 DMIC4 0x1 0 SWRM_TX3_CH1>,
|
||
<3 DMIC5 0x2 0 SWRM_TX3_CH2>,
|
||
<3 DMIC6 0x4 0 SWRM_TX3_CH3>,
|
||
<3 DMIC7 0x8 0 SWRM_TX3_CH4>;
|
||
|
||
qcom,swr-tx-port-params =
|
||
<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL0 LANE2>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,
|
||
<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,
|
||
<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL2 LANE0>,
|
||
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>;
|
||
|
||
qcom,wcd-rst-gpio-node = <&wcd939x_rst_gpio>;
|
||
qcom,rx-slave = <&wcd939x_rx_slave>;
|
||
qcom,tx-slave = <&wcd939x_tx_slave>;
|
||
|
||
cdc-vdd-rx-supply = <&L15B>;
|
||
qcom,cdc-vdd-rx-voltage = <1800000 1800000>;
|
||
qcom,cdc-vdd-rx-current = <30000>;
|
||
qcom,cdc-vdd-rx-lpm-supported = <1>;
|
||
|
||
cdc-vdd-tx-supply = <&L15B>;
|
||
qcom,cdc-vdd-tx-voltage = <1800000 1800000>;
|
||
qcom,cdc-vdd-tx-current = <30000>;
|
||
qcom,cdc-vdd-tx-lpm-supported = <1>;
|
||
|
||
cdc-vdd-buck-supply = <&L15B>;
|
||
qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
|
||
qcom,cdc-vdd-buck-current = <650000>;
|
||
qcom,cdc-vdd-buck-lpm-supported = <1>;
|
||
|
||
cdc-vdd-mic-bias-supply = <&BOB1>;
|
||
qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>;
|
||
qcom,cdc-vdd-mic-bias-current = <30000>;
|
||
|
||
cdc-vdd-px-supply = <&L3C>;
|
||
qcom,cdc-vdd-px-voltage = <1200000 1200000>;
|
||
qcom,cdc-vdd-px-current = <5000>;
|
||
qcom,cdc-vdd-px-lpm-supported = <1>;
|
||
|
||
qcom,cdc-vdd-px-rem-supported = <1>;
|
||
|
||
qcom,cdc-micbias1-mv = <1800>;
|
||
qcom,cdc-micbias2-mv = <1800>;
|
||
qcom,cdc-micbias3-mv = <1800>;
|
||
qcom,cdc-micbias4-mv = <1800>;
|
||
|
||
qcom,cdc-static-supplies = "cdc-vdd-rx",
|
||
"cdc-vdd-tx",
|
||
"cdc-vdd-mic-bias";
|
||
qcom,cdc-on-demand-supplies = "cdc-vdd-buck",
|
||
"cdc-vdd-px";
|
||
};
|
||
|
||
};
|
||
|
||
&spf_core_platform {
|
||
pineapple_snd: sound {
|
||
qcom,model = "pineapple-mtp-snd-card";
|
||
qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>, <1>, <1>;
|
||
qcom,mi2s-tdm-is-hw-vote-needed = <1>, <1>, <1>, <1>, <1>, <1>, <1>;
|
||
qcom,wcn-bt = <1>;
|
||
qcom,ext-disp-audio-rx = <0>;
|
||
qcom,tdm-max-slots = <8>;
|
||
qcom,tdm-clk-attribute = <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>;
|
||
qcom,mi2s-clk-attribute = <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>;
|
||
qcom,audio-core-list = <0>, <1>;
|
||
qcom,audio-routing =
|
||
"AMIC1", "Analog Mic1",
|
||
"AMIC1", "MIC BIAS1",
|
||
"AMIC2", "Analog Mic2",
|
||
"AMIC2", "MIC BIAS2",
|
||
"AMIC3", "Analog Mic3",
|
||
"AMIC3", "MIC BIAS3",
|
||
"AMIC4", "Analog Mic4",
|
||
"AMIC4", "MIC BIAS3",
|
||
"AMIC5", "Analog Mic5",
|
||
"AMIC5", "MIC BIAS4",
|
||
"VA AMIC1", "Analog Mic1",
|
||
"VA AMIC1", "VA MIC BIAS1",
|
||
"VA AMIC2", "Analog Mic2",
|
||
"VA AMIC2", "VA MIC BIAS2",
|
||
"VA AMIC3", "Analog Mic3",
|
||
"VA AMIC3", "VA MIC BIAS3",
|
||
"VA AMIC4", "Analog Mic4",
|
||
"VA AMIC4", "VA MIC BIAS3",
|
||
"VA AMIC5", "Analog Mic5",
|
||
"VA AMIC5", "VA MIC BIAS4",
|
||
"TX DMIC0", "Digital Mic0",
|
||
"TX DMIC0", "MIC BIAS3",
|
||
"TX DMIC1", "Digital Mic1",
|
||
"TX DMIC1", "MIC BIAS3",
|
||
"TX DMIC2", "Digital Mic2",
|
||
"TX DMIC2", "MIC BIAS1",
|
||
"TX DMIC3", "Digital Mic3",
|
||
"TX DMIC3", "MIC BIAS1",
|
||
"IN1_HPHL", "HPHL_OUT",
|
||
"IN2_HPHR", "HPHR_OUT",
|
||
"IN3_EAR", "AUX_OUT",
|
||
"WSA SRC0_INP", "SRC0",
|
||
"WSA_TX DEC0_INP", "TX DEC0 MUX",
|
||
"WSA_TX DEC1_INP", "TX DEC1 MUX",
|
||
"RX_TX DEC0_INP", "TX DEC0 MUX",
|
||
"RX_TX DEC1_INP", "TX DEC1 MUX",
|
||
"RX_TX DEC2_INP", "TX DEC2 MUX",
|
||
"RX_TX DEC3_INP", "TX DEC3 MUX",
|
||
"SpkrLeft IN", "WSA_SPK1 OUT",
|
||
"SpkrRight IN", "WSA_SPK2 OUT",
|
||
"TX SWR_INPUT", "WCD_TX_OUTPUT",
|
||
"VA SWR_INPUT", "VA_SWR_CLK",
|
||
"VA SWR_INPUT", "WCD_TX_OUTPUT",
|
||
"VA_AIF1 CAP", "VA_SWR_CLK",
|
||
"VA_AIF2 CAP", "VA_SWR_CLK",
|
||
"VA_AIF3 CAP", "VA_SWR_CLK",
|
||
"VA DMIC0", "Digital Mic0",
|
||
"VA DMIC1", "Digital Mic1",
|
||
"VA DMIC2", "Digital Mic2",
|
||
"VA DMIC3", "Digital Mic3",
|
||
"VA DMIC0", "VA MIC BIAS3",
|
||
"VA DMIC1", "VA MIC BIAS3",
|
||
"VA DMIC2", "VA MIC BIAS1",
|
||
"VA DMIC3", "VA MIC BIAS1";
|
||
qcom,msm-mbhc-usbc-audio-supported = <0>;
|
||
qcom,msm-mbhc-hphl-swh = <1>;
|
||
qcom,msm-mbhc-gnd-swh = <1>;
|
||
|
||
qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>;
|
||
qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>;
|
||
qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>;
|
||
asoc-codec = <&stub_codec>, <&lpass_cdc>,
|
||
<&wcd939x_codec>, <&swr_haptics>,
|
||
<&wsa884x_0220>, <&wsa884x_0221>;
|
||
asoc-codec-names = "msm-stub-codec.1", "lpass-cdc",
|
||
"wcd939x_codec", "swr-haptics",
|
||
"wsa-codec1", "wsa-codec2";
|
||
qcom,wsa-max-devs = <2>;
|
||
qcom,msm_audio_ssr_devs = <&audio_gpr>, <&lpi_tlmm>,
|
||
<&lpass_cdc>;
|
||
|
||
/*
|
||
* ====================
|
||
* UPD backend - WSA
|
||
* ====================
|
||
*
|
||
* Mute/Unmute the interpolator
|
||
* ------------------------------
|
||
* Register: LPASS_WSA_CDC_RX0_RX_PATH_MIX_CTL - 0x6B00418
|
||
*
|
||
* Send control commands to the peripheral from the soundwire controller
|
||
* -----------------------------------------------------------------------
|
||
* Register: LPASS_WSA_SWR_MSTR_WSA_SWRM_CPUn_CMD_FIFO_WR_CMD - 0x6B14020
|
||
*
|
||
* Enable/Disable ear piece
|
||
* --------------------------
|
||
* Register: DIG_CTRL0_PA_FSM_EN - 0x3430
|
||
*
|
||
*/
|
||
qcom,upd_backends_used = "wsa";
|
||
qcom,upd_lpass_reg_addr = <0x6B00418 0x6B14020>;
|
||
qcom,upd_ear_pa_reg_addr = <0x3430>;
|
||
|
||
/*
|
||
* ====================
|
||
* UPD backend - WCD
|
||
* ====================
|
||
*
|
||
* Mute/Unmute the interpolator
|
||
* ------------------------------
|
||
* Register: LPASS_WCD_CDC_RX0_RX_PATH_MIX_CTL - 0x6AC0418
|
||
*
|
||
* Send control commands to the wcd from the soundwire controller
|
||
* ----------------------------------------------------------------
|
||
* Register: LPASS_WCD_SWR_MSTR_WSA_SWRM_CPUn_CMD_FIFO_WR_CMD - 0x6D34020
|
||
*
|
||
* Enable/Disable ear piece
|
||
* --------------------------
|
||
* Register: DIG_CTRL0_PA_FSM_EN - 0x300A
|
||
*
|
||
*/
|
||
/*
|
||
qcom,upd_backends_used = "wcd";
|
||
qcom,upd_lpass_reg_addr = <0x6AC0418 0x6D34020>;
|
||
qcom,upd_ear_pa_reg_addr = <0x300A>;
|
||
*/
|
||
};
|
||
|
||
cdc_pri_mi2s_gpios: pri_mi2s_pinctrl {
|
||
status = "disabled";
|
||
compatible = "qcom,msm-cdc-pinctrl";
|
||
pinctrl-names = "aud_active", "aud_sleep";
|
||
pinctrl-0 = <&i2s0_sck_active &i2s0_ws_active
|
||
&i2s0_sd0_active &i2s0_sd1_active>;
|
||
pinctrl-1 = <&i2s0_sck_sleep &i2s0_ws_sleep
|
||
&i2s0_sd0_sleep &i2s0_sd1_sleep>;
|
||
#gpio-cells = <0>;
|
||
};
|
||
|
||
fm_i2s1_gpios: fm_i2s1_pinctrl {
|
||
compatible = "qcom,msm-cdc-pinctrl";
|
||
pinctrl-names = "aud_active", "aud_sleep";
|
||
pinctrl-0 = <&i2s1_sck_active &i2s1_ws_active
|
||
&i2s1_sd0_active>;
|
||
pinctrl-1 = <&i2s1_sck_sleep &i2s1_ws_sleep
|
||
&i2s1_sd0_sleep>;
|
||
#gpio-cells = <0>;
|
||
};
|
||
|
||
cdc_tert_mi2s_gpios: tert_mi2s_pinctrl {
|
||
status = "disabled";
|
||
compatible = "qcom,msm-cdc-pinctrl";
|
||
pinctrl-names = "aud_active", "aud_sleep";
|
||
pinctrl-0 = <&lpi_i2s4_sck_active &lpi_i2s4_ws_active
|
||
&lpi_i2s4_sd0_active &lpi_i2s4_sd1_active>;
|
||
pinctrl-1 = <&lpi_i2s4_sck_sleep &lpi_i2s4_ws_sleep
|
||
&lpi_i2s4_sd0_sleep &lpi_i2s4_sd1_sleep>;
|
||
qcom,lpi-gpios;
|
||
qcom,tlmm-pins = <185 187>;
|
||
#gpio-cells = <0>;
|
||
};
|
||
|
||
cdc_quat_mi2s_gpios: quat_mi2s_pinctrl {
|
||
status = "disabled";
|
||
compatible = "qcom,msm-cdc-pinctrl";
|
||
pinctrl-names = "aud_active", "aud_sleep";
|
||
pinctrl-0 = <&quat_mi2s_sck_active &quat_mi2s_ws_active
|
||
&quat_mi2s_sd0_active &quat_mi2s_sd1_active
|
||
&quat_mi2s_sd2_active &quat_mi2s_sd3_active>;
|
||
pinctrl-1 = <&quat_mi2s_sck_sleep &quat_mi2s_ws_sleep
|
||
&quat_mi2s_sd0_sleep &quat_mi2s_sd1_sleep
|
||
&quat_mi2s_sd2_sleep &quat_mi2s_sd3_sleep>;
|
||
qcom,lpi-gpios;
|
||
qcom,tlmm-pins = <166 169>;
|
||
#gpio-cells = <0>;
|
||
};
|
||
|
||
cdc_quin_mi2s_gpios: quin_mi2s_pinctrl {
|
||
status = "disabled";
|
||
compatible = "qcom,msm-cdc-pinctrl";
|
||
pinctrl-names = "aud_active", "aud_sleep";
|
||
pinctrl-0 = <&lpi_i2s1_sck_active &lpi_i2s1_ws_active
|
||
&lpi_i2s1_sd0_active &lpi_i2s1_sd1_active>;
|
||
pinctrl-1 = <&lpi_i2s1_sck_sleep &lpi_i2s1_ws_sleep
|
||
&lpi_i2s1_sd0_sleep &lpi_i2s1_sd1_sleep>;
|
||
qcom,lpi-gpios;
|
||
qcom,tlmm-pins = <171 172 174>;
|
||
#gpio-cells = <0>;
|
||
};
|
||
|
||
cdc_sen_mi2s_gpios: sen_mi2s_pinctrl {
|
||
status = "disabled";
|
||
compatible = "qcom,msm-cdc-pinctrl";
|
||
pinctrl-names = "aud_active", "aud_sleep";
|
||
pinctrl-0 = <&lpi_i2s2_sck_active &lpi_i2s2_ws_active
|
||
&lpi_i2s2_sd0_active &lpi_i2s2_sd1_active>;
|
||
pinctrl-1 = <&lpi_i2s2_sck_sleep &lpi_i2s2_ws_sleep
|
||
&lpi_i2s2_sd0_sleep &lpi_i2s2_sd1_sleep>;
|
||
qcom,lpi-gpios;
|
||
qcom,tlmm-pins = <176 181>;
|
||
#gpio-cells = <0>;
|
||
};
|
||
|
||
cdc_sep_mi2s_gpios: sep_mi2s_pinctrl {
|
||
status = "disabled";
|
||
compatible = "qcom,msm-cdc-pinctrl";
|
||
pinctrl-names = "aud_active", "aud_sleep";
|
||
pinctrl-0 = <&lpi_i2s3_sck_active &lpi_i2s3_ws_active
|
||
&lpi_i2s3_sd0_active &lpi_i2s3_sd1_active>;
|
||
pinctrl-1 = <&lpi_i2s3_sck_sleep &lpi_i2s3_ws_sleep
|
||
&lpi_i2s3_sd0_sleep &lpi_i2s3_sd1_sleep>;
|
||
qcom,lpi-gpios;
|
||
qcom,tlmm-pins = <177 182>;
|
||
#gpio-cells = <0>;
|
||
};
|
||
|
||
wsa_swr_gpios: wsa_swr_clk_data_pinctrl {
|
||
compatible = "qcom,msm-cdc-pinctrl";
|
||
pinctrl-names = "aud_active", "aud_sleep";
|
||
pinctrl-0 = <&wsa_swr_clk_active &wsa_swr_data_active>;
|
||
pinctrl-1 = <&wsa_swr_clk_sleep &wsa_swr_data_sleep>;
|
||
qcom,lpi-gpios;
|
||
qcom,tlmm-pins = <176>;
|
||
#gpio-cells = <0>;
|
||
};
|
||
|
||
wsa2_swr_gpios: wsa2_swr_clk_data_pinctrl {
|
||
compatible = "qcom,msm-cdc-pinctrl";
|
||
pinctrl-names = "aud_active", "aud_sleep";
|
||
pinctrl-0 = <&wsa2_swr_clk_active &wsa2_swr_data_active>;
|
||
pinctrl-1 = <&wsa2_swr_clk_sleep &wsa2_swr_data_sleep>;
|
||
qcom,lpi-gpios;
|
||
qcom,tlmm-pins = <181>;
|
||
#gpio-cells = <0>;
|
||
};
|
||
|
||
rx_swr_gpios: rx_swr_clk_data_pinctrl {
|
||
compatible = "qcom,msm-cdc-pinctrl";
|
||
pinctrl-names = "aud_active", "aud_sleep";
|
||
pinctrl-0 = <&rx_swr_clk_active &rx_swr_data_active
|
||
&rx_swr_data1_active>;
|
||
pinctrl-1 = <&rx_swr_clk_sleep &rx_swr_data_sleep
|
||
&rx_swr_data1_sleep>;
|
||
qcom,lpi-gpios;
|
||
qcom,tlmm-pins = <169>;
|
||
#gpio-cells = <0>;
|
||
};
|
||
|
||
va_swr_gpios: tx_swr_clk_data_pinctrl {
|
||
compatible = "qcom,msm-cdc-pinctrl";
|
||
pinctrl-names = "aud_active", "aud_sleep";
|
||
pinctrl-0 = <&tx_swr_clk_active &tx_swr_data0_active
|
||
&tx_swr_data1_active &tx_swr_data2_active>;
|
||
pinctrl-1 = <&tx_swr_clk_sleep &tx_swr_data0_sleep
|
||
&tx_swr_data1_sleep &tx_swr_data2_sleep>;
|
||
qcom,lpi-gpios;
|
||
qcom,chip-wakeup-reg = <0xf1a6008>;
|
||
qcom,chip-wakeup-maskbit = <7>;
|
||
qcom,chip-wakeup-default-val = <0x1>;
|
||
qcom,tlmm-pins = <166>;
|
||
#gpio-cells = <0>;
|
||
};
|
||
|
||
cdc_dmic01_gpios: cdc_dmic01_pinctrl {
|
||
compatible = "qcom,msm-cdc-pinctrl";
|
||
pinctrl-names = "aud_active", "aud_sleep";
|
||
pinctrl-0 = <&cdc_dmic01_clk_active &cdc_dmic01_data_active>;
|
||
pinctrl-1 = <&cdc_dmic01_clk_sleep &cdc_dmic01_data_sleep>;
|
||
qcom,lpi-gpios;
|
||
qcom,tlmm-pins = <171 172>;
|
||
#gpio-cells = <0>;
|
||
};
|
||
|
||
cdc_dmic23_gpios: cdc_dmic23_pinctrl {
|
||
compatible = "qcom,msm-cdc-pinctrl";
|
||
pinctrl-names = "aud_active", "aud_sleep";
|
||
pinctrl-0 = <&cdc_dmic23_clk_active &cdc_dmic23_data_active>;
|
||
pinctrl-1 = <&cdc_dmic23_clk_sleep &cdc_dmic23_data_sleep>;
|
||
qcom,lpi-gpios;
|
||
qcom,tlmm-pins = <174>;
|
||
#gpio-cells = <0>;
|
||
};
|
||
|
||
cdc_dmic45_gpios: cdc_dmic45_pinctrl {
|
||
compatible = "qcom,msm-cdc-pinctrl";
|
||
pinctrl-names = "aud_active", "aud_sleep";
|
||
pinctrl-0 = <&cdc_dmic45_clk_active &cdc_dmic45_data_active>;
|
||
pinctrl-1 = <&cdc_dmic45_clk_sleep &cdc_dmic45_data_sleep>;
|
||
qcom,lpi-gpios;
|
||
qcom,tlmm-pins = <177>;
|
||
#gpio-cells = <0>;
|
||
};
|
||
|
||
cdc_dmic67_gpios: cdc_dmic67_pinctrl {
|
||
compatible = "qcom,msm-cdc-pinctrl";
|
||
pinctrl-names = "aud_active", "aud_sleep";
|
||
pinctrl-0 = <&cdc_dmic67_clk_active &cdc_dmic67_data_active>;
|
||
pinctrl-1 = <&cdc_dmic67_clk_sleep &cdc_dmic67_data_sleep>;
|
||
qcom,lpi-gpios;
|
||
qcom,tlmm-pins = <182>;
|
||
#gpio-cells = <0>;
|
||
};
|
||
};
|
||
|
||
&soc {
|
||
wsa_spkr_en02: wsa_spkr_en1_pinctrl {
|
||
compatible = "qcom,msm-cdc-pinctrl";
|
||
pinctrl-names = "aud_active", "aud_sleep";
|
||
pinctrl-0 = <&spkr_02_sd_n_active>;
|
||
pinctrl-1 = <&spkr_02_sd_n_sleep>;
|
||
qcom,lpi-gpios;
|
||
};
|
||
|
||
wsa_spkr_en13: wsa_spkr_en2_pinctrl {
|
||
compatible = "qcom,msm-cdc-pinctrl";
|
||
pinctrl-names = "aud_active", "aud_sleep";
|
||
pinctrl-0 = <&spkr_13_sd_n_active>;
|
||
pinctrl-1 = <&spkr_13_sd_n_sleep>;
|
||
qcom,lpi-gpios;
|
||
};
|
||
|
||
wcd939x_rst_gpio: msm_cdc_pinctrl@32 {
|
||
compatible = "qcom,msm-cdc-pinctrl";
|
||
pinctrl-names = "aud_active", "aud_sleep";
|
||
pinctrl-0 = <&wcd939x_reset_active>;
|
||
pinctrl-1 = <&wcd939x_reset_sleep>;
|
||
};
|
||
|
||
clock_audio_va_1: va_core_clk {
|
||
compatible = "qcom,audio-ref-clk";
|
||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK>;
|
||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||
qcom,codec-lpass-clk-id = <0x307>;
|
||
#clock-cells = <1>;
|
||
};
|
||
|
||
clock_audio_wsa_1: wsa_core_clk {
|
||
compatible = "qcom,audio-ref-clk";
|
||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_2>;
|
||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||
qcom,codec-lpass-clk-id = <0x309>;
|
||
#clock-cells = <1>;
|
||
};
|
||
|
||
clock_audio_wsa_2: wsa2_core_clk {
|
||
compatible = "qcom,audio-ref-clk";
|
||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_9>;
|
||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||
qcom,codec-lpass-clk-id = <0x310>;
|
||
#clock-cells = <1>;
|
||
};
|
||
|
||
clock_audio_rx_1: rx_core_clk {
|
||
compatible = "qcom,audio-ref-clk";
|
||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_4>;
|
||
qcom,codec-lpass-ext-clk-freq = <22579200>;
|
||
qcom,codec-lpass-clk-id = <0x30E>;
|
||
#clock-cells = <1>;
|
||
};
|
||
|
||
clock_audio_rx_tx: rx_core_tx_clk {
|
||
compatible = "qcom,audio-ref-clk";
|
||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_10>;
|
||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||
qcom,codec-lpass-clk-id = <0x312>;
|
||
#clock-cells = <1>;
|
||
};
|
||
|
||
clock_audio_tx_1: tx_core_clk {
|
||
compatible = "qcom,audio-ref-clk";
|
||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_6>;
|
||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||
qcom,codec-lpass-clk-id = <0x30C>;
|
||
#clock-cells = <1>;
|
||
};
|
||
|
||
clock_audio_wsa_tx: wsa_core_tx_clk {
|
||
compatible = "qcom,audio-ref-clk";
|
||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_11>;
|
||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||
qcom,codec-lpass-clk-id = <0x314>;
|
||
#clock-cells = <1>;
|
||
};
|
||
|
||
clock_audio_wsa2_tx: wsa2_core_tx_clk {
|
||
compatible = "qcom,audio-ref-clk";
|
||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_12>;
|
||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||
qcom,codec-lpass-clk-id = <0x316>;
|
||
#clock-cells = <1>;
|
||
};
|
||
|
||
clock_audio_rx_mclk2_2x_clk: rx_mclk2_2x_clk {
|
||
compatible = "qcom,audio-ref-clk";
|
||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_13>;
|
||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||
qcom,codec-lpass-clk-id = <0x318>;
|
||
#clock-cells = <1>;
|
||
};
|
||
};
|
||
|
||
&adsp_loader {
|
||
status = "ok";
|
||
};
|