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Merge "ARM: dts: msm: add support to configure hw-fence ctl reg offset"

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This commit is contained in:
qctecmdr
2024-02-05 09:23:13 -08:00
committed by Gerrit - the friendly Code Review server
parent b179caf787 945dccd0fd
commit 4872c166e5
2 changed files with 15 additions and 2 deletions
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6
bindings/sde.txt
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@@ -569,9 +569,13 @@ Optional properties:
silver or gold or gold+. silver or gold or gold+.
- qcom,sde-qos-cpu-dma-latency: A u32 value indicating desired PM QoS CPU DMA latency in usec. - qcom,sde-qos-cpu-dma-latency: A u32 value indicating desired PM QoS CPU DMA latency in usec.
- qcom,sde-qos-cpu-irq-latency: A u32 value indicating desired PM QoS CPU irq latency in usec. - qcom,sde-qos-cpu-irq-latency: A u32 value indicating desired PM QoS CPU irq latency in usec.
- qcom,sde-soccp-controller: The phandle for the soccp controller.
This value is optional and only required for targets with SOCCP.
- qcom,sde-ipcc-protocol-id: A u32 value indicating ipcc protocol id used for hw fencing feature. - qcom,sde-ipcc-protocol-id: A u32 value indicating ipcc protocol id used for hw fencing feature.
- qcom,sde-ipcc-client-dpu-phys-id: A u32 value indicating ipcc physical client id of dpu used - qcom,sde-ipcc-client-dpu-phys-id: A u32 value indicating ipcc physical client id of dpu used
for ipcc registers access. for ipcc registers access.
- qcom,sde-hw-fence-mdp-ctl-offset: An optional u32 value indicating the hw fence mdp reg
offset.
- qcom,sde-inline-rot-xin: An integer array of xin-ids related to inline - qcom,sde-inline-rot-xin: An integer array of xin-ids related to inline
rotation. rotation.
- qcom,sde-inline-rot-xin-type: A string array indicating the type of xin, - qcom,sde-inline-rot-xin-type: A string array indicating the type of xin,
@@ -911,8 +915,10 @@ Example:
qcom,sde-qos-cpu-dma-latency = <300>; qcom,sde-qos-cpu-dma-latency = <300>;
qcom,sde-qos-cpu-irq-latency = <300>; qcom,sde-qos-cpu-irq-latency = <300>;
qcom,sde-soccp-controller = <&soccp_pas>;
qcom,sde-ipcc-protocol-id = <0x2>; qcom,sde-ipcc-protocol-id = <0x2>;
qcom,sde-ipcc-client-dpu-phys-id = <0x19>; qcom,sde-ipcc-client-dpu-phys-id = <0x19>;
qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>;
qcom,sde-vbif-off = <0 0>; qcom,sde-vbif-off = <0 0>;
qcom,sde-vbif-id = <0 1>; qcom,sde-vbif-id = <0 1>;

11
display/sun-sde-common.dtsi
View File

@@ -12,10 +12,12 @@
compatible = "qcom,sde-kms"; compatible = "qcom,sde-kms";
reg = <0x0ae00000 0x93800>, reg = <0x0ae00000 0x93800>,
<0x0aeb0000 0x2008>, <0x0aeb0000 0x2008>,
<0x0af80000 0x7000>; <0x0af80000 0x7000>,
<0x400000 0x2000>;
reg-names = "mdp_phys", reg-names = "mdp_phys",
"vbif_phys", "vbif_phys",
"regdma_phys"; "regdma_phys",
"ipcc_reg";
/* interrupt config */ /* interrupt config */
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
@@ -261,6 +263,11 @@
qcom,sde-qos-cpu-dma-latency = <300>; qcom,sde-qos-cpu-dma-latency = <300>;
qcom,sde-qos-cpu-irq-latency = <300>; qcom,sde-qos-cpu-irq-latency = <300>;
qcom,sde-ipcc-protocol-id = <0x4>;
qcom,sde-ipcc-client-dpu-phys-id = <0x14>;
qcom,sde-soccp-controller = <&soccp_pas>;
qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>;
/* offsets are relative to "mdp_phys + qcom,sde-off */ /* offsets are relative to "mdp_phys + qcom,sde-off */
qcom,sde-reg-dma-off = <0 0x800>; qcom,sde-reg-dma-off = <0 0x800>;
qcom,sde-reg-dma-id = <0 1>; qcom,sde-reg-dma-id = <0 1>;