ARM: dts: msm: add support to configure hw-fence ctl reg offset

This change adds support for configuring mdp hw-fence ctl
register offset, as this value can change from target-to-target.

Change-Id: I436bec0732473c21cf4753cb292204ce618de512
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
This commit is contained in:
Christina Oliveira
2024-01-24 15:31:57 -08:00
parent febcd23b71
commit 945dccd0fd
2 changed files with 4 additions and 0 deletions

View File

@@ -574,6 +574,8 @@ Optional properties:
- qcom,sde-ipcc-protocol-id: A u32 value indicating ipcc protocol id used for hw fencing feature.
- qcom,sde-ipcc-client-dpu-phys-id: A u32 value indicating ipcc physical client id of dpu used
for ipcc registers access.
- qcom,sde-hw-fence-mdp-ctl-offset: An optional u32 value indicating the hw fence mdp reg
offset.
- qcom,sde-inline-rot-xin: An integer array of xin-ids related to inline
rotation.
- qcom,sde-inline-rot-xin-type: A string array indicating the type of xin,
@@ -916,6 +918,7 @@ Example:
qcom,sde-soccp-controller = <&soccp_pas>;
qcom,sde-ipcc-protocol-id = <0x2>;
qcom,sde-ipcc-client-dpu-phys-id = <0x19>;
qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>;
qcom,sde-vbif-off = <0 0>;
qcom,sde-vbif-id = <0 1>;

View File

@@ -266,6 +266,7 @@
qcom,sde-ipcc-protocol-id = <0x4>;
qcom,sde-ipcc-client-dpu-phys-id = <0x14>;
qcom,sde-soccp-controller = <&soccp_pas>;
qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>;
/* offsets are relative to "mdp_phys + qcom,sde-off */
qcom,sde-reg-dma-off = <0 0x800>;