From 945dccd0fde70ff85699e224ced366f2767de00a Mon Sep 17 00:00:00 2001 From: Christina Oliveira Date: Wed, 24 Jan 2024 15:31:57 -0800 Subject: [PATCH] ARM: dts: msm: add support to configure hw-fence ctl reg offset This change adds support for configuring mdp hw-fence ctl register offset, as this value can change from target-to-target. Change-Id: I436bec0732473c21cf4753cb292204ce618de512 Signed-off-by: Christina Oliveira --- bindings/sde.txt | 3 +++ display/sun-sde-common.dtsi | 1 + 2 files changed, 4 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index b334b16d..6ceef390 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -574,6 +574,8 @@ Optional properties: - qcom,sde-ipcc-protocol-id: A u32 value indicating ipcc protocol id used for hw fencing feature. - qcom,sde-ipcc-client-dpu-phys-id: A u32 value indicating ipcc physical client id of dpu used for ipcc registers access. +- qcom,sde-hw-fence-mdp-ctl-offset: An optional u32 value indicating the hw fence mdp reg + offset. - qcom,sde-inline-rot-xin: An integer array of xin-ids related to inline rotation. - qcom,sde-inline-rot-xin-type: A string array indicating the type of xin, @@ -916,6 +918,7 @@ Example: qcom,sde-soccp-controller = <&soccp_pas>; qcom,sde-ipcc-protocol-id = <0x2>; qcom,sde-ipcc-client-dpu-phys-id = <0x19>; + qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>; qcom,sde-vbif-off = <0 0>; qcom,sde-vbif-id = <0 1>; diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index 5d73da80..3300a722 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -266,6 +266,7 @@ qcom,sde-ipcc-protocol-id = <0x4>; qcom,sde-ipcc-client-dpu-phys-id = <0x14>; qcom,sde-soccp-controller = <&soccp_pas>; + qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>; /* offsets are relative to "mdp_phys + qcom,sde-off */ qcom,sde-reg-dma-off = <0 0x800>;