945dccd0fd
This change adds support for configuring mdp hw-fence ctl register offset, as this value can change from target-to-target. Change-Id: I436bec0732473c21cf4753cb292204ce618de512 Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
1138 lines
56 KiB
Plaintext
1138 lines
56 KiB
Plaintext
Qualcomm Technologies, Inc. SDE KMS
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Snapdragon Display Engine implements Linux DRM/KMS APIs to drive user
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interface to different panel interfaces. SDE driver is the core of
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display subsystem which manage all data paths to different panel interfaces.
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Required properties
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- compatible: Must be "qcom,sde-kms"
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- compatible: "msm-hdmi-audio-codec-rx";
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- reg: Offset and length of the register set for the device.
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- reg-names : Names to refer to register sets related to this device
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- clocks: List of Phandles for clock device nodes
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needed by the device.
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- clock-names: List of clock names needed by the device.
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- mmagic-supply: Phandle for mmagic mdss supply regulator device node.
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- vdd-supply: Phandle for vdd regulator device node.
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- interrupt-parent: Must be core interrupt controller.
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- interrupts: Interrupt associated with MDSS.
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- interrupt-controller: Mark the device node as an interrupt controller.
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- #interrupt-cells: Should be one. The first cell is interrupt number.
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- iommus: Specifies the SID's used by this context bank.
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- qcom,sde-sspp-type: Array of strings for SDE source surface pipes type information.
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A source pipe can be "vig", "rgb", "dma" or "cursor" type.
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Number of xin ids defined should match the number of offsets
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defined in property: qcom,sde-sspp-off.
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- qcom,sde-sspp-off: Array of offset for SDE source surface pipes. The offsets
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are calculated from register "mdp_phys" defined in
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reg property + "sde-off". The number of offsets defined here should
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reflect the amount of pipes that can be active in SDE for
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this configuration.
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- qcom,sde-sspp-xin-id: Array of VBIF clients ids (xins) corresponding
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to the respective source pipes. Number of xin ids
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defined should match the number of offsets
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defined in property: qcom,sde-sspp-off.
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- qcom,sde-ctl-off: Array of offset addresses for the available ctl
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hw blocks within SDE, these offsets are
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calculated from register "mdp_phys" defined in
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reg property. The number of ctl offsets defined
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here should reflect the number of control paths
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that can be configured concurrently on SDE for
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this configuration.
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- qcom,sde-wb-off: Array of offset addresses for the programmable
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writeback blocks within SDE.
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- qcom,sde-wb-xin-id: Array of VBIF clients ids (xins) corresponding
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to the respective writeback. Number of xin ids
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defined should match the number of offsets
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defined in property: qcom,sde-wb-off.
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- qcom,sde-mixer-off: Array of offset addresses for the available
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mixer blocks that can drive data to panel
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interfaces. These offsets are be calculated from
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register "mdp_phys" defined in reg property.
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The number of offsets defined should reflect the
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amount of mixers that can drive data to a panel
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interface.
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- qcom,sde-dspp-top-off: Offset address for the dspp top block.
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The offset is calculated from register "mdp_phys"
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defined in reg property.
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- qcom,sde-dspp-off: Array of offset addresses for the available dspp
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blocks. These offsets are calculated from
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register "mdp_phys" defined in reg property.
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- qcom,sde-pp-off: Array of offset addresses for the available
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pingpong blocks. These offsets are calculated
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from register "mdp_phys" defined in reg property.
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- qcom,sde-pp-slave: Array of flags indicating whether each ping pong
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block may be configured as a pp slave.
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- qcom,sde-pp-merge-3d-id: Array of index ID values for the merge 3d block
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connected to each pingpong, starting at 0.
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- qcom,sde-merge-3d-off: Array of offset addresses for the available
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merge 3d blocks. These offsets are calculated
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from register "mdp_phys" defined in reg property.
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- qcom,sde-intf-off: Array of offset addresses for the available SDE
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interface blocks that can drive data to a
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panel controller. The offsets are calculated
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from "mdp_phys" defined in reg property. The number
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of offsets defined should reflect the number of
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programmable interface blocks available in hardware.
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- qcom,sde-mixer-blend-op-off Array of offset addresses for the available
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blending stages. The offsets are relative to
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qcom,sde-mixer-off.
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- qcom,sde-mixer-pair-mask Array of mixer numbers that can be paired with
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mixer number corresponding to the array index.
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Optional properties:
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- clock-rate: List of clock rates in Hz.
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- clock-max-rate: List of maximum clock rate in Hz that this device supports.
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- clock-mmrm: List of clocks that enable setting the clk rate through MMRM driver.
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The order of the list must match the 'clocks' and 'clock-names' properties.
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The 'DISP_CC' ID of the clock must be used to enable the property for the
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respective clock, whereas a value of zero disables the property.
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- qcom,platform-supply-entries: A node that lists the elements of the supply. There
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can be more than one instance of this binding,
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in which case the entry would be appended with
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the supply entry index.
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e.g. qcom,platform-supply-entry@0
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-- reg: offset and length of the register set for the device.
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-- qcom,supply-name: name of the supply (vdd/vdda/vddio)
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-- qcom,supply-min-voltage: minimum voltage level (uV)
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-- qcom,supply-max-voltage: maximum voltage level (uV)
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-- qcom,supply-enable-load: load drawn (uA) from enabled supply
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-- qcom,supply-disable-load: load drawn (uA) from disabled supply
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-- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on
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-- qcom,supply-post-on-sleep: time to sleep (ms) after turning on
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-- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off
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-- qcom,supply-post-off-sleep: time to sleep (ms) after turning off
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- qcom,sde-hw-version: A u32 value indicates the MDSS hw version
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- qcom,sde-sspp-src-size: A u32 value indicates the address range for each sspp.
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- qcom,sde-mixer-size: A u32 value indicates the address range for each mixer.
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- qcom,sde-ctl-size: A u32 value indicates the address range for each ctl.
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- qcom,sde-dspp-size: A u32 value indicates the address range for each dspp.
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- qcom,sde-intf-size: A u32 value indicates the address range for each intf.
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- qcom,sde-dsc-size: A u32 value indicates the address range for each dsc.
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- qcom,sde-vdc-size: A u32 value indicates the address range for each vdc.
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- qcom,sde-cdm-size: A u32 value indicates the address range for each cdm.
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- qcom,sde-pp-size: A u32 value indicates the address range for each pingpong.
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- qcom,sde-merge-3d-size: A u32 value indicates the address range for each merge 3d.
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- qcom,sde-pp-cwb: Array of u32 flags indicating whether each ping pong
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block may be configured as a cwb pp block.
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- qcom,sde-wb-size: A u32 value indicates the address range for each writeback.
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- qcom,sde-len: A u32 entry for SDE address range.
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- qcom,sde-intf-max-prefetch-lines: Array of u32 values for max prefetch lines on
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each interface.
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- qcom,sde-sspp-linewidth: A u32 value indicates the max sspp line width.
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- qcom,sde-vig-sspp-linewidth: A u32 value indicates the max vig sspp line width.
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- qcom,sde-scaling-linewidth: A u32 value indicates the max vig source pipe line width
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for scaling purposes.
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- qcom,sde-mixer-linewidth: A u32 value indicates the max mixer line width.
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- qcom,sde-wb-linewidth: A u32 value indicates the max writeback line width.
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- qcom,sde-wb-linewidth-linear: A u32 value indicates the max line width
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supported by WB for linear color formats.
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- qcom,sde-sspp-scale-size: A u32 value indicates the scaling block size on sspp.
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- qcom,sde-mixer-blendstages: A u32 value indicates the max mixer blend stages for
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alpha blending.
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- qcom,sde-qseed-sw-lib-rev: A string entry indicates qseed sw library revision
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supporting the qseed HW block. It supports
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"qseedv3", "qseedv3lite" and "qseedv2" entries for qseed
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revision. By default "qseedv2" is used if this
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optional property is not defined.
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- qcom,sde-qseed-scalar-version: A u32 value indicating the HW version of the
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QSEED hardware block
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- qcom,sde-csc-type: A string entry indicates csc support on sspp and wb.
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It supports "csc" and "csc-10bit" entries for csc
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type.
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- qcom,sde-highest-bank-bit: Property to specify GPU/Camera/Video highest memory
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bank bit used for tile format buffers. First value
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in the array represents the ddr type and the second
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value is the hbb value corresponding to the ddr type.
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- qcom,sde-ubwc-version: Property to specify the UBWC feature version. A u32 UBWC version is based on MDSS support.
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- qcom,sde-ubwc-static: Property to specify the default UBWC static
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configuration value.
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- qcom,sde-ubwc-bw-calc-version: A u32 property to specify version of UBWC bandwidth
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calculation algorithm
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- qcom,sde-ubwc-swizzle: Property to specify the default UBWC swizzle
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configuration value.
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- qcom,sde-smart-panel-align-mode: A u32 property to specify the align mode for
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split display on smart panel. Possible values:
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0x0 - no alignment
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0xc - align at start of frame
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0xd - align at start of line
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- qcom,sde-panic-per-pipe: Boolean property to indicate if panic signal
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control feature is available on each source pipe.
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- qcom,sde-has-src-split: Boolean property to indicate if source split
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feature is available or not.
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- qcom,sde-has-dim-layer: Boolean property to indicate if mixer has dim layer
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feature is available or not.
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- qcom,sde-has-idle-pc: Boolean property to indicate if target has idle
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power collapse feature available or not.
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- qcom,sde-wakeup-with-touch: Boolean property to indicate if command mode display
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will exit from power collapse based on display input
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touch event or not.
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- qcom,sde-has-mixer-gc: Boolean property to indicate if mixer has gamma correction
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feature available or not.
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- qcom,sde-has-dest-scaler: Boolean property to indicate if destination scaler
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feature is available or not.
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- qcom,sde-max-dest-scaler-input-linewidth: A u32 value indicates the
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maximum input line width to destination scaler.
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- qcom,sde-max-dest-scaler-output-linewidth: A u32 value indicates the
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maximum output line width of destination scaler.
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- qcom,sde-dest-scaler-top-off: A u32 value provides the
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offset from mdp base to destination scaler block.
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- qcom,sde-dest-scaler-top-size: A u32 value indicates the address range for ds top
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- qcom,sde-dest-scaler-off: Array of u32 offsets indicate the qseed3 scaler blocks
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offset from destination scaler top offset.
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- qcom,sde-dest-scaler-size: A u32 value indicates the address range for each scaler block
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- qcom,sde-sspp-clk-ctrl: Array of offsets describing clk control
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offsets for dynamic clock gating. 1st value
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in the array represents offset of the control
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register. 2nd value represents bit offset within
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control register. Number of offsets defined should
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match the number of offsets defined in
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property: qcom,sde-sspp-off
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- qcom,sde-sspp-clk-status: Array of offsets describing clk status
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offsets for clock active state. 1st value
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in the array represents offset of the status
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register. 2nd value represents bit offset within
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status register. Number of offsets defined should
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match the number of offsets defined in
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property: qcom,sde-sspp-off.
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- qcom,sde-sspp-excl-rect: Array of u32 values indicating exclusion rectangle
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support on each sspp.
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- qcom,sde-sspp-smart-dma-priority: Array of u32 values indicating hw pipe
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priority of secondary rectangles when smart dma
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is supported. Number of priority values should
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match the number of offsets defined in
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qcom,sde-sspp-off node. Zero indicates no support
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for smart dma for the sspp.
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- qcom,sde-smart-dma-rev: A string entry indicating the smart dma version
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supported on the device. Supported entries are
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"smart_dma_v1" and "smart_dma_v2".
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- qcom,sde-vdc-hw-rev: A string indicating the hw version of vdc.
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- qcom,sde-intf-type: Array of string provides the interface type information.
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Possible string values
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"dsi" - dsi display interface
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"dp" - Display Port interface
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"hdmi" - HDMI display interface
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An interface is considered as "none" if interface type
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is not defined.
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- qcom,sde-intf-tear-irq-off Array of offset addresses for the available
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tear effect (TE) IRQ blocks from "mdp_phys".
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There should be one entry per INTF instance with
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a zero value for INTFs without TE IRQ block.
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- qcom,sde-emulated-env: Boolean property to indicate if the MDSS is running in an
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emulated environment.
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- qcom,sde-off: SDE offset from "mdp_phys" defined in reg property.
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- qcom,sde-cdm-off: Array of offset addresses for the available
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cdm blocks. These offsets will be calculated from
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register "mdp_phys" defined in reg property.
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- qcom,sde-vbif-off: Array of offset addresses for the available
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vbif blocks. These offsets will be calculated from
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register "vbif_phys" defined in reg property.
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- qcom,sde-vbif-size: A u32 value indicates the vbif block address range.
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- qcom,sde-uidle-off: A u32 value with the offset for the uidle
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block, from the "mdp_phys".
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- qcom,sde-uidle-size: A u32 value indicates the uidle block address range.
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- qcom,sde-te-off: A u32 offset indicates the te block offset on pingpong.
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This offset is 0x0 by default.
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- qcom,sde-te2-off: A u32 offset indicates the te2 block offset on pingpong.
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- qcom,sde-te-size: A u32 value indicates the te block address range.
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- qcom,sde-te2-size: A u32 value indicates the te2 block address range.
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- qcom,sde-dsc-off: Array of offset addresses for the available dsc
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blocks. These offsets are calculated from
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register "mdp_phys" defined in reg property.
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- qcom,sde-dsc-hw-rev: A string value indicates the dsc hw block
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version.
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- qcom,sde-dsc-enc: Array of offset addresses for the available dsc
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encoder blocks. These offsets are calculated from
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the corresponding DSC base.
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- qcom,sde-dsc-enc-size A u32 value indicates the enc block offset range.
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- qcom,sde-dsc-ctl: Array of offset addresses for the available dsc
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ctl blocks. These offsets are calculated from
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the corresponding DSC base.
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- qcom,sde-dsc-ctl-size A u32 value indicates the ctl block offset range.
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- qcom,sde-dsc-native422-supp: Array of flags indicating whether corresponding dsc
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block can support native 422 and native 420
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encoding.
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- qcom,sde-dsc-linewidth: A u32 value indicates the max dsc line width.
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- qcom,sde-vdc-off: A u32 offset address for the available vdc blocks.
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This offset is calculated from register "mdp_phys"
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defined in reg property.
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- qcom,sde-vdc-enc-size A u32 value indicates the enc block offset range.
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- qcom,sde-vdc-enc: A u32 offset address for the vdc encoder block. This offset is
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calculated from qcom,sde-vdc-off.
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- qcom,sde-vdc-ctl: A u32 offset address for the vdc ctl block. This offset is
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calculated from qcom,sde-vdc-off.
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- qcom,sde-vdc-ctl-size A u32 value indicates the ctl block offset range.
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- qcom,sde-qdss-off: A u32 offset indicates the qdss block offset.
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- qcom,sde-dither-off: A u32 offset indicates the dither block offset on pingpong.
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- qcom,sde-dither-version: A u32 value indicates the dither block version.
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- qcom,sde-dither-size: A u32 value indicates the dither block address range.
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- qcom,sde-cwb-dither: Array of u32 flags indicating whether each dither block
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may be configured as a cwb dither block.
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- qcom,sde-sspp-vig-blocks: A node that lists the blocks inside the VIG hardware. There can
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be more than one instance of this binding, in which case the
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entry would be appended with the vcm entry index. Each entry will
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contain the offset and version (if needed) of each feature block.
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The presence of a block entry indicates that the SSPP VIG contains
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that feature hardware.
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e.g. qcom,sde-sspp-vig-blocks
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-- vcm@0
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-- cell-index: A u32 index for the sub-block.
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-- qcom,sde-vig-top-off: A u32 offset of the sub-block top.
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-- qcom,sde-vig-csc-off: offset of CSC hardware
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-- qcom,sde-vig-qseed-off: offset of QSEED hardware
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-- qcom,sde-vig-qseed-size: A u32 address range for qseed scaler.
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-- qcom,sde-vig-pcc: offset and version of PCC hardware
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-- qcom,sde-vig-hsic: offset and version of global PA adjustment
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-- qcom,sde-vig-memcolor: offset and version of PA memcolor hardware
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-- qcom,sde-vig-gamut: offset and version of 3D LUT Gamut hardware
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-- qcom,sde-vig-igc: offset and version of 1D LUT IGC hardware
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-- qcom,sde-vig-inverse-pma: Boolean property to indicate if
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inverse PMA feature is available on VIG pipe
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-- qcom,sde-fp16-igc: u32 offset and version of the FP16 IGC hardware
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-- qcom,sde-fp16-unmult: u32 offset and version of the FP16 Unmult hardware
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-- qcom,sde-fp16-gc: u32 offset and version of the FP16 GC hardware
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-- qcom,sde-fp16-csc: u32 offset and version of the FP16 CSC hardware
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-- qcom,sde-ucsc-igc: u32 offset and version of the UCSC
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IGC hardware
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-- qcom,sde-ucsc-unmult: u32 offset and version of the UCSC
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Unmult hardware
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-- qcom,sde-ucsc-gc: u32 offset and version of the UCSC
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GC hardware
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-- qcom,sde-ucsc-csc: u32 offset and version of the UCSC
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CSC hardware
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-- qcom,sde-ucsc-alpha-dither: u32 offset and version of the UCSC
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Alpha Dither hardware
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- qcom,sde-sspp-dma-blocks: A node that lists the blocks inside the DMA hardware. There
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can be more than one instance of this binding, in which case the
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entry would be appended with dgm entry index. Each entry will
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contain the offset and version (if needed) of each feature block.
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The presence of a block entry indicates that the SSPP DMA contains
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that feature hardware.
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e.g. qcom,sde-sspp-dma-blocks
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-- dgm@0
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-- cell-index: A u32 index for the sub-block.
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-- qcom,sde-dma-top-off: A u32 offset of the sub-block top.
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-- qcom,sde-dma-igc: offset and version of DMA IGC
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-- qcom,sde-dma-gc: offset and version of DMA GC
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-- qcom,sde-dma-inverse-pma: Boolean property to indicate if
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inverse PMA feature is available on DMA pipe
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-- qcom,sde-dma-csc-off: offset of CSC hardware
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-- qcom,sde-fp16-igc: u32 offset and version of the FP16 IGC hardware
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-- qcom,sde-fp16-unmult: u32 offset and version of the FP16 Unmult hardware
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-- qcom,sde-fp16-gc: u32 offset and version of the FP16 GC hardware
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-- qcom,sde-fp16-csc: u32 offset and version of the FP16 CSC hardware
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-- qcom,sde-ucsc-igc: u32 offset and version of the UCSC
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IGC hardware
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-- qcom,sde-ucsc-unmult: u32 offset and version of the UCSC
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Unmult hardware
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-- qcom,sde-ucsc-gc: u32 offset and version of the UCSC
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GC hardware
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-- qcom,sde-ucsc-csc: u32 offset and version of the UCSC
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CSC hardware
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-- qcom,sde-ucsc-alpha-dither: u32 offset and version of the UCSC
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Alpha Dither hardware
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- qcom,sde-sspp-rgb-blocks: A node that lists the blocks inside the RGB hardware. The
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block entries will contain the offset and version (if needed)
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of each feature block. The presence of a block entry
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indicates that the SSPP RGB contains that feature hardware.
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e.g. qcom,sde-sspp-rgb-blocks
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-- qcom,sde-rgb-scaler-off: offset of RGB scaler hardware
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-- qcom,sde-rgb-scaler-size: A u32 address range for scaler.
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-- qcom,sde-rgb-pcc: offset and version of PCC hardware
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- qcom,sde-dspp-blocks: A node that lists the blocks inside the DSPP hardware. The
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block entries will contain the offset and version of each
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feature block. The presence of a block entry indicates that
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the DSPP contains that feature hardware.
|
|
e.g. qcom,sde-dspp-blocks
|
|
-- qcom,sde-dspp-pcc: offset and version of PCC hardware
|
|
-- qcom,sde-dspp-gc: offset and version of GC hardware
|
|
-- qcom,sde-dspp-igc: offset and version of IGC hardware
|
|
-- qcom,sde-dspp-hsic: offset and version of global PA adjustment
|
|
-- qcom,sde-dspp-memcolor: offset and version of PA memcolor hardware
|
|
-- qcom,sde-dspp-sixzone: offset and version of PA sixzone hardware
|
|
-- qcom,sde-dspp-gamut: offset and version of Gamut mapping hardware
|
|
-- qcom,sde-dspp-dither: offset and version of dither hardware
|
|
-- qcom,sde-dspp-hist: offset and version of histogram hardware
|
|
-- qcom,sde-dspp-vlut: offset and version of PA vLUT hardware
|
|
- qcom,sde-mixer-blocks: A node that lists the blocks inside the layer mixer hardware. The
|
|
block entries will contain the offset and version (if needed)
|
|
of each feature block. The presence of a block entry
|
|
indicates that the layer mixer contains that feature hardware.
|
|
e.g. qcom,sde-mixer-blocks
|
|
-- qcom,sde-mixer-gc: offset and version of mixer GC hardware
|
|
- qcom,sde-dspp-ad-off: Array of u32 offsets indicate the ad block offset from the
|
|
DSPP offset. Since AD hardware is represented as part of
|
|
DSPP block, the AD offsets must be offset from the
|
|
corresponding DSPP base.
|
|
- qcom,sde-dspp-ad-version A u32 value indicating the version of the AD hardware
|
|
- qcom,sde-dspp-ltm-version A u32 value indicating the major(upper 16 bits) and minor(lower 16 bits)
|
|
version of the LTM hardware
|
|
- qcom,sde-dspp-ltm-off: Array of u32 offsets indicate the LTM block offsets from the
|
|
DSPP offsets. Since LTM hardware is represented as part of
|
|
DSPP block, the LTM offsets are calculated based on the
|
|
corresponding DSPP base.
|
|
- qcom,sde-dspp-rc-version: A u32 value indicating the version of the RC hardware.
|
|
- qcom,sde-dspp-rc-off: Array of u32 offsets indicate the RC block offsets from the
|
|
DSPP offsets. Since RC hardware is represented as part of
|
|
DSPP block, the RC offsets are calculated based on the
|
|
corresponding DSPP base.
|
|
- qcom,sde-dspp-rc-size: A u32 value indicating the RC block address range.
|
|
- qcom,sde-dspp-rc-mem-size: A u32 value indicating the RC block shared memory size.
|
|
- qcom,sde-dspp-rc-min-region-width: A u32 value indicating the RC block minimum region width.
|
|
- qcom,sde-dspp-spr-off: Array of u32 offsets indicate the SPR block offsets from the
|
|
corresponding DSPP block offset as base.
|
|
- qcom,sde-dspp-spr-size: A u32 value indicating the SPR block register address range
|
|
- qcom,sde-dspp-spr-version: A u32 value indicating the version of SPR hardware.
|
|
- qcom,sde-dspp-demura-off: Array of u32 offsets indicate the demura block offsets from the
|
|
corresponding DSPP block offset as base.
|
|
- qcom,sde-dspp-demura-size: A u32 value indicating the demura block register address range
|
|
- qcom,sde-dspp-demura-version: A u32 value indicating the version of demura hardware.
|
|
- qcom,sde-dspp-aiqe-off: Array of u32 values indicating the offset of each AIQE block
|
|
relative to its parent DSPP block.
|
|
- qcom,sde-dspp-aiqe-version: A u32 value indicating the version of the AIQE hardware.
|
|
- qcom,sde-dspp-aiqe-size: A u32 value indicating the shared memory size of each AIQE
|
|
hardware block instance.
|
|
- qcom,sde-dspp-aiqe-dither-off: Array of u32 values indicating the offset of each AIQE
|
|
dither block relative to its parent DSPP block.
|
|
- qcom,sde-dspp-aiqe-dither-version: A u32 value indicating the version of the AIQE dither
|
|
hardware.
|
|
- qcom,sde-dspp-aiqe-dither-size: A u32 value indicating the shared memory size of each AIQE
|
|
dither hardware block instance.
|
|
- qcom,sde-dspp-aiqe-wrapper-off: Array of u32 values indicating the offset of each AIQE
|
|
wrapper block relative to its parent DSPP block.
|
|
- qcom,sde-dspp-aiqe-wrapper-version: A u32 value indicating the version of the AIQE wrapper
|
|
hardware.
|
|
- qcom,sde-dspp-aiqe-wrapper-size: A u32 value indicating the shared memory size of each AIQE
|
|
wrapper hardware block instance.
|
|
- qcom,sde-dspp-aiqe-aiscaler-off: Array of u32 values indicating the offset of each AIQE
|
|
AI Scaler block relative to its parent DSPP block.
|
|
- qcom,sde-dspp-aiqe-aiscaler-version: A u32 value indicating the version of the AIQE AI Scaler
|
|
hardware.
|
|
- qcom,sde-dspp-aiqe-aiscaler-size: A u32 value indicating the shared memory size of each AIQE
|
|
AI Scaler hardware block instance.
|
|
- qcom,sde-aiqe-has-feature-mdnie: Boolean property indicating the presence of AIQE feature mDNIe
|
|
hardware.
|
|
- qcom,sde-aiqe-has-feature-abc: Boolean property indicating the presence of AIQE feature ABC
|
|
hardware.
|
|
- qcom,sde-aiqe-has-feature-ssrc: Boolean property indicating the presence of AIQE feature SSRC
|
|
hardware.
|
|
- qcom,sde-aiqe-has-feature-copr: Boolean property indicating the presence of AIQE feature COPR
|
|
hardware.
|
|
- qcom,sde-aiqe-has-feature-aiscaler: Boolean property indicating the presence of AIQE feature
|
|
AI Scaler hardware.
|
|
- qcom,sde-lm-noise-off: A u32 value indicating noise layer offset from mixer base.
|
|
- qcom,sde-lm-noise-version: A u32 value indicating the noise layer version.
|
|
- qcom,sde-vbif-id: Array of vbif ids corresponding to the
|
|
offsets defined in property: qcom,sde-vbif-off.
|
|
- qcom,sde-vbif-default-ot-rd-limit: A u32 value indicates the default read OT limit
|
|
- qcom,sde-vbif-default-ot-wr-limit: A u32 value indicates the default write OT limit
|
|
- qcom,sde-vbif-dynamic-ot-rd-limit: A series of 2 cell property, with a format
|
|
of (pps, OT limit), where pps is pixel per second and
|
|
OT limit is the read limit to apply if the given
|
|
pps is not exceeded.
|
|
- qcom,sde-vbif-dynamic-ot-wr-limit: A series of 2 cell property, with a format
|
|
of (pps, OT limit), where pps is pixel per second and
|
|
OT limit is the write limit to apply if the given
|
|
pps is not exceeded.
|
|
- qcom,sde-vbif-memtype-0: Array of u32 vbif memory type settings, group 0
|
|
- qcom,sde-vbif-memtype-1: Array of u32 vbif memory type settings, group 1
|
|
- qcom,sde-wb-id: Array of writeback ids corresponding to the
|
|
offsets defined in property: qcom,sde-wb-off.
|
|
- qcom,sde-wb-clk-ctrl: Array of 2 cell property describing clk control
|
|
offsets for dynamic clock gating. 1st value
|
|
in the array represents offset of the control
|
|
register. 2nd value represents bit offset within
|
|
control register. Number of offsets defined should
|
|
match the number of offsets defined in
|
|
property: qcom,sde-wb-off
|
|
- qcom,sde-wb-clk-status: Array of 2 cell property describing clk status
|
|
offsets for clock active state. 1st value
|
|
in the array represents offset of the status
|
|
register. 2nd value represents bit offset within
|
|
status register. Number of offsets defined should
|
|
match the number of offsets defined in
|
|
property: qcom,sde-wb-off
|
|
- qcom,sde-reg-dma-off: Array of u32 offset addresses of the dma hardware blocks,
|
|
relative to "regdma_phys" defined in reg property.
|
|
- qcom,sde-reg-dma-id: Array of u32 DMA block type ids corresponding to the
|
|
offsets declared in property: qcom,sde-reg-dma-off
|
|
- qcom,sde-reg-dma-version: Version of the reg dma hardware blocks.
|
|
- qcom,sde-reg-dma-trigger-off: Offset of the lut dma trigger reg from "mdp_phys"
|
|
defined in reg property.
|
|
- qcom,sde-reg-dma-broadcast-disabled: Boolean property to indicate if broadcast
|
|
functionality in the register dma hardware block should be used.
|
|
- qcom,sde-reg-dma-xin-id: VBIF clients id (xin) corresponding
|
|
to the LUTDMA block.
|
|
- qcom,sde-reg-dma-clk-ctrl: Array of 2 cell property describing clk control
|
|
offsets for dynamic clock gating. 1st value
|
|
in the array represents offset of the control
|
|
register. 2nd value represents bit offset within
|
|
control register.
|
|
- qcom,sde-dram-channels: This represents the number of channels in the
|
|
Bus memory controller.
|
|
- qcom,sde-num-nrt-paths: Integer property represents the number of non-realtime
|
|
paths in each Bus Scaling Usecase. This value depends on
|
|
number of AXI ports that are dedicated to non-realtime VBIF
|
|
for particular chipset.
|
|
These paths must be defined after rt-paths in
|
|
"qcom,msm-bus,vectors-KBps" vector request.
|
|
- qcom,sde-max-bw-low-kbps: This value indicates the max bandwidth in Kbps
|
|
that can be supported without underflow.
|
|
This is a low bandwidth threshold which should
|
|
be applied in most scenarios to be safe from
|
|
underflows when unable to satisfy bandwidth
|
|
requirements.
|
|
- qcom,sde-max-bw-high-kbps: This value indicates the max bandwidth in Kbps
|
|
that can be supported without underflow in the
|
|
event where there is no VFE.
|
|
This is a high bandwidth threshold which can be
|
|
applied in scenarios where panel interface can
|
|
be more tolerant to memory latency such as
|
|
command mode panels.
|
|
- qcom,sde-core-ib-ff: A string entry indicating the fudge factor for
|
|
core ib calculation.
|
|
- qcom,sde-core-clk-ff: A string entry indicating the fudge factor for
|
|
core clock calculation.
|
|
- qcom,sde-min-core-ib-kbps: This u32 value indicates the minimum mnoc ib
|
|
vote in Kbps that can be reduced without hitting underflow.
|
|
BW calculation logic will choose the IB bandwidth requirement
|
|
based on usecase if this floor value is not defined.
|
|
- qcom,sde-min-llcc-ib-kbps: This u32 value indicates the minimum llcc ib
|
|
vote in Kbps that can be reduced without hitting underflow.
|
|
BW calculation logic will choose the IB bandwidth requirement
|
|
based on usecase if this floor value is not defined.
|
|
- qcom,sde-min-dram-ib-kbps: This u32 value indicates the minimum dram ib
|
|
vote in Kbps that can be reduced without hitting underflow.
|
|
BW calculation logic will choose the IB bandwidth requirement
|
|
based on usecase if this floor value is not defined.
|
|
- qcom,sde-comp-ratio-rt: A string entry indicating the compression ratio
|
|
for each supported compressed format on realtime interface.
|
|
The string is composed of one or more of
|
|
<fourcc code>/<vendor code>/<modifier>/<compression ratio>
|
|
separated with spaces.
|
|
- qcom,sde-comp-ratio-nrt: A string entry indicating the compression ratio
|
|
for each supported compressed format on non-realtime interface.
|
|
The string is composed of one or more of
|
|
<fourcc code>/<vendor code>/<modifier>/<compression ratio>
|
|
separated with spaces.
|
|
- qcom,sde-undersized-prefill-lines: A u32 value indicates the size of undersized prefill in lines.
|
|
- qcom,sde-xtra-prefill-lines: A u32 value indicates the extra prefill in lines.
|
|
- qcom,sde-dest-scale-prefill-lines: A u32 value indicates the latency of destination scaler in lines.
|
|
- qcom,sde-macrotile-prefill-lines: A u32 value indicates the latency of macrotile in lines.
|
|
- qcom,sde-yuv-nv12-prefill-lines: A u32 value indicates the latency of yuv/nv12 in lines.
|
|
- qcom,sde-linear-prefill-lines: A u32 value indicates the latency of linear in lines.
|
|
- qcom,sde-downscaling-prefill-lines: A u32 value indicates the latency of downscaling in lines.
|
|
- qcom,sde-max-per-pipe-bw-kbps: Array of u32 value indicates the max per pipe bandwidth in Kbps.
|
|
- qcom,sde-amortizable-threshold: This value indicates the min for traffic shaping in lines.
|
|
- qcom,sde-vbif-qos-rt-remap: This u32 array is used to program vbif qos remapper register
|
|
priority for realtime clients. First 8 entries are for rp_remap and
|
|
the next 8 entries are for lvl_remap.
|
|
- qcom,sde-vbif-qos-nrt-remap: This u32 array is used to program vbif qos remapper register
|
|
priority for non-realtime clients. First 8 entries are for rp_remap and
|
|
the next 8 entries are for lvl_remap.
|
|
- qcom,sde-vbif-qos-cwb-remap: This u32 array is used to program vbif qos remapper register
|
|
priority for concurrent writeback clients. First 8 entries are
|
|
for rp_remap and the next 8 entries are for lvl_remap.
|
|
- qcom,sde-vbif-qos-lutdma-remap: This u32 array is used to program vbif qos remapper register
|
|
priority for lutdma client. First 8 entries are for rp_remap and
|
|
the next 8 entries are for lvl_remap.
|
|
- qcom,sde-vbif-qos-cnoc-remap: This u32 array is used to program vbif qos remapper register
|
|
priority for cnoc clients. First 8 entries are for rp_remap and
|
|
the next 8 entries are for lvl_remap.
|
|
- qcom,sde-vbif-qos-offline-wb-remap: This u32 array is used to program vbif qos remapper register
|
|
priority for offline-wb clients. First 8 entries are for rp_remap
|
|
and the next 8 entries are for lvl_remap.
|
|
- qcom,sde-vbif-qos-wb-rot-remap: This u32 array is used to program vbif qos remapper register
|
|
priority for wb-rotation clients. First 8 entries are for rp_remap
|
|
and the next 8 entries are for lvl_remap.
|
|
- qcom,sde-qos-refresh-rates: This u32 array indicates danger, safe and creq luts
|
|
qos configuration for different refresh rates.
|
|
- qcom,sde-danger-lut: This u32 array of 18 cell property, with a format of
|
|
<portrait-panel, landscape-panel> for each entry,
|
|
<linear, tile, nrt, cwb-linear, cwb-tile, inline, inline-restricted,
|
|
offline-wb, wb_rotate>, indicating the danger luts on sspp and wb.
|
|
- qcom,sde-safe-lut: This u32 array of 18 cell property, with a format of
|
|
<portrait-panel, landscape-panel> for each entry,
|
|
<linear, tile, nrt, cwb-linear, cwb-tile, inline, inline-restricted,
|
|
offline-wb, wb_rotate>, indicating the safe luts on sspp and wb.
|
|
- qcom,sde-creq-lut: This u64 array of 18 cell property, with a format of
|
|
<lut hi, lut lo, lut hi with-qseed, lut lo with-qseed> for each
|
|
entry, for qos cases from <linear, tile, nrt, cwb-linear, cwb-tile,
|
|
inline, inline-restricted, offline-wb, wb_rotate>, with of-node count based
|
|
on the qos refresh rates count.
|
|
- qcom,sde-cdp-setting: Array of 2 cell property, with a format of
|
|
<read enable, write enable> for cdp use cases in
|
|
order of <real_time>, and <non_real_time>.
|
|
- qcom,sde-qos-cpu-mask: A u32 value indicating desired PM QoS CPU affine mask.
|
|
- qcom,sde-qos-cpu-mask-performance: Each bit represents a CPU mask. For example
|
|
0xf represents 4 cpu cores. These cores can be
|
|
silver or gold or gold+.
|
|
- qcom,sde-qos-cpu-dma-latency: A u32 value indicating desired PM QoS CPU DMA latency in usec.
|
|
- qcom,sde-qos-cpu-irq-latency: A u32 value indicating desired PM QoS CPU irq latency in usec.
|
|
- qcom,sde-soccp-controller: The phandle for the soccp controller.
|
|
This value is optional and only required for targets with SOCCP.
|
|
- qcom,sde-ipcc-protocol-id: A u32 value indicating ipcc protocol id used for hw fencing feature.
|
|
- qcom,sde-ipcc-client-dpu-phys-id: A u32 value indicating ipcc physical client id of dpu used
|
|
for ipcc registers access.
|
|
- qcom,sde-hw-fence-mdp-ctl-offset: An optional u32 value indicating the hw fence mdp reg
|
|
offset.
|
|
- qcom,sde-inline-rot-xin: An integer array of xin-ids related to inline
|
|
rotation.
|
|
- qcom,sde-inline-rot-xin-type: A string array indicating the type of xin,
|
|
namely sspp or wb. Number of entries should match
|
|
the number of xin-ids defined in
|
|
property: qcom,sde-inline-rot-xin
|
|
- qcom,sde-inline-rot-clk-ctrl: Array of offsets describing clk control
|
|
offsets for dynamic clock gating. 1st value
|
|
in the array represents offset of the control
|
|
register. 2nd value represents bit offset within
|
|
control register. Number of offsets defined should
|
|
match the number of xin-ids defined in
|
|
property: qcom,sde-inline-rot-xin
|
|
- qcom,sde-secure-sid-mask: Array of secure SID masks used during
|
|
secure-camera/secure-display usecases.
|
|
- #power-domain-cells: Number of cells in a power-domain specifier and should contain 0.
|
|
- #list-cells: Number of mdp cells, must be 1.
|
|
- qcom,sde-mixer-display-pref: A string array indicating the preferred display type
|
|
for the mixer block. Possible values:
|
|
"primary" - preferred for primary display
|
|
"none" - no preference on display
|
|
- qcom,sde-mixer-cwb-pref: A string array indicating the preferred mixer block.
|
|
for CWB. Possible values:
|
|
"cwb" - preferred for cwb
|
|
"none" - no preference on display
|
|
- qcom,sde-mixer-dcwb-pref: A string array indicating the preferred mixer block.
|
|
for Dedicated-CWB. Possible values:
|
|
"dcwb" - preferred for dedicated-cwb
|
|
"none" - no preference on display
|
|
- qcom,sde-ctl-display-pref: A string array indicating the preferred display type
|
|
for the ctl block. Possible values:
|
|
"primary" - preferred for primary display
|
|
"none" - no preference on display
|
|
- qcom,sde-pipe-order-version: A u32 property to indicate version of pipe
|
|
ordering block
|
|
0: lower priority pipe has to be on the left for a given pair of pipes.
|
|
1: priority have to be explicitly configured for a given pair of pipes.
|
|
- qcom,sde-trusted-vm-env: Boolean property to indicate if the device
|
|
driver is executing in a trusted VM
|
|
- qcom,sde-max-trusted-vm-displays: A u32 property to indicate the maximum
|
|
number of concurrent displays supported in the
|
|
trusted vm environment
|
|
- qcom,sde-vm-exclude-reg-names A string array indicating the reg-names which
|
|
should be excluded from IO memory validation list
|
|
in trusted vm environment
|
|
- qcom,tvm-include-reg An array of u32 tuplets indicating the address
|
|
ranges of the display sub-device registers
|
|
- qcom,vram-size: A u32 value indicating the size of the VRAM in bytes
|
|
- qcom,pmic-arb-address: A u32 array of display related SPMI address
|
|
bit mask, which is a combination of SID and pheripheral id's.
|
|
- qcom,sde-ib-bw-vote: A u32 array of IB bandwidth vote values in kbps for
|
|
MNOC, LLCC and DDR/EBI respectively.
|
|
- qcom,sde-dnsc-blur-version: A u32 value indicating the downscale blur version
|
|
- qcom,sde-dnsc-blur-off: An array of u32 values with the offset for the downscale blur
|
|
block, from the "mdp_phys".
|
|
- qcom,sde-dnsc-blur-size: A u32 value indicates the downscale blur block address range.
|
|
- qcom,sde-dnsc-blur-gaus-lut-off: An array of u32 values with the offset for gaussian LUT
|
|
block, from the dnsc-blur-off
|
|
- qcom,sde-dnsc-blur-gaus-lut-size: A u32 value indicates the gaussian LUT block address range.
|
|
- qcom,sde-dnsc-blur-dither-off: An array of u32 values with the offset for dither
|
|
block, from the dnsc-blur-off
|
|
- qcom,sde-dnsc-blur-dither-size: A u32 value indicates the dither block address range.
|
|
|
|
Bus Scaling:
|
|
- interconnects An array of 4 cell properties with the format of
|
|
(src-noc master-id dst-noc slave-id) as described in:
|
|
Documentation/devicetree/bindings/interconnect/interconnect.txt
|
|
One entry for each interconnect path available.
|
|
Master/Slave ID bindings can be found at:
|
|
include/dt-bindings/interconnect/
|
|
- interconnect-names An array of string properties associated with "interconnects"
|
|
each with a unique name used to lookup the respective path.
|
|
The following paths are currently supported: qcom,sde-reg-bus,
|
|
qcom,sde-data-bus0, qcom,sde-data-bus1, qcom,sde-llcc-bus,
|
|
qcom,sde-ebi-bus
|
|
- qcom,sde-reg-bus,vectors-KBps:A series of 2 cell properties with a format of
|
|
(ab, ib) specified in kilobytes-per-second.
|
|
Used when applying reg-bus votes and must be
|
|
given whenever "qcom,sde-reg-bus" is used.
|
|
- qcom,sde-inline-rotator: A 2 cell property, with format of (rotator phandle,
|
|
instance id), of inline rotator device.
|
|
|
|
SMMU Subnodes:
|
|
- smmu_sde_****: Child nodes representing sde smmu virtual
|
|
devices
|
|
|
|
Subnode properties:
|
|
- compatible: Compatible names used for smmu devices.
|
|
names should be:
|
|
"qcom,smmu_sde_unsec": smmu context bank device
|
|
for unsecure sde real time domain.
|
|
"qcom,smmu_sde_sec": smmu context bank device
|
|
for secure sde real time domain.
|
|
"qcom,smmu_sde_nrt_unsec": smmu context bank device
|
|
for unsecure sde non-real time domain.
|
|
"qcom,smmu_sde_nrt_sec": smmu context bank device
|
|
for secure sde non-real time domain.
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|
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|
Please refer to ../../interrupt-controller/interrupts.txt for a general
|
|
description of interrupt bindings.
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|
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|
Example:
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|
mdss_mdp: qcom,mdss_mdp@900000 {
|
|
compatible = "qcom,sde-kms";
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|
reg = <0x00900000 0x90000>,
|
|
<0x009b0000 0x1040>,
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|
<0x009b8000 0x1040>,
|
|
<0x0aeac000 0x00f0>;
|
|
reg-names = "mdp_phys",
|
|
"vbif_phys",
|
|
"vbif_nrt_phys",
|
|
"regdma_phys";
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|
qcom,tvm-include-reg = <0xaf20000 0x4d68>,
|
|
<0xaf30000 0x3fd4>;
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clocks = <&clock_mmss clk_mdss_ahb_clk>,
|
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<&clock_mmss clk_mdss_axi_clk>,
|
|
<&clock_mmss clk_mdp_clk_src>,
|
|
<&clock_mmss clk_mdss_mdp_vote_clk>,
|
|
<&clock_mmss clk_smmu_mdp_axi_clk>,
|
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<&clock_mmss clk_mmagic_mdss_axi_clk>,
|
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<&clock_mmss clk_mdss_vsync_clk>;
|
|
clock-names = "iface_clk",
|
|
"bus_clk",
|
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"core_clk_src",
|
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"core_clk",
|
|
"iommu_clk",
|
|
"mmagic_clk",
|
|
"vsync_clk";
|
|
clock-rate = <0>, <0>, <0>;
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clock-max-rate= <0 320000000 0>;
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clock-mmrm = <0 0 DISP_CC_MDSS_MDP_CLK_SRC 0 0 0 0>;
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mmagic-supply = <&gdsc_mmagic_mdss>;
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vdd-supply = <&gdsc_mdss>;
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interrupt-parent = <&intc>;
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interrupts = <0 83 0>;
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interrupt-controller;
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#interrupt-cells = <1>;
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iommus = <&mdp_smmu 0>;
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#power-domain-cells = <0>;
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qcom,sde-hw-version = <0x70000000>;
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qcom,sde-emulated-env;
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qcom,sde-off = <0x1000>;
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qcom,sde-ctl-off = <0x00002000 0x00002200 0x00002400
|
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0x00002600 0x00002800>;
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qcom,sde-ctl-display-pref = "primary", "none", "none",
|
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"none", "none";
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qcom,sde-mixer-off = <0x00045000 0x00046000
|
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0x00047000 0x0004a000>;
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qcom,sde-mixer-display-pref = "primary", "none",
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"none", "none";
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qcom,sde-mixer-cwb-pref = "none", "none",
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"cwb", "none";
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qcom,sde-dspp-top-off = <0x1300>;
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qcom,sde-dspp-off = <0x00055000 0x00057000>;
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qcom,sde-dspp-ad-off = <0x24000 0x22800>;
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qcom,sde-dspp-ad-version = <0x00030000>;
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qcom,sde-dspp-rc-version = <0x00010000>;
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qcom,sde-dspp-rc-off = <0x15800 0x14c00>;
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qcom,sde-dspp-rc-size = <0x100>;
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qcom,sde-dspp-rc-min-region-width = <20>;
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qcom,sde-dspp-spr-off = <0x15400 0x14400>;
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qcom,sde-dspp-spr-size = <0x200>;
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qcom,sde-dspp-spr-version = <0x00010000>:
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qcom,sde-dspp-demura-off = <0x15600 0x14800>;
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qcom,sde-dspp-demura-size = <0x200>;
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qcom,sde-dspp-demura-version = <0x00010000>;
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qcom,sde-lm-noise-off = <0x320>;
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qcom,sde-lm-noise-version = <0x00010000>;
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qcom,sde-dspp-aiqe-off = <0x39000 0xffffffff 0x3a000 0xffffffff>;
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qcom,sde-dspp-aiqe-version = <0x00010000>;
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qcom,sde-dspp-aiqe-size = <0x3fc>;
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qcom,sde-dspp-aiqe-dither-off = <0x39700 0xffffffff 0x3a700 0xffffffff>;
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qcom,sde-dspp-aiqe-dither-version = <0x00010000>;
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qcom,sde-dspp-aiqe-dither-size = <0x20>;
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qcom,sde-dspp-aiqe-wrapper-off = <0x39780 0xffffffff 0x3a780 0xffffffff>;
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qcom,sde-dspp-aiqe-wrapper-version = <0x00010000>;
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qcom,sde-dspp-aiqe-wrapper-size = <0x1c>;
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qcom,sde-aiqe-has-feature-mdnie;
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qcom,sde-aiqe-has-feature-abc;
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qcom,sde-aiqe-has-feature-ssrc;
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qcom,sde-aiqe-has-feature-copr;
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|
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qcom,sde-dspp-rc-mem-size = <2720>;
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qcom,sde-dest-scaler-top-off = <0x00061000>;
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qcom,sde-dest-scaler-off = <0x800 0x1000>;
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qcom,sde-wb-off = <0x00066000>;
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qcom,sde-wb-xin-id = <6>;
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qcom,sde-intf-off = <0x0006b000 0x0006b800
|
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0x0006c000 0x0006c800>;
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qcom,sde-intf-type = "none", "dsi", "dsi", "hdmi";
|
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qcom,sde-intf-tear-irq-off = <0 0x6e800 0x6e900 0>;
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qcom,sde-pp-off = <0x00071000 0x00071800
|
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0x00072000 0x00072800>;
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qcom,sde-pp-slave = <0x0 0x0 0x0 0x0>;
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qcom,sde-pp-cwb = <0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x1>;
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qcom,sde-cwb-dither = <0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x1>;
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qcom,sde-cdm-off = <0x0007a200>;
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qcom,sde-dsc-off = <0x00081000 0x00081400>;
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qcom,sde-vdc-off = <0x7C000>;
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qcom,sde-vdc-size = <0xf10>;
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qcom,sde-vdc-hw-rev = "vdc_1_2";
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qcom,sde-vdc-enc = <0x200>;
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qcom,sde-vdc-ctl = <0xf00>;
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qcom,sde-intf-max-prefetch-lines = <0x15 0x15 0x15 0x15>;
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qcom,sde-mixer-pair-mask = <2 1 6 0 0 3>;
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qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98
|
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0xb0 0xc8 0xe0 0xf8 0x110>;
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qcom,sde-qdss-off = <0x81a00>;
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qcom,sde-sspp-type = "vig", "vig", "vig",
|
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"vig", "rgb", "rgb",
|
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"rgb", "rgb", "dma",
|
|
"dma", "cursor", "cursor";
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|
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qcom,sde-sspp-off = <0x00005000 0x00007000 0x00009000
|
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0x0000b000 0x00015000 0x00017000
|
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0x00019000 0x0001b000 0x00025000
|
|
0x00027000 0x00035000 0x00037000>;
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|
|
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qcom,sde-sspp-xin-id = <0 4 8
|
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12 1 5
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9 13 2
|
|
10 7 7>;
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/* offsets are relative to "mdp_phys + qcom,sde-off */
|
|
qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2b4 0>, <0x2bc 0>,
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<0x2c4 0>, <0x2ac 4>, <0x2b4 4>, <0x2bc 4>,
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<0x2c4 4>, <0x2ac 8>, <0x2b4 8>, <0x3a8 16>,
|
|
<0x3b0 16>;
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qcom,sde-sspp-clk-status = <0x2ac 0>, <0x2b4 0>, <0x2bc 0>,
|
|
<0x2c4 0>, <0x2ac 4>, <0x2b4 4>, <0x2bc 4>,
|
|
<0x2c4 4>, <0x2ac 8>, <0x2b4 8>, <0x3a8 16>,
|
|
<0x3b0 16>;
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|
qcom,sde-scaling-linewidth = <2560>;
|
|
qcom,sde-mixer-linewidth = <2560>;
|
|
qcom,sde-sspp-linewidth = <2560>;
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|
qcom,sde-mixer-blendstages = <0x7>;
|
|
qcom,sde-dsc-linewidth = <2048>;
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|
qcom,sde-highest-bank-bit = <0x7 0x2>;
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|
qcom,sde-ubwc-version = <0x10000000>;
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|
qcom,sde-ubwc-static = <0x100>;
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|
qcom,sde-ubwc-swizzle = <0>;
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|
qcom,sde-ubwc-bw-calc-version = <0x1>;
|
|
qcom,sde-smart-panel-align-mode = <0xd>;
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|
qcom,sde-panic-per-pipe;
|
|
qcom,sde-has-src-split;
|
|
qcom,sde-pipe-order-version = <0x1>;
|
|
qcom,sde-has-dim-layer;
|
|
qcom,sde-sspp-src-size = <0x100>;
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|
qcom,sde-mixer-size = <0x100>;
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|
qcom,sde-ctl-size = <0x100>;
|
|
qcom,sde-dspp-top-size = <0xc>;
|
|
qcom,sde-dspp-size = <0x100>;
|
|
qcom,sde-intf-size = <0x100>;
|
|
qcom,sde-dsc-size = <0x100>;
|
|
qcom,sde-cdm-size = <0x100>;
|
|
qcom,sde-pp-size = <0x100>;
|
|
qcom,sde-wb-size = <0x100>;
|
|
qcom,sde-dest-scaler-top-size = <0xc>;
|
|
qcom,sde-dest-scaler-size = <0x800>;
|
|
qcom,sde-len = <0x100>;
|
|
qcom,sde-wb-linewidth = <2560>;
|
|
qcom,sde-wb-linewidth-linear = <5120>;
|
|
qcom,sde-sspp-scale-size = <0x100>;
|
|
qcom,sde-mixer-blendstages = <0x8>;
|
|
qcom,sde-qseed-sw-lib-rev = "qseedv2";
|
|
qcom,sde-qseed-scalar-version = <0x3000>;
|
|
qcom,sde-csc-type = "csc-10bit";
|
|
qcom,sde-highest-bank-bit = <15>;
|
|
qcom,sde-has-mixer-gc;
|
|
qcom,sde-has-idle-pc;
|
|
qcom,sde-wakeup-with-touch;
|
|
qcom,fullsize-va-map;
|
|
qcom,sde-has-dest-scaler;
|
|
qcom,sde-max-trusted-vm-displays = <1>;
|
|
qcom,sde-max-dest-scaler-input-linewidth = <2048>;
|
|
qcom,sde-max-dest-scaler-output-linewidth = <2560>;
|
|
qcom,sde-sspp-max-rects = <1 1 1 1
|
|
1 1 1 1
|
|
1 1
|
|
1 1>;
|
|
qcom,sde-sspp-excl-rect = <1 1 1 1
|
|
1 1 1 1
|
|
1 1
|
|
1 1>;
|
|
qcom,sde-sspp-smart-dma-priority = <0 0 0 0
|
|
0 0 0 0
|
|
0 0
|
|
1 2>;
|
|
qcom,sde-smart-dma-rev = "smart_dma_v2";
|
|
qcom,sde-te-off = <0x100>;
|
|
qcom,sde-te2-off = <0x100>;
|
|
qcom,sde-te-size = <0xffff>;
|
|
qcom,sde-te2-size = <0xffff>;
|
|
qcom,sde-trusted-vm-env;
|
|
|
|
qcom,sde-wb-id = <2>;
|
|
qcom,sde-wb-clk-ctrl = <0x2bc 16>;
|
|
qcom,sde-wb-clk-status = <0x3bc 20>;
|
|
|
|
qcom,sde-qos-refresh-rates = <60 120>;
|
|
qcom,sde-danger-lut = <0x3ffff 0x3ffff 0x0 0x0 0x0 0x3fffff 0x3fffff>,
|
|
<0x3ffffff 0x3ffffff 0x0 0x0 0x0 0x3ffffff 0x3fffff,
|
|
0xffff0000 0xffff0000>;
|
|
qcom,sde-safe-lut = <0xFE00 0xFE00 0xFFFF 0x01 0x03FF 0xF800 0xF800>,
|
|
<0xE000 0xE000 0xFFFF 0x01 0x03FF 0xE000 0xF800, 0xff,
|
|
0xff>;
|
|
qcom,sde-creq-lut = <0x00112234 0x45566777 0x00112236 0x67777777
|
|
0x00112234 0x45566777 0x00112236 0x67777777
|
|
0x0 0x0 0x0 0x0
|
|
0x77776666 0x66666540 0x77776666 0x66666540
|
|
0x77776541 0x00000000 0x77776541 0x00000000
|
|
0x00123445 0x56677777 0x00123667 0x77777777
|
|
0x00123445 0x56677777 0x00123667 0x77777777
|
|
0x55555544 0x33221100 0x55555544 0x33221100>,
|
|
<0x02344455 0x56667777 0x02366677 0x77777777
|
|
0x02344455 0x56667777 0x02366677 0x77777777
|
|
0x0 0x0 0x0 0x0
|
|
0x77776666 0x66666540 0x77776666 0x66666540
|
|
0x77776541 0x00000000 0x77776541 0x00000000
|
|
0x02344455 0x56667777 0x02366677 0x77777777
|
|
0x00123445 0x56677777 0x00123667 0x77777777
|
|
0x55555544 0x33221100 0x55555544 0x33221100>;
|
|
|
|
qcom,sde-cdp-setting = <1 1>, <1 0>;
|
|
|
|
qcom,sde-qos-cpu-mask = <0x3>;
|
|
qcom,sde-qos-cpu-mask-performance = <0xf>;
|
|
qcom,sde-qos-cpu-dma-latency = <300>;
|
|
qcom,sde-qos-cpu-irq-latency = <300>;
|
|
|
|
qcom,sde-soccp-controller = <&soccp_pas>;
|
|
qcom,sde-ipcc-protocol-id = <0x2>;
|
|
qcom,sde-ipcc-client-dpu-phys-id = <0x19>;
|
|
qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>;
|
|
|
|
qcom,sde-vbif-off = <0 0>;
|
|
qcom,sde-vbif-id = <0 1>;
|
|
qcom,sde-vbif-default-ot-rd-limit = <32>;
|
|
qcom,sde-vbif-default-ot-wr-limit = <16>;
|
|
qcom,sde-vbif-dynamic-ot-rd-limit = <62208000 2>,
|
|
<124416000 4>, <248832000 16>;
|
|
qcom,sde-vbif-dynamic-ot-wr-limit = <62208000 2>,
|
|
<124416000 4>, <248832000 16>;
|
|
qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
|
|
qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;
|
|
|
|
qcom,sde-uidle-off = <0x80000>;
|
|
qcom,sde-uidle-size = <0x70>;
|
|
|
|
qcom,sde-dram-channels = <2>;
|
|
qcom,sde-num-nrt-paths = <1>;
|
|
|
|
qcom,sde-max-bw-high-kbps = <9000000>;
|
|
qcom,sde-max-bw-low-kbps = <9000000>;
|
|
|
|
qcom,sde-core-ib-ff = "1.1";
|
|
qcom,sde-core-clk-ff = "1.0";
|
|
qcom,sde-min-core-ib-kbps = <2400000>;
|
|
qcom,sde-min-llcc-ib-kbps = <800000>;
|
|
qcom,sde-min-dram-ib-kbps = <800000>;
|
|
qcom,sde-comp-ratio-rt = "NV12/5/1/1.1 AB24/5/1/1.2 XB24/5/1/1.3";
|
|
qcom,sde-comp-ratio-nrt = "NV12/5/1/1.1 AB24/5/1/1.2 XB24/5/1/1.3";
|
|
qcom,sde-undersized-prefill-lines = <4>;
|
|
qcom,sde-xtra-prefill-lines = <5>;
|
|
qcom,sde-dest-scale-prefill-lines = <6>;
|
|
qcom,sde-macrotile-prefill-lines = <7>;
|
|
qcom,sde-yuv-nv12-prefill-lines = <8>;
|
|
qcom,sde-linear-prefill-lines = <9>;
|
|
qcom,sde-downscaling-prefill-lines = <10>;
|
|
qcom,sde-max-per-pipe-bw-kbps = <2400000 2400000 2400000 2400000
|
|
2400000 2400000 2400000 2400000>;
|
|
qcom,sde-amortizable-threshold = <11>;
|
|
qcom,sde-secure-sid-mask = <0x200801 0x200c01>;
|
|
|
|
qcom,sde-dnsc-blur-version = <0x100>;
|
|
qcom,sde-dnsc-blur-off = <0x7D000>;
|
|
qcom,sde-dnsc-blur-size = <0x40>;
|
|
qcom,sde-dnsc-blur-gaus-lut-off = <0x100>;
|
|
qcom,sde-dnsc-blur-gaus-lut-size = <0x400>;
|
|
qcom,sde-dnsc-blur-dither-off = <0x5E0>;
|
|
qcom,sde-dnsc-blur-dither-size = <0x20>;
|
|
|
|
qcom,vram-size = <0x200000>;
|
|
qcom,pmic-arb-address = <0x3F800 0x3F900 0x3FA00>;
|
|
|
|
qcom,sde-ib-bw-vote = <2500000 0 800000>;
|
|
|
|
qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6 3 3 4 4 5 5 6 6>;
|
|
qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>;
|
|
qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3 3 3 4 4 5 5 6 3>;
|
|
qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4 3 3 3 3 4 4 4 4>;
|
|
qcom,sde-vbif-qos-offline-wb-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>;
|
|
qcom,sde-vbif-qos-cnoc-remap = <3 3 4 4 5 5 5 5 3 3 3 3 3 3 3 3>;
|
|
qcom,sde-vbif-qos-wb-rot-remap = <4 4 5 5 5 5 5 6 4 4 5 5 5 5 5 6>;
|
|
|
|
qcom,sde-reg-dma-off = <0 0x400>;
|
|
qcom,sde-reg-dma-id = <0 1>;
|
|
qcom,sde-reg-dma-version = <0x00020000>;
|
|
qcom,sde-reg-dma-trigger-off = <0x119c>;
|
|
qcom,sde-reg-dma-broadcast-disabled = <0>;
|
|
qcom,sde-reg-dma-xin-id = <7>;
|
|
qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>;
|
|
|
|
qcom,sde-sspp-vig-blocks {
|
|
vcm@0 {
|
|
cell-index = <0>;
|
|
qcom,sde-vig-top-off = <0xa00>;
|
|
qcom,sde-vig-csc-off = <0x1a00>;
|
|
qcom,sde-vig-qseed-off = <0xa00>;
|
|
qcom,sde-vig-qseed-size = <0xe0>;
|
|
qcom,sde-vig-gamut = <0x1d00 0x00060001>;
|
|
qcom,sde-vig-igc = <0x1d00 0x00060000>;
|
|
/* Offset from vig top, version of HSIC */
|
|
qcom,sde-vig-hsic = <0x200 0x00010000>;
|
|
qcom,sde-vig-memcolor = <0x200 0x00010000>;
|
|
qcom,sde-vig-pcc = <0x1780 0x00010000>;
|
|
qcom,sde-vig-inverse-pma;
|
|
qcom,sde-fp16-igc = <0x200 0x00010000>;
|
|
qcom,sde-fp16-unmult = <0x200 0x00010000>;
|
|
qcom,sde-fp16-gc = <0x200 0x00010000>;
|
|
qcom,sde-fp16-csc = <0x200 0x00010000>;
|
|
qcom,sde-ucsc-igc = <0x700 0x00010000>;
|
|
qcom,sde-ucsc-unmult = <0x700 0x00010000>;
|
|
qcom,sde-ucsc-gc = <0x700 0x00010000>;
|
|
qcom,sde-ucsc-csc = <0x700 0x00010000>;
|
|
qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>;
|
|
};
|
|
|
|
vcm@1 {
|
|
cell-index = <1>;
|
|
qcom,sde-fp16-igc = <0x280 0x00010000>;
|
|
qcom,sde-fp16-unmult = <0x280 0x00010000>;
|
|
qcom,sde-fp16-gc = <0x280 0x00010000>;
|
|
qcom,sde-fp16-csc = <0x280 0x00010000>;
|
|
qcom,sde-ucsc-igc = <0x1700 0x00010000>;
|
|
qcom,sde-ucsc-unmult = <0x1700 0x00010000>;
|
|
qcom,sde-ucsc-gc = <0x1700 0x00010000>;
|
|
qcom,sde-ucsc-csc = <0x1700 0x00010000>;
|
|
qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>;
|
|
};
|
|
};
|
|
|
|
qcom,sde-sspp-dma-blocks {
|
|
dgm@0 {
|
|
cell-index = <0>;
|
|
qcom,sde-dma-top-off = <0x800>;
|
|
qcom,sde-dma-igc = <0x400 0x00050000>;
|
|
qcom,sde-dma-gc = <0x600 0x00050000>;
|
|
qcom,sde-dma-inverse-pma;
|
|
qcom,sde-dma-csc-off = <0x200>;
|
|
qcom,sde-fp16-igc = <0x200 0x00010000>;
|
|
qcom,sde-fp16-unmult = <0x200 0x00010000>;
|
|
qcom,sde-fp16-gc = <0x200 0x00010000>;
|
|
qcom,sde-fp16-csc = <0x200 0x00010000>;
|
|
qcom,sde-ucsc-igc = <0x700 0x00010000>;
|
|
qcom,sde-ucsc-unmult = <0x700 0x00010000>;
|
|
qcom,sde-ucsc-gc = <0x700 0x00010000>;
|
|
qcom,sde-ucsc-csc = <0x700 0x00010000>;
|
|
qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>;
|
|
};
|
|
|
|
dgm@1 {
|
|
cell-index = <1>;
|
|
qcom,sde-dma-igc = <0x1400 0x00050000>;
|
|
qcom,sde-dma-gc = <0x600 0x00050000>;
|
|
qcom,sde-dma-inverse-pma;
|
|
qcom,sde-dma-csc-off = <0x1200>;
|
|
qcom,sde-fp16-igc = <0x200 0x00010000>;
|
|
qcom,sde-fp16-unmult = <0x200 0x00010000>;
|
|
qcom,sde-fp16-gc = <0x200 0x00010000>;
|
|
qcom,sde-fp16-csc = <0x200 0x00010000>;
|
|
qcom,sde-ucsc-igc = <0x1700 0x00010000>;
|
|
qcom,sde-ucsc-unmult = <0x1700 0x00010000>;
|
|
qcom,sde-ucsc-gc = <0x1700 0x00010000>;
|
|
qcom,sde-ucsc-csc = <0x1700 0x00010000>;
|
|
qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>;
|
|
};
|
|
};
|
|
|
|
qcom,sde-sspp-rgb-blocks {
|
|
qcom,sde-rgb-scaler-off = <0x200>;
|
|
qcom,sde-rgb-scaler-size = <0x74>;
|
|
qcom,sde-rgb-pcc = <0x380 0x00010000>;
|
|
};
|
|
|
|
qcom,sde-dspp-blocks {
|
|
qcom,sde-dspp-igc = <0x0 0x00010000>;
|
|
qcom,sde-dspp-pcc = <0x1700 0x00010000>;
|
|
qcom,sde-dspp-gc = <0x17c0 0x00010000>;
|
|
qcom,sde-dspp-hsic = <0x0 0x00010000>;
|
|
qcom,sde-dspp-memcolor = <0x0 0x00010000>;
|
|
qcom,sde-dspp-sixzone = <0x0 0x00010000>;
|
|
qcom,sde-dspp-gamut = <0x1600 0x00010000>;
|
|
qcom,sde-dspp-dither = <0x0 0x00010000>;
|
|
qcom,sde-dspp-hist = <0x0 0x00010000>;
|
|
qcom,sde-dspp-vlut = <0x0 0x00010000>;
|
|
};
|
|
|
|
qcom,sde-mixer-blocks {
|
|
qcom,sde-mixer-gc = <0x3c0 0x00010000>;
|
|
};
|
|
|
|
qcom,msm-hdmi-audio-rx {
|
|
compatible = "qcom,msm-hdmi-audio-codec-rx";
|
|
};
|
|
|
|
qcom,sde-inline-rotator = <&mdss_rotator 0>;
|
|
qcom,sde-inline-rot-xin = <10 11>;
|
|
qcom,sde-inline-rot-xin-type = "sspp", "wb";
|
|
qcom,sde-inline-rot-clk-ctrl = <0x2bc 0x8>, <0x2bc 0xc>;
|
|
|
|
qcom,platform-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
qcom,platform-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "vdd";
|
|
qcom,supply-min-voltage = <0>;
|
|
qcom,supply-max-voltage = <0>;
|
|
qcom,supply-enable-load = <0>;
|
|
qcom,supply-disable-load = <0>;
|
|
qcom,supply-pre-on-sleep = <0>;
|
|
qcom,supply-post-on-sleep = <0>;
|
|
qcom,supply-pre-off-sleep = <0>;
|
|
qcom,supply-post-off-sleep = <0>;
|
|
};
|
|
};
|
|
|
|
interconnects = <&mmss_noc MASTER_MDP0 &mmss_noc SLAVE_MNOC_HF_MEM_NOC>
|
|
<&mmss_noc MASTER_MDP1 &mmss_noc SLAVE_MNOC_HF_MEM_NOC>,
|
|
<&gem_noc MASTER_MNOC_HF_MEM_NOC &gem_noc SLAVE_LLCC>,
|
|
<&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
|
|
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>;
|
|
interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1",
|
|
"qcom,sde-llcc-bus", "qcom,sde-ebi-bus", "qcom,sde-reg-bus";
|
|
qcom,sde-reg-bus,vectors-KBps = <0 0>,
|
|
<0 76800>,
|
|
<0 150000>,
|
|
<0 300000>;
|
|
|
|
smmu_kms_unsec: qcom,smmu_kms_unsec_cb {
|
|
compatible = "qcom,smmu_sde_unsec";
|
|
iommus = <&mmss_smmu 0>;
|
|
};
|
|
|
|
smmu_kms_sec: qcom,smmu_kms_sec_cb {
|
|
compatible = "qcom,smmu_sde_sec";
|
|
iommus = <&mmss_smmu 1>;
|
|
};
|
|
};
|