From 745316e53e8d59bdffb7b2091c4b28fa2569c5ea Mon Sep 17 00:00:00 2001 From: Christina Oliveira Date: Mon, 29 Jan 2024 14:19:45 -0800 Subject: [PATCH 1/3] ARM: dts: msm: add support for ipcc protocol for hw fence on sun This change adds the register address and size for ipcc base and the dpu client physical id to be used for hw fencing register access. Change-Id: I6a389626c186cc0f5a10900e890ecd33f6a606d2 Signed-off-by: Christina Oliveira --- display/sun-sde-common.dtsi | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index d8fe8840..36d306c0 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -12,10 +12,12 @@ compatible = "qcom,sde-kms"; reg = <0x0ae00000 0x93800>, <0x0aeb0000 0x2008>, - <0x0af80000 0x7000>; + <0x0af80000 0x7000>, + <0x400000 0x2000>; reg-names = "mdp_phys", "vbif_phys", - "regdma_phys"; + "regdma_phys", + "ipcc_reg"; /* interrupt config */ interrupts = ; @@ -261,6 +263,9 @@ qcom,sde-qos-cpu-dma-latency = <300>; qcom,sde-qos-cpu-irq-latency = <300>; + qcom,sde-ipcc-protocol-id = <0x4>; + qcom,sde-ipcc-client-dpu-phys-id = <0x14>; + /* offsets are relative to "mdp_phys + qcom,sde-off */ qcom,sde-reg-dma-off = <0 0x800>; qcom,sde-reg-dma-id = <0 1>; From febcd23b71babca9c5f838a7abdec2f1ca6acc75 Mon Sep 17 00:00:00 2001 From: Christina Oliveira Date: Wed, 24 Jan 2024 11:33:00 -0800 Subject: [PATCH 2/3] ARM: dts: msm: add soccp dtsi property to sun target This change adds the soccp phandle needed for SOCCP power vote for hw-fencing usecases. Change-Id: Ife59c04e9ba166493f7b7078e0b22848d2a444e2 Signed-off-by: Christina Oliveira --- bindings/sde.txt | 3 +++ display/sun-sde-common.dtsi | 1 + 2 files changed, 4 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index 779a3da7..b334b16d 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -569,6 +569,8 @@ Optional properties: silver or gold or gold+. - qcom,sde-qos-cpu-dma-latency: A u32 value indicating desired PM QoS CPU DMA latency in usec. - qcom,sde-qos-cpu-irq-latency: A u32 value indicating desired PM QoS CPU irq latency in usec. +- qcom,sde-soccp-controller: The phandle for the soccp controller. + This value is optional and only required for targets with SOCCP. - qcom,sde-ipcc-protocol-id: A u32 value indicating ipcc protocol id used for hw fencing feature. - qcom,sde-ipcc-client-dpu-phys-id: A u32 value indicating ipcc physical client id of dpu used for ipcc registers access. @@ -911,6 +913,7 @@ Example: qcom,sde-qos-cpu-dma-latency = <300>; qcom,sde-qos-cpu-irq-latency = <300>; + qcom,sde-soccp-controller = <&soccp_pas>; qcom,sde-ipcc-protocol-id = <0x2>; qcom,sde-ipcc-client-dpu-phys-id = <0x19>; diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index 36d306c0..5d73da80 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -265,6 +265,7 @@ qcom,sde-ipcc-protocol-id = <0x4>; qcom,sde-ipcc-client-dpu-phys-id = <0x14>; + qcom,sde-soccp-controller = <&soccp_pas>; /* offsets are relative to "mdp_phys + qcom,sde-off */ qcom,sde-reg-dma-off = <0 0x800>; From 945dccd0fde70ff85699e224ced366f2767de00a Mon Sep 17 00:00:00 2001 From: Christina Oliveira Date: Wed, 24 Jan 2024 15:31:57 -0800 Subject: [PATCH 3/3] ARM: dts: msm: add support to configure hw-fence ctl reg offset This change adds support for configuring mdp hw-fence ctl register offset, as this value can change from target-to-target. Change-Id: I436bec0732473c21cf4753cb292204ce618de512 Signed-off-by: Christina Oliveira --- bindings/sde.txt | 3 +++ display/sun-sde-common.dtsi | 1 + 2 files changed, 4 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index b334b16d..6ceef390 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -574,6 +574,8 @@ Optional properties: - qcom,sde-ipcc-protocol-id: A u32 value indicating ipcc protocol id used for hw fencing feature. - qcom,sde-ipcc-client-dpu-phys-id: A u32 value indicating ipcc physical client id of dpu used for ipcc registers access. +- qcom,sde-hw-fence-mdp-ctl-offset: An optional u32 value indicating the hw fence mdp reg + offset. - qcom,sde-inline-rot-xin: An integer array of xin-ids related to inline rotation. - qcom,sde-inline-rot-xin-type: A string array indicating the type of xin, @@ -916,6 +918,7 @@ Example: qcom,sde-soccp-controller = <&soccp_pas>; qcom,sde-ipcc-protocol-id = <0x2>; qcom,sde-ipcc-client-dpu-phys-id = <0x19>; + qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>; qcom,sde-vbif-off = <0 0>; qcom,sde-vbif-id = <0 1>; diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index 5d73da80..3300a722 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -266,6 +266,7 @@ qcom,sde-ipcc-protocol-id = <0x4>; qcom,sde-ipcc-client-dpu-phys-id = <0x14>; qcom,sde-soccp-controller = <&soccp_pas>; + qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>; /* offsets are relative to "mdp_phys + qcom,sde-off */ qcom,sde-reg-dma-off = <0 0x800>;