ARM: dts: msm: Add a node for gclk cycle counter driver

Add gclk cycle counter register information to devicetree in a
separate node for use by associated driver.

Change-Id: Ie27724dc04703d496a652729d61e03e0f4ff0115
Signed-off-by: Sai Harshini Nimmala <quic_snimmala@quicinc.com>

qcom/sun-walt.dtsi

@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+&soc {
+	walt {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		qcom,cycle-cntr {
+			compatible = "qcom,gclk";
+			reg = <0x18880400 0x8>,
+				<0x19880400 0x8>;
+			reg-names = "freq-domain0",
+				"freq-domain1";
+		};
+	};
+};

qcom/sun.dtsi

@@ -3154,6 +3154,7 @@
 #include "sun-thermal.dtsi"
 #include "sun-pcie.dtsi"
 #include "msm-rdbg.dtsi"
+#include "sun-walt.dtsi"
 
 &qupv3_se7_2uart {
 	status = "ok";